libdrm: Changes to 'debian-unstable'
ChangeLog | 309 +++++
configure.ac | 7
debian/changelog | 8
debian/libdrm-radeon1.symbols | 4
debian/libdrm2.symbols | 1
debian/rules | 4
include/drm/i915_drm.h | 37
include/drm/radeon_drm.h | 24
intel/Makefile.am | 1
intel/intel_bufmgr_gem.c | 20
intel/intel_decode.c | 1501 +++++++++++++------------
intel/tests/gen7-2d-copy.batch |binary
intel/tests/gen7-2d-copy.batch-ref.txt | 14
intel/tests/gen7-2d-copy.batch.sh | 1
intel/tests/gen7-3d.batch-ref.txt | 1922 ++++++++++++++-------------------
radeon/Makefile.am | 5
radeon/r600_pci_ids.h | 271 ++++
radeon/radeon_surface.c | 995 +++++++++++++++++
radeon/radeon_surface.h | 114 +
xf86drmMode.c | 21
xf86drmMode.h | 1
21 files changed, 3474 insertions(+), 1786 deletions(-)
New commits:
commit ef308a29b590f84a4283fe030ecaeeaeaca787bf
Author: Robert Hooker <sarvatt@ubuntu.com>
Date: Tue Feb 7 11:20:35 2012 -0500
Refresh libdrm2 and libdrm-radeon1 symbols, bump shlibs.
diff --git a/debian/changelog b/debian/changelog
index a3f910a..94e2d44 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,8 +1,10 @@
libdrm (2.4.31-1) UNRELEASED; urgency=low
* New upstream release.
+ * Bump libdrm2 and libdrm-radeon1 symbols and shlibs to account for
+ recent changes.
- -- Robert Hooker <sarvatt@ubuntu.com> Tue, 07 Feb 2012 10:54:39 -0500
+ -- Robert Hooker <sarvatt@ubuntu.com> Tue, 07 Feb 2012 11:06:32 -0500
libdrm (2.4.30-1) unstable; urgency=low
diff --git a/debian/libdrm-radeon1.symbols b/debian/libdrm-radeon1.symbols
index c900ea9..557be89 100644
--- a/debian/libdrm-radeon1.symbols
+++ b/debian/libdrm-radeon1.symbols
@@ -56,3 +56,7 @@ libdrm_radeon.so.1 libdrm-radeon1 #MINVER#
radeon_gem_get_reloc_in_cs@Base 2.4.20
radeon_gem_name_bo@Base 2.4.17
radeon_gem_set_domain@Base 2.4.17
+ radeon_surface_best@Base 2.4.31
+ radeon_surface_init@Base 2.4.31
+ radeon_surface_manager_free@Base 2.4.31
+ radeon_surface_manager_new@Base 2.4.31
diff --git a/debian/libdrm2.symbols b/debian/libdrm2.symbols
index 29ce302..0f70434 100644
--- a/debian/libdrm2.symbols
+++ b/debian/libdrm2.symbols
@@ -90,6 +90,7 @@ libdrm.so.2 libdrm2 #MINVER#
drmModeFreeFB@Base 2.4.3
drmModeFreeModeInfo@Base 2.4.3
drmModeFreePlane@Base 2.4.30
+ drmModeFreePlaneResources@Base 2.4.31
drmModeFreeProperty@Base 2.4.3
drmModeFreePropertyBlob@Base 2.4.3
drmModeFreeResources@Base 2.4.3
diff --git a/debian/rules b/debian/rules
index a620ec7..7857963 100755
--- a/debian/rules
+++ b/debian/rules
@@ -75,7 +75,7 @@ endif
dh_strip -s --remaining-packages
override_dh_makeshlibs:
- dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.30)' -- -c4
+ dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.31)' -- -c4
ifeq ($(INTEL), yes)
dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.30)' -- -c4
endif
@@ -83,7 +83,7 @@ ifeq ($(NOUVEAU), yes)
dh_makeshlibs -plibdrm-nouveau1a -V'libdrm-nouveau1a (>= 2.4.23)' -- -c4
endif
ifeq ($(RADEON), yes)
- dh_makeshlibs -plibdrm-radeon1 -V'libdrm-radeon1 (>= 2.4.20)' -- -c4
+ dh_makeshlibs -plibdrm-radeon1 -V'libdrm-radeon1 (>= 2.4.31)' -- -c4
endif
ifeq ($(LIBKMS), yes)
dh_makeshlibs -plibkms1 -V'libkms1' -- -c4
commit 1761b100e3e7b405bd8c12c92392a3c623081c9e
Author: Robert Hooker <sarvatt@ubuntu.com>
Date: Tue Feb 7 10:58:36 2012 -0500
Bump changelogs.
diff --git a/ChangeLog b/ChangeLog
index fe7581a..4d5e8df 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,312 @@
+commit 230ec7d7bbf1e8a7e263d471b21afb08c28eba0c
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Mon Feb 6 15:22:58 2012 -0500
+
+ configure: Bump version for 2.4.31
+
+commit 356b87d8b34daf9aeadd33465141bc212ad6e3ff
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Mon Feb 6 15:22:14 2012 -0500
+
+ radeon: add r600_pci_ids.h to header file
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit 10c0837780b2d4a33568c16bb92527e196d6c05e
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Fri Feb 3 12:22:11 2012 -0500
+
+ radeon: fix surface API for good before anyone start relying on it
+
+ The mipmap level computation was wrong, we need to know the block
+ width, height, depth of compressed texture to properly compute this.
+ Change API to provide block width, height, depth instead of nblk_x,
+ nblk_y, nblk_z.
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit 6a720cb8660975acea1100e61a88a92a7cb3856e
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Thu Feb 2 14:17:10 2012 -0500
+
+ radeon: surface fix macro -> micro tile fallback
+
+ We need to force 1D tiling only on old kernel the fallback was
+ broken along the way.
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit 76b4a69aab7cbfb4a087194b6d6ee182c1d5dd7e
+Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
+Date: Thu Feb 2 14:53:43 2012 -0500
+
+ Using sizeof() on a function parameter with an array type does not
+ work. sizeof() treats such parameters as pointers.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
+
+commit a14c3dd0f9c468d5dba86df5ffa786aea77068a9
+Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
+Date: Thu Feb 2 14:53:41 2012 -0500
+
+ This function was missing.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
+
+commit df497e9281036ca9397bc5a08a82fdf44dbc12b2
+Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
+Date: Thu Feb 2 14:53:39 2012 -0500
+
+ drmModeFreeResources() always leaked some memory.
+ drmModeGetPlaneResources() and drmModeGetPlane() leaked in one error
+ path.
+
+ Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
+
+commit c51f7f0e460dcadb9f1a56ecf1615810877c33c8
+Author: Jerome Glisse <jglisse@redhat.com>
+Date: Fri Dec 9 21:07:15 2011 -0500
+
+ radeon: add surface allocator helper v10
+
+ The surface allocator is able to build complete miptree when allocating
+ surface for r600/r700/evergreen/northern islands GPU family. It also
+ compute bo size and alignment for render buffer, depth buffer and
+ scanout buffer.
+
+ v2 fix r6xx/r7xx 2D tiling width align computation
+ v3 add tile split support and fix 1d texture alignment
+ v4 rework to more properly support compressed format, split surface pixel
+ size and surface element size in separate fields
+ v5 support texture array (still issue on r6xx)
+ v6 split surface value computation and mipmap tree building, rework eg
+ and newer computation
+ v7 add a check for tile split and 2d tiled
+ v8 initialize mode value before testing it in all case, reenable
+ 2D macro tile mode on r6xx for cubemap and array. Fix cubemap
+ to force array size to the number of face.
+ v9 fix handling of stencil buffer on evergreen
+ v10 on evergreen depth buffer need to have enough room for a stencil
+ buffer just after depth one
+
+ Signed-off-by: Jerome Glisse <jglisse@redhat.com>
+
+commit 151cdcfe685ee280a4344dfc40e6087d74a5590f
+Author: Eugeni Dodonov <eugeni.dodonov@intel.com>
+Date: Tue Jan 17 15:20:19 2012 -0200
+
+ intel: query for LLC support
+
+ This adds support for querying the kernel about the LLC support in the
+ hardware.
+
+ In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
+
+ v2: fix the return code checking
+
+ Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
+
+commit 82c6938d232327233caac743a07639ac91bceb7e
+Author: Paul Berry <stereotype441@gmail.com>
+Date: Tue Jan 31 14:44:14 2012 -0800
+
+ intel: Fix build of Intel DRM on x86 systems
+
+ Commit efd6e81e inadvertently broke the build by looking for "i?86" or
+ "x86_64" in $host_os. The correct variable to check is $host_cpu.
+
+ This was preventing libdrm_intel.so from being built.
+
+ Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
+
+commit efd6e81e2ba112105457887ae18a58dfa4bbc8ef
+Author: Jeremy Huddleston <jeremyhu@apple.com>
+Date: Mon Jan 30 15:20:04 2012 -0800
+
+ Don't build Intel DRM if $CHOST is not i?86-* or x86_64-*
+
+ This fixes a failure in 'make check' found by the tinderbox when trying to
+ build this code on Linux/ppc. This code is only designed to run on
+ Intel platforms, so don't even bother building it if we're not in that set.
+
+ Found-by: Tinderbox
+ Signed-off-by: Jeremy Huddleston <jeremyhu@apple.com>
+
+commit 592ac67626f6d69bd8b518a33e80e9c4d223eba2
+Author: Chad Versace <chad.versace@linux.intel.com>
+Date: Fri Jan 27 10:02:16 2012 -0800
+
+ intel: Fix bufmgr_gem->gen for gen > 4
+
+ If the pci_device's actual gen was > 4, then we stupidly set
+ bufmgr_gem->gen = 6. Luckily this caused no bugs, and this fix shouldn't
+ change any behavior, because all checks against the gen currently have one
+ of the forms below:
+ gen == 2
+ gen == 3
+ gen >= 4
+
+ Reviewed-by: Eric Anholt <eric@anholt.net>
+ Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
+ Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
+
+commit b643b0713aefdc0611e47654e88263b53b0de6f5
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 14:36:13 2012 -0800
+
+ intel: Add minimal decode for remaining gen7 packets in use.
+
+ This just gets packet name and length in place, with the remainder
+ unfinished. I've long since finished the work that got me started
+ fixing up the decode.
+
+commit 54b12a085f9e84368fd4ca664138be6ea4120ae2
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 13:41:55 2012 -0800
+
+ intel: Add decode for gen7 constant buffer packets.
+
+commit 938df6be489cb66c2f90043a8ced9834765e4e8e
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 12:23:42 2012 -0800
+
+ intel: Add decode for gen7 state pointers.
+
+ Since CC_STATE_POINTERS for gen6 and 7 are quite different but use the
+ same opcode, move gen6 out to a helper function too, so we can use a
+ helper function for gen7.
+
+commit 6a0b25e66b5515b3831db272211c337bcbdfb39a
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 12:12:41 2012 -0800
+
+ intel: Add support for parsing gen7 URB packets.
+
+commit ba8ce2da04daabacd598d7f049493b622ac96f58
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 13:18:42 2012 -0800
+
+ intel: Make most of the logic for 965 3d packet length checks table-driven.
+
+ This puts the error message in a consistent location relative to the
+ packet, and while I'm here I made the error message a bit more
+ informative.
+
+ Now, most static length packets need to just declare their length in
+ the table and not worry.
+
+commit b129e10af28016017a9c0e19af8e75a958063b5b
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 13:00:29 2012 -0800
+
+ intel: Move the logic for getting 965 3d packet length to the packet table.
+
+ While I'm touching every line of the table, sort it by opcode.
+
+commit 3dcb2d47ee9f3fe15f075e7eb1b80c0c625b4d69
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 12:06:44 2012 -0800
+
+ intel: Add support for parsing 965 3d packets using helper functions.
+
+ I want to add packets, without contributing to the switch statement of
+ doom.
+
+commit 5a1c10fe6a50c6b21e616bb77bfb00a9903cc517
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 12:01:49 2012 -0800
+
+ intel: Parse the correct length for gen7 3DSTATE_MULTISAMPLE.
+
+commit 9695eee8a2b6c749d79980e6057ac231aea6cb6d
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 12:00:59 2012 -0800
+
+ intel: Put the "gen" shorthand chipset identifier in the context.
+
+ It's a lot nicer than using IS_WHATEVER(devid) all over the place, and
+ we have this in our other projects too.
+
+commit 028715ee7074691895051296105e8b4cbbfaabb8
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 12:31:40 2012 -0800
+
+ intel: Avoid the need for most overflow checks by using a scratch page.
+
+ The overflow checks were all thoroughly untested, and a bunch of the
+ ones I'm deleting were pretty broken. Now, in the case of overflow,
+ you just decode data of 0xd0d0d0d0, and instr_out prints the warning
+ message instead. Note that this still has the same issue of being
+ under-tested, but at least it's one place instead of per-packet.
+
+ A couple of BUFFER_FAIL uses are left where the length to be decoded
+ could be (significantly) larger than a page, and the decode didn't
+ just call instr_out (which doesn't dereference data itself unless it's
+ safe).
+
+commit c1d2946da8f13ea8cbda1e33aeccee4d06015fea
+Author: Eric Anholt <eric@anholt.net>
+Date: Tue Dec 20 15:29:03 2011 -0800
+
+ intel: Make instr_out take the decode context.
+
+ This reduces some of the extra derefs of the pointers.
+
+commit b0371612f45229879c46d6a29adbe6939fbc97d4
+Author: Eric Anholt <eric@anholt.net>
+Date: Tue Dec 20 15:19:24 2011 -0800
+
+ intel: Use the context to simplify BR01 decode.
+
+ Similar to BR00, count was always 1 and was always an index, not a count.
+
+commit 62b410344c010d84ed75cc42e1aeaa6d23e8c396
+Author: Eric Anholt <eric@anholt.net>
+Date: Tue Dec 20 15:17:24 2011 -0800
+
+ intel: Use the context to simplify BR00 decode.
+
+ The count (actually index) was always 0, because BR00 is dword 0.
+
+commit de49fd41e26185da20a9de227e82ff71571f1a0a
+Author: Eric Anholt <eric@anholt.net>
+Date: Tue Dec 20 15:15:21 2011 -0800
+
+ intel: Plumb the context through the decode callchain.
+
+ We still deref the context at the start of every call, but that will
+ change next.
+
+commit a756fa384fdaaa0ae61075cb648554853a91bf22
+Author: Eric Anholt <eric@anholt.net>
+Date: Tue Dec 20 15:05:29 2011 -0800
+
+ intel: Drop the code for counting parsing failures.
+
+ Nothing was consuming it. If something wants this in the future,
+ would be done using the decode context anyway.
+
+commit 8fb66a7ded7efdb192a1dd09898e91487de493a3
+Author: Eric Anholt <eric@anholt.net>
+Date: Tue Dec 20 14:59:38 2011 -0800
+
+ intel: Track the current packet location in the decode context.
+
+ This is the start of plumbing the context through the decode
+ callchain instead of the current 4 arguments.
+
+commit b5cb7f88de249c6871b0e1d1e4005a7b1f54f088
+Author: Eric Anholt <eric@anholt.net>
+Date: Wed Jan 4 11:52:32 2012 -0800
+
+ intel: Add a regression test for 2D decode, which I'm about to refactor.
+
+commit 66518ab5653cfdc840cd69e7b653ec05df060584
+Author: Jesse Barnes <jbarnes@virtuousgeek.org>
+Date: Mon Jan 9 10:22:33 2012 -0800
+
+ intel: add sprite ioctl defines and struct for i915 sprite code
+
commit adf1428915bfd0ee24758a3cbd56ce9b64f6eefb
Author: Eric Anholt <eric@anholt.net>
Date: Fri Jan 6 08:50:31 2012 -0800
diff --git a/debian/changelog b/debian/changelog
index 3b92e88..a3f910a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+libdrm (2.4.31-1) UNRELEASED; urgency=low
+
+ * New upstream release.
+
+ -- Robert Hooker <sarvatt@ubuntu.com> Tue, 07 Feb 2012 10:54:39 -0500
+
libdrm (2.4.30-1) unstable; urgency=low
* New upstream release.
commit 230ec7d7bbf1e8a7e263d471b21afb08c28eba0c
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Feb 6 15:22:58 2012 -0500
configure: Bump version for 2.4.31
diff --git a/configure.ac b/configure.ac
index b59bc54..6784566 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.30],
+ [2.4.31],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 356b87d8b34daf9aeadd33465141bc212ad6e3ff
Author: Jerome Glisse <jglisse@redhat.com>
Date: Mon Feb 6 15:22:14 2012 -0500
radeon: add r600_pci_ids.h to header file
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
diff --git a/radeon/Makefile.am b/radeon/Makefile.am
index e64aff4..37be8cc 100644
--- a/radeon/Makefile.am
+++ b/radeon/Makefile.am
@@ -52,7 +52,8 @@ libdrm_radeoninclude_HEADERS = \
radeon_bo_gem.h \
radeon_cs_gem.h \
radeon_bo_int.h \
- radeon_cs_int.h
+ radeon_cs_int.h \
+ r600_pci_ids.h
pkgconfigdir = @pkgconfigdir@
pkgconfig_DATA = libdrm_radeon.pc
commit 10c0837780b2d4a33568c16bb92527e196d6c05e
Author: Jerome Glisse <jglisse@redhat.com>
Date: Fri Feb 3 12:22:11 2012 -0500
radeon: fix surface API for good before anyone start relying on it
The mipmap level computation was wrong, we need to know the block
width, height, depth of compressed texture to properly compute this.
Change API to provide block width, height, depth instead of nblk_x,
nblk_y, nblk_z.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index b2e5511..d7e9187 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -144,12 +144,12 @@ static void surf_minify(struct radeon_surface *surf,
uint32_t xalign, uint32_t yalign, uint32_t zalign,
unsigned offset)
{
- surf->level[level].nblk_x = mip_minify(surf->nblk_x, level);
- surf->level[level].nblk_y = mip_minify(surf->nblk_y, level);
- surf->level[level].nblk_z = mip_minify(surf->nblk_z, level);
surf->level[level].npix_x = mip_minify(surf->npix_x, level);
surf->level[level].npix_y = mip_minify(surf->npix_y, level);
surf->level[level].npix_z = mip_minify(surf->npix_z, level);
+ surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
+ surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
+ surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y < yalign) {
surf->level[level].mode = RADEON_SURF_MODE_1D;
@@ -499,12 +499,12 @@ static void eg_surf_minify(struct radeon_surface *surf,
{
unsigned mtile_pr, mtile_ps;
- surf->level[level].nblk_x = mip_minify(surf->nblk_x, level);
- surf->level[level].nblk_y = mip_minify(surf->nblk_y, level);
- surf->level[level].nblk_z = mip_minify(surf->nblk_z, level);
surf->level[level].npix_x = mip_minify(surf->npix_x, level);
surf->level[level].npix_y = mip_minify(surf->npix_y, level);
surf->level[level].npix_z = mip_minify(surf->npix_z, level);
+ surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w;
+ surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h;
+ surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d;
if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y < mtileh) {
surf->level[level].mode = RADEON_SURF_MODE_1D;
@@ -595,12 +595,6 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
/* macro tile bytes */
mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
- /* check if surface is big enought */
- if (surf->nblk_x < mtilew || surf->nblk_y < mtileh) {
- surf->level[start_level].mode = RADEON_SURF_MODE_1D;
- return eg_surface_init_1d(surf_man, surf, offset, start_level);
- }
-
if (!start_level) {
surf->bo_alignment = MAX2(256, mtileb);
}
@@ -610,7 +604,7 @@ static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
surf->level[i].mode = RADEON_SURF_MODE_2D;
eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset);
if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
- return r6_surface_init_1d(surf_man, surf, offset, i);
+ return eg_surface_init_1d(surf_man, surf, offset, i);
}
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
@@ -914,10 +908,7 @@ static int radeon_surface_sanity(struct radeon_surface_manager *surf_man,
if (!surf->npix_x || !surf->npix_y || !surf->npix_z) {
return -EINVAL;
}
- if (!surf->nblk_x || !surf->nblk_y || !surf->nblk_z) {
- return -EINVAL;
- }
- if (surf->npix_x < surf->nblk_x || surf->npix_y < surf->nblk_y || surf->npix_z < surf->nblk_z) {
+ if (!surf->blk_w || !surf->blk_h || !surf->blk_d) {
return -EINVAL;
}
if (!surf->array_size) {
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index 3e5fbed..bfee8ab 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -79,9 +79,9 @@ struct radeon_surface {
uint32_t npix_x;
uint32_t npix_y;
uint32_t npix_z;
- uint32_t nblk_x;
- uint32_t nblk_y;
- uint32_t nblk_z;
+ uint32_t blk_w;
+ uint32_t blk_h;
+ uint32_t blk_d;
uint32_t array_size;
uint32_t last_level;
uint32_t bpe;
commit 6a720cb8660975acea1100e61a88a92a7cb3856e
Author: Jerome Glisse <jglisse@redhat.com>
Date: Thu Feb 2 14:17:10 2012 -0500
radeon: surface fix macro -> micro tile fallback
We need to force 1D tiling only on old kernel the fallback was
broken along the way.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 0f01e2e..b2e5511 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -173,6 +173,7 @@ static void surf_minify(struct radeon_surface *surf,
static int r6_init_hw_info(struct radeon_surface_manager *surf_man)
{
uint32_t tiling_config;
+ drmVersionPtr version;
int r;
r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG,
@@ -181,6 +182,12 @@ static int r6_init_hw_info(struct radeon_surface_manager *surf_man)
return r;
}
+ surf_man->hw_info.allow_2d = 0;
+ version = drmGetVersion(surf_man->fd);
+ if (version && version->version_minor >= 14) {
+ surf_man->hw_info.allow_2d = 1;
+ }
+
switch ((tiling_config & 0xe) >> 1) {
case 0:
surf_man->hw_info.num_pipes = 1;
@@ -358,6 +365,13 @@ static int r6_surface_init(struct radeon_surface_manager *surf_man,
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
+ /* force 1d on kernel that can't do 2d */
+ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
+ mode = RADEON_SURF_MODE_1D;
+ surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
+ surf->flags |= RADEON_SURF_SET(mode, MODE);
+ }
+
/* check surface dimension */
if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) {
return -EINVAL;
@@ -629,69 +643,64 @@ static int eg_surface_sanity(struct radeon_surface_manager *surf_man,
return -EINVAL;
}
+ /* force 1d on kernel that can't do 2d */
+ if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
+ mode = RADEON_SURF_MODE_1D;
+ surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
+ surf->flags |= RADEON_SURF_SET(mode, MODE);
+ }
+
/* check tile split */
- switch (surf->tile_split) {
- case 0:
- if (mode == RADEON_SURF_MODE_2D) {
+ if (mode == RADEON_SURF_MODE_2D) {
+ switch (surf->tile_split) {
+ case 64:
+ case 128:
+ case 256:
+ case 512:
+ case 1024:
+ case 2048:
+ case 4096:
+ break;
+ default:
return -EINVAL;
}
- case 64:
- case 128:
- case 256:
- case 512:
- case 1024:
- case 2048:
- case 4096:
- break;
- default:
- return -EINVAL;
- }
- switch (surf->mtilea) {
- case 0:
- case 1:
- case 2:
- case 4:
- case 8:
- break;
- default:
- return -EINVAL;
- }
- /* check aspect ratio */
- if (surf_man->hw_info.num_banks < surf->mtilea) {
- return -EINVAL;
- }
- /* check bank width */
- switch (surf->bankw) {
- case 0:
- case 1:
- case 2:
- case 4:
- case 8:
- break;
- default:
- return -EINVAL;
- }
- /* check bank height */
- switch (surf->bankh) {
- case 0:
- case 1:
- case 2:
- case 4:
- case 8:
- break;
- default:
- return -EINVAL;
- }
- tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
- if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
- if (mode == RADEON_SURF_MODE_2D) {
+ switch (surf->mtilea) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ return -EINVAL;
+ }
+ /* check aspect ratio */
+ if (surf_man->hw_info.num_banks < surf->mtilea) {
+ return -EINVAL;
+ }
+ /* check bank width */
+ switch (surf->bankw) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ return -EINVAL;
+ }
+ /* check bank height */
+ switch (surf->bankh) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ return -EINVAL;
+ }
+ tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
+ if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
return -EINVAL;
}
- }
-
- /* force 1d on kernel that can't do 2d */
- if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
- mode = RADEON_SURF_MODE_1D;
}
return 0;
commit 76b4a69aab7cbfb4a087194b6d6ee182c1d5dd7e
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Thu Feb 2 14:53:43 2012 -0500
Using sizeof() on a function parameter with an array type does not
work. sizeof() treats such parameters as pointers.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
diff --git a/xf86drmMode.c b/xf86drmMode.c
index 473e734..c809c44 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -271,9 +271,9 @@ int drmModeAddFB2(int fd, uint32_t width, uint32_t height,
f.height = height;
f.pixel_format = pixel_format;
f.flags = flags;
- memcpy(f.handles, bo_handles, sizeof(bo_handles));
- memcpy(f.pitches, pitches, sizeof(pitches));
- memcpy(f.offsets, offsets, sizeof(offsets));
+ memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0]));
+ memcpy(f.pitches, pitches, 4 * sizeof(pitches[0]));
+ memcpy(f.offsets, offsets, 4 * sizeof(offsets[0]));
if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f)))
return ret;
commit a14c3dd0f9c468d5dba86df5ffa786aea77068a9
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Thu Feb 2 14:53:41 2012 -0500
This function was missing.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
diff --git a/xf86drmMode.c b/xf86drmMode.c
index e67ed4a..473e734 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -965,3 +965,12 @@ err_allocs:
return r;
}
+
+void drmModeFreePlaneResources(drmModePlaneResPtr ptr)
+{
+ if (!ptr)
+ return;
+
+ drmFree(ptr->planes);
+ drmFree(ptr);
+}
diff --git a/xf86drmMode.h b/xf86drmMode.h
index c0fc2ef..34f5fb1 100644
--- a/xf86drmMode.h
+++ b/xf86drmMode.h
@@ -305,6 +305,7 @@ extern void drmModeFreeCrtc( drmModeCrtcPtr ptr );
extern void drmModeFreeConnector( drmModeConnectorPtr ptr );
extern void drmModeFreeEncoder( drmModeEncoderPtr ptr );
extern void drmModeFreePlane( drmModePlanePtr ptr );
+extern void drmModeFreePlaneResources(drmModePlaneResPtr ptr);
/**
* Retrives all of the resources associated with a card.
commit df497e9281036ca9397bc5a08a82fdf44dbc12b2
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date: Thu Feb 2 14:53:39 2012 -0500
drmModeFreeResources() always leaked some memory.
drmModeGetPlaneResources() and drmModeGetPlane() leaked in one error
path.
Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
diff --git a/xf86drmMode.c b/xf86drmMode.c
index da7b462..e67ed4a 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -96,6 +96,10 @@ void drmModeFreeResources(drmModeResPtr ptr)
if (!ptr)
return;
+ drmFree(ptr->fbs);
+ drmFree(ptr->crtcs);
+ drmFree(ptr->connectors);
+ drmFree(ptr->encoders);
drmFree(ptr);
}
@@ -898,6 +902,7 @@ retry:
ovr.count_format_types, sizeof(uint32_t));
if (ovr.count_format_types && !r->formats) {
drmFree(r->formats);
+ drmFree(r);
r = 0;
}
@@ -951,6 +956,7 @@ retry:
res.count_planes, sizeof(uint32_t));
if (res.count_planes && !r->planes) {
drmFree(r->planes);
+ drmFree(r);
r = 0;
}
commit c51f7f0e460dcadb9f1a56ecf1615810877c33c8
Author: Jerome Glisse <jglisse@redhat.com>
Date: Fri Dec 9 21:07:15 2011 -0500
radeon: add surface allocator helper v10
The surface allocator is able to build complete miptree when allocating
surface for r600/r700/evergreen/northern islands GPU family. It also
compute bo size and alignment for render buffer, depth buffer and
scanout buffer.
v2 fix r6xx/r7xx 2D tiling width align computation
v3 add tile split support and fix 1d texture alignment
v4 rework to more properly support compressed format, split surface pixel
size and surface element size in separate fields
v5 support texture array (still issue on r6xx)
v6 split surface value computation and mipmap tree building, rework eg
and newer computation
v7 add a check for tile split and 2d tiled
v8 initialize mode value before testing it in all case, reenable
2D macro tile mode on r6xx for cubemap and array. Fix cubemap
to force array size to the number of face.
v9 fix handling of stencil buffer on evergreen
v10 on evergreen depth buffer need to have enough room for a stencil
buffer just after depth one
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 3b762d6..00d66b3 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -802,13 +802,23 @@ struct drm_radeon_gem_create {
uint32_t flags;
};
-#define RADEON_TILING_MACRO 0x1
-#define RADEON_TILING_MICRO 0x2
-#define RADEON_TILING_SWAP_16BIT 0x4
-#define RADEON_TILING_SWAP_32BIT 0x8
-#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface
- * when mapped - i.e. front buffer */
-#define RADEON_TILING_MICRO_SQUARE 0x20
+#define RADEON_TILING_MACRO 0x1
+#define RADEON_TILING_MICRO 0x2
+#define RADEON_TILING_SWAP_16BIT 0x4
+#define RADEON_TILING_SWAP_32BIT 0x8
+/* this object requires a surface when mapped - i.e. front buffer */
+#define RADEON_TILING_SURFACE 0x10
+#define RADEON_TILING_MICRO_SQUARE 0x20
+#define RADEON_TILING_EG_BANKW_SHIFT 8
+#define RADEON_TILING_EG_BANKW_MASK 0xf
+#define RADEON_TILING_EG_BANKH_SHIFT 12
+#define RADEON_TILING_EG_BANKH_MASK 0xf
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
+#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
+#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
+#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
+#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
struct drm_radeon_gem_set_tiling {
uint32_t handle;
diff --git a/radeon/Makefile.am b/radeon/Makefile.am
index dc94b5f..e64aff4 100644
--- a/radeon/Makefile.am
+++ b/radeon/Makefile.am
@@ -40,6 +40,7 @@ libdrm_radeon_la_SOURCES = \
radeon_cs_space.c \
radeon_bo.c \
radeon_cs.c \
+ radeon_surface.c \
bof.c \
bof.h
@@ -47,6 +48,7 @@ libdrm_radeonincludedir = ${includedir}/libdrm
libdrm_radeoninclude_HEADERS = \
radeon_bo.h \
radeon_cs.h \
+ radeon_surface.h \
radeon_bo_gem.h \
radeon_cs_gem.h \
radeon_bo_int.h \
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
new file mode 100644
index 0000000..0ffb741
--- /dev/null
+++ b/radeon/r600_pci_ids.h
@@ -0,0 +1,271 @@
+CHIPSET(0x9400, R600_9400, R600)
+CHIPSET(0x9401, R600_9401, R600)
+CHIPSET(0x9402, R600_9402, R600)
+CHIPSET(0x9403, R600_9403, R600)
+CHIPSET(0x9405, R600_9405, R600)
+CHIPSET(0x940A, R600_940A, R600)
+CHIPSET(0x940B, R600_940B, R600)
+CHIPSET(0x940F, R600_940F, R600)
+
+CHIPSET(0x94C0, RV610_94C0, RV610)
+CHIPSET(0x94C1, RV610_94C1, RV610)
+CHIPSET(0x94C3, RV610_94C3, RV610)
+CHIPSET(0x94C4, RV610_94C4, RV610)
+CHIPSET(0x94C5, RV610_94C5, RV610)
+CHIPSET(0x94C6, RV610_94C6, RV610)
+CHIPSET(0x94C7, RV610_94C7, RV610)
+CHIPSET(0x94C8, RV610_94C8, RV610)
+CHIPSET(0x94C9, RV610_94C9, RV610)
+CHIPSET(0x94CB, RV610_94CB, RV610)
+CHIPSET(0x94CC, RV610_94CC, RV610)
+CHIPSET(0x94CD, RV610_94CD, RV610)
+
+CHIPSET(0x9580, RV630_9580, RV630)
+CHIPSET(0x9581, RV630_9581, RV630)
+CHIPSET(0x9583, RV630_9583, RV630)
+CHIPSET(0x9586, RV630_9586, RV630)
+CHIPSET(0x9587, RV630_9587, RV630)
+CHIPSET(0x9588, RV630_9588, RV630)
+CHIPSET(0x9589, RV630_9589, RV630)
+CHIPSET(0x958A, RV630_958A, RV630)
+CHIPSET(0x958B, RV630_958B, RV630)
+CHIPSET(0x958C, RV630_958C, RV630)
+CHIPSET(0x958D, RV630_958D, RV630)
+CHIPSET(0x958E, RV630_958E, RV630)
+CHIPSET(0x958F, RV630_958F, RV630)
+
+CHIPSET(0x9500, RV670_9500, RV670)
+CHIPSET(0x9501, RV670_9501, RV670)
+CHIPSET(0x9504, RV670_9504, RV670)
+CHIPSET(0x9505, RV670_9505, RV670)
+CHIPSET(0x9506, RV670_9506, RV670)
+CHIPSET(0x9507, RV670_9507, RV670)
+CHIPSET(0x9508, RV670_9508, RV670)
+CHIPSET(0x9509, RV670_9509, RV670)
+CHIPSET(0x950F, RV670_950F, RV670)
+CHIPSET(0x9511, RV670_9511, RV670)
+CHIPSET(0x9515, RV670_9515, RV670)
+CHIPSET(0x9517, RV670_9517, RV670)
+CHIPSET(0x9519, RV670_9519, RV670)
+
+CHIPSET(0x95C0, RV620_95C0, RV620)
+CHIPSET(0x95C2, RV620_95C2, RV620)
+CHIPSET(0x95C4, RV620_95C4, RV620)
+CHIPSET(0x95C5, RV620_95C5, RV620)
+CHIPSET(0x95C6, RV620_95C6, RV620)
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