xserver-xorg-video-intel: Changes to 'upstream-unstable'
Makefile.am | 4
NEWS | 43
configure.ac | 114
man/intel.man | 30
src/Makefile.am | 6
src/brw_structs.h | 124
src/i965_3d.c | 438 ++
src/i965_reg.h | 132
src/i965_render.c | 578 ++-
src/i965_video.c | 578 ++-
src/intel.h | 45
src/intel_batchbuffer.c | 13
src/intel_batchbuffer.h | 2
src/intel_display.c | 16
src/intel_dri.c | 479 ++-
src/intel_driver.c | 26
src/intel_driver.h | 9
src/intel_module.c | 660 +---
src/intel_video.c | 1
src/legacy/i810/i810_dri.c | 1
src/render_program/Makefile.am | 50
src/render_program/exa_wm_affine.g6i | 35
src/render_program/exa_wm_mask_affine.g6a | 8
src/render_program/exa_wm_mask_affine.g7a | 41
src/render_program/exa_wm_mask_affine.g7b | 4
src/render_program/exa_wm_mask_projective.g7a | 63
src/render_program/exa_wm_mask_projective.g7b | 12
src/render_program/exa_wm_mask_sample_a.g7a | 49
src/render_program/exa_wm_mask_sample_a.g7b | 3
src/render_program/exa_wm_mask_sample_argb.g7a | 49
src/render_program/exa_wm_mask_sample_argb.g7b | 3
src/render_program/exa_wm_sample_planar.g4i | 64
src/render_program/exa_wm_src_affine.g6a | 8
src/render_program/exa_wm_src_affine.g7a | 41
src/render_program/exa_wm_src_affine.g7b | 4
src/render_program/exa_wm_src_projective.g7a | 63
src/render_program/exa_wm_src_projective.g7b | 12
src/render_program/exa_wm_src_sample_a.g7a | 48
src/render_program/exa_wm_src_sample_a.g7b | 3
src/render_program/exa_wm_src_sample_argb.g4a | 18
src/render_program/exa_wm_src_sample_argb.g4i | 44
src/render_program/exa_wm_src_sample_argb.g7a | 38
src/render_program/exa_wm_src_sample_argb.g7b | 3
src/render_program/exa_wm_src_sample_planar.g4a | 36
src/render_program/exa_wm_src_sample_planar.g7a | 38
src/render_program/exa_wm_src_sample_planar.g7b | 5
src/render_program/exa_wm_write.g6a | 38
src/render_program/exa_wm_write.g6i | 61
src/render_program/exa_wm_write.g7a | 41
src/render_program/exa_wm_write.g7b | 17
src/render_program/exa_wm_yuv_rgb.g7a | 1
src/render_program/exa_wm_yuv_rgb.g7b | 12
src/sna/Makefile.am | 101
src/sna/README | 30
src/sna/blt.c | 73
src/sna/gen2_render.c | 2314 ++++++++++++++
src/sna/gen2_render.h | 795 +++++
src/sna/gen3_render.c | 3716 ++++++++++++++++++++++++
src/sna/gen3_render.h | 1479 +++++++++
src/sna/gen4_render.c | 2839 ++++++++++++++++++
src/sna/gen4_render.h | 2643 +++++++++++++++++
src/sna/gen5_render.c | 2842 ++++++++++++++++++
src/sna/gen5_render.h | 2730 +++++++++++++++++
src/sna/gen6_render.c | 2891 ++++++++++++++++++
src/sna/gen6_render.h | 1598 ++++++++++
src/sna/gen7_render.c | 3036 +++++++++++++++++++
src/sna/gen7_render.h | 1716 +++++++++++
src/sna/kgem.c | 1978 ++++++++++++
src/sna/kgem.h | 337 ++
src/sna/kgem_debug.c | 408 ++
src/sna/kgem_debug.h | 31
src/sna/kgem_debug_gen2.c | 60
src/sna/kgem_debug_gen3.c | 1620 ++++++++++
src/sna/kgem_debug_gen4.c | 711 ++++
src/sna/kgem_debug_gen5.c | 687 ++++
src/sna/kgem_debug_gen6.c | 1099 +++++++
src/sna/sna.h | 581 +++
src/sna/sna_accel.c | 3435 ++++++++++++++++++++++
src/sna/sna_blt.c | 1361 ++++++++
src/sna/sna_composite.c | 738 ++++
src/sna/sna_damage.c | 971 ++++++
src/sna/sna_damage.h | 109
src/sna/sna_display.c | 2145 +++++++++++++
src/sna/sna_dri.c | 1748 +++++++++++
src/sna/sna_driver.c | 1037 ++++++
src/sna/sna_glyphs.c | 1177 +++++++
src/sna/sna_gradient.c | 352 ++
src/sna/sna_io.c | 446 ++
src/sna/sna_module.h | 3
src/sna/sna_reg.h | 108
src/sna/sna_render.c | 1154 +++++++
src/sna/sna_render.h | 550 +++
src/sna/sna_render_inline.h | 119
src/sna/sna_stream.c | 99
src/sna/sna_tiling.c | 264 +
src/sna/sna_transform.c | 139
src/sna/sna_trapezoids.c | 2387 +++++++++++++++
src/sna/sna_video.c | 585 +++
src/sna/sna_video.h | 129
src/sna/sna_video_hwmc.c | 252 +
src/sna/sna_video_hwmc.h | 74
src/sna/sna_video_overlay.c | 731 ++++
src/sna/sna_video_textured.c | 437 ++
test/.gitignore | 13
test/Makefile.am | 31
test/README | 3
test/basic-copyarea-size.c | 102
test/basic-copyarea.c | 301 +
test/basic-fillrect.c | 263 +
test/basic-putimage.c | 283 +
test/basic-stress.c | 155 +
test/mixed-stress.c | 208 +
test/render-composite-solid.c | 255 +
test/render-copyarea-size.c | 115
test/render-copyarea.c | 324 ++
test/render-fill-copy.c | 279 +
test/render-fill.c | 247 +
test/render-trapezoid-image.c | 615 +++
test/render-trapezoid.c | 434 ++
test/test.h | 118
test/test_display.c | 150
test/test_image.c | 217 +
test/test_log.c | 17
test/test_render.c | 149
uxa/uxa-accel.c | 411 --
uxa/uxa-glyphs.c | 10
126 files changed, 64275 insertions(+), 1501 deletions(-)
New commits:
commit 3a81bb6bafdbd37802dab96b8f05173ec6701d7f
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Aug 9 09:42:40 2011 +0100
NEWS: 2.16.0 release
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/NEWS b/NEWS
index 4192e9d..46d0d24 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,14 @@
+Release 2.16.0 (2011-08-09)
+==============================
+A new quarter, a new release! The key feature of this release, looking past
+the bug fixes, is the enabling of IvyBridge acceleration. We have also fixed
+many bugs and graphical glitches and would encourage everyone to upgrade.
+
+Bugs fixed in this snapshot (compared to 2.15.901)
+--------------------------------------------------
+
+* Build fix for xserver-1.7.7
+
Snapshot 2.15.901 (2011-07-30)
==============================
This is the first release candidate in preparation for the upcoming
diff --git a/configure.ac b/configure.ac
index b6091a8..fbd46a7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.63])
AC_INIT([xf86-video-intel],
- [2.15.901],
+ [2.16.0],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-intel])
AC_CONFIG_SRCDIR([Makefile.am])
commit f4bbbd1dfe59031f864c7d2bbf7bb0252a3aa6a7
Author: Edward Sheldrake <ejsheldrake@gmail.com>
Date: Mon Aug 1 14:46:08 2011 +0100
Fix man page formatting
Two option sections were not starting at the beginning of a new line.
diff --git a/man/intel.man b/man/intel.man
index 282b9f3..f74ee80 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -228,11 +228,13 @@ lag too far behind the CPU and thus noticeable delays in user responsible at
the cost of throughput performance.
.IP
Default: enabled.
+.TP
.BI "Option \*qHotPlug\*q \*q" boolean \*q
This option controls whether the driver automatically notifies
applications when monitors are connected or disconnected.
.IP
Default: enabled.
+.TP
.BI "Option \*qZaphodHeads\*q \*q" string \*q
.IP
Specify the randr output(s) to use with zaphod mode for a particular driver
commit 63518c42234001ec96f638af5732c09079a3d682
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon Aug 1 13:36:28 2011 +0100
dri: Build fix for xserver-1.7.7
Back in the olden days before the introduction of dixRegisterPrivate().
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/intel_dri.c b/src/intel_dri.c
index 90f9b8f..1227dbb 100644
--- a/src/intel_dri.c
+++ b/src/intel_dri.c
@@ -71,7 +71,11 @@ typedef struct {
PixmapPtr pixmap;
} I830DRI2BufferPrivateRec, *I830DRI2BufferPrivatePtr;
+#if HAS_DEVPRIVATEKEYREC
static DevPrivateKeyRec i830_client_key;
+#else
+static int i830_client_key;
+#endif
static uint32_t pixmap_flink(PixmapPtr pixmap)
{
@@ -705,7 +709,11 @@ i830_dri2_register_frame_event_resource_types(void)
static XID
get_client_id(ClientPtr client)
{
+#if HAS_DIXREGISTERPRIVATEKEY
XID *ptr = dixGetPrivateAddr(&client->devPrivates, &i830_client_key);
+#else
+ XID *ptr = dixLookupPrivate(&client->devPrivates, &i830_client_key);
+#endif
if (*ptr == 0)
*ptr = FakeClientID(client->index);
return *ptr;
@@ -1480,8 +1488,13 @@ Bool I830DRI2ScreenInit(ScreenPtr screen)
return FALSE;
}
+#if HAS_DIXREGISTERPRIVATEKEY
if (!dixRegisterPrivateKey(&i830_client_key, PRIVATE_CLIENT, sizeof(XID)))
return FALSE;
+#else
+ if (!dixRequestPrivate(&i830_client_key, sizeof(XID)))
+ return FALSE;
+#endif
#if DRI2INFOREC_VERSION >= 4
commit 7976f5144d42a03ccd027908252a600db2631054
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Jul 30 09:21:36 2011 +0100
NEWS: 2.15.901 snapshot
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/NEWS b/NEWS
index 61866b0..4192e9d 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,33 @@
+Snapshot 2.15.901 (2011-07-30)
+==============================
+This is the first release candidate in preparation for the upcoming
+2.16.0 release. We will appreciate any feedback we can get from
+testing of this snapshot.
+
+The highlight of this snapshot is the full enabling of IvyBridge with
+acceleration for Render and Xv, along with handling of the shared render
+buffer allocations required for Mesa. Also of note is that deep-color
+support is enabled (for all chipsets), which allows you to drive your
+30-bit monitor at its native colour depth.
+
+Bugs fixed in this snapshot (compared to 2.15.0)
+--------------------------------------------------
+
+* Misuse of the Resource database causing crashes after DRI clients close
+ https://bugs.freedesktop.org/show_bug.cgi?id=37700
+
+* Crash on large strings
+ https://bugs.freedesktop.org/show_bug.cgi?id=36860
+
+* Incorrect rendering for some core drawing operations
+ http://bugs.freedesktop.org/show_bug.cgi?id=28768
+ http://bugs.freedesktop.org/show_bug.cgi?id=28798
+ http://bugs.freedesktop.org/show_bug.cgi?id=28908
+ http://bugs.freedesktop.org/show_bug.cgi?id=29401
+
+* Crash in Xv due to insufficient checks on batch space
+ https://bugs.freedesktop.org/show_bug.cgi?id=36319
+
Release 2.15.0 (2011-04-14)
==============================
We are pleased to announce this major release of the xf86-video-intel
diff --git a/configure.ac b/configure.ac
index 8d0653a..b6091a8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.63])
AC_INIT([xf86-video-intel],
- [2.15.0],
+ [2.15.901],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-intel])
AC_CONFIG_SRCDIR([Makefile.am])
commit 2cfb703bbe7ec043d443452f4fa94f06b1ff7266
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Jul 30 09:23:22 2011 +0100
Fix typos for distcheck
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/Makefile.am b/src/sna/Makefile.am
index 241c14b..daf4e98 100644
--- a/src/sna/Makefile.am
+++ b/src/sna/Makefile.am
@@ -39,13 +39,13 @@ libsna_la_SOURCES = \
sna_blt.c \
sna_composite.c \
sna_damage.c \
- snd_damage.h \
+ sna_damage.h \
sna_display.c \
sna_driver.c \
- sna_driver.h \
sna_glyphs.c \
sna_gradient.c \
sna_io.c \
+ sna_module.h \
sna_render.c \
sna_render.h \
sna_render_inline.h \
diff --git a/test/Makefile.am b/test/Makefile.am
index 752e997..475cb17 100644
--- a/test/Makefile.am
+++ b/test/Makefile.am
@@ -21,6 +21,7 @@ LDADD = libtest.la @X11_LIBS@
noinst_LTLIBRARIES = libtest.la
libtest_la_SOURCES = \
+ test.h \
test_display.c \
test_image.c \
test_log.c \
commit 6f919264da69ed8bce6f2573629d89962a670783
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Jul 30 09:00:06 2011 +0100
sna: Mark the stencil as untiled
In reality, Mesa will be treating it as W-tiling, only we have no way of
communicating that requirement to the kernel (as not only does the
kernel not understand W-tiling, but also the GTT is incapable of fencing
a W-tiled region.).
Ported from Chad Versace's 3e55f3e88.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c
index ec65642..9b0ce20 100644
--- a/src/sna/sna_dri.c
+++ b/src/sna/sna_dri.c
@@ -246,12 +246,22 @@ sna_dri_create_buffer(DrawablePtr drawable,
*
* If we neglect to double the pitch, then
* drm_intel_gem_bo_map_gtt() maps the memory incorrectly.
+ *
+ * The alignment for W-tiling is quite different to the
+ * nominal no-tiling case, so we have to account for
+ * the tiled access pattern explicitly.
+ *
+ * The stencil buffer is W tiled. However, we request from
+ * the kernel a non-tiled buffer because the kernel does
+ * not understand W tiling and the GTT is incapable of
+ * W fencing.
*/
bpp = format ? format : drawable->bitsPerPixel;
bo = kgem_create_2d(&sna->kgem,
- drawable->width,
- drawable->height/2, 2*bpp,
- I915_TILING_Y,
+ ALIGN(drawable->width, 64),
+ ALIGN((drawable->height + 1) / 2, 64),
+ 2*bpp,
+ I915_TILING_NONE,
CREATE_EXACT);
break;
commit 326a84e832c43cc200a32e091b4e60b8b6a4a7c8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri Jul 22 11:10:26 2011 +0100
sna: Port IVB acceleration code (Xrender + Xv)
Based on the superlative work by Kenneth Graunke and Xiang, Haihao.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/sna/Makefile.am b/src/sna/Makefile.am
index d76480d..241c14b 100644
--- a/src/sna/Makefile.am
+++ b/src/sna/Makefile.am
@@ -68,6 +68,8 @@ libsna_la_SOURCES = \
gen5_render.h \
gen6_render.c \
gen6_render.h \
+ gen7_render.c \
+ gen7_render.h \
$(NULL)
if DRI
diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c
new file mode 100644
index 0000000..502590e
--- /dev/null
+++ b/src/sna/gen7_render.c
@@ -0,0 +1,3036 @@
+/*
+ * Copyright © 2006,2008,2011 Intel Corporation
+ * Copyright © 2007 Red Hat, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ * Wang Zhenyu <zhenyu.z.wang@sna.com>
+ * Eric Anholt <eric@anholt.net>
+ * Carl Worth <cworth@redhat.com>
+ * Keith Packard <keithp@keithp.com>
+ * Chris Wilson <chris@chris-wilson.co.uk>
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <xf86.h>
+
+#include "sna.h"
+#include "sna_reg.h"
+#include "sna_render.h"
+#include "sna_render_inline.h"
+#include "sna_video.h"
+
+#include "gen7_render.h"
+
+#if DEBUG_RENDER
+#undef DBG
+#define DBG(x) ErrorF x
+#else
+#define NDEBUG 1
+#endif
+
+#define NO_COMPOSITE 0
+#define NO_COPY 0
+#define NO_COPY_BOXES 0
+#define NO_FILL 0
+#define NO_FILL_BOXES 0
+
+#define GEN7_MAX_SIZE 16384
+
+/* XXX Todo
+ *
+ * STR (software tiled rendering) mode. No, really.
+ * 64x32 pixel blocks align with the rendering cache. Worth considering.
+ */
+
+#define is_aligned(x, y) (((x) & ((y) - 1)) == 0)
+
+static const uint32_t ps_kernel_nomask_affine[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_nomask_projective[][4] = {
+#include "exa_wm_src_projective.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_maskca_affine[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_mask_affine.g7b"
+#include "exa_wm_mask_sample_argb.g7b"
+#include "exa_wm_ca.g6b" //#include "exa_wm_ca.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_maskca_projective[][4] = {
+#include "exa_wm_src_projective.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_mask_projective.g7b"
+#include "exa_wm_mask_sample_argb.g7b"
+#include "exa_wm_ca.g6b" //#include "exa_wm_ca.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_maskca_srcalpha_affine[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_a.g7b"
+#include "exa_wm_mask_affine.g7b"
+#include "exa_wm_mask_sample_argb.g7b"
+#include "exa_wm_ca_srcalpha.g6b" //#include "exa_wm_ca_srcalpha.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_maskca_srcalpha_projective[][4] = {
+#include "exa_wm_src_projective.g7b"
+#include "exa_wm_src_sample_a.g7b"
+#include "exa_wm_mask_projective.g7b"
+#include "exa_wm_mask_sample_argb.g7b"
+#include "exa_wm_ca_srcalpha.g6b" //#include "exa_wm_ca_srcalpha.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_masknoca_affine[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_mask_affine.g7b"
+#include "exa_wm_mask_sample_a.g7b"
+#include "exa_wm_noca.g6b"// #include "exa_wm_noca.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_masknoca_projective[][4] = {
+#include "exa_wm_src_projective.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_mask_projective.g7b"
+#include "exa_wm_mask_sample_a.g7b"
+#include "exa_wm_noca.g6b" //#include "exa_wm_noca.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_packed[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_argb.g7b"
+#include "exa_wm_yuv_rgb.g7b"
+#include "exa_wm_write.g7b"
+};
+
+static const uint32_t ps_kernel_planar[][4] = {
+#include "exa_wm_src_affine.g7b"
+#include "exa_wm_src_sample_planar.g7b"
+#include "exa_wm_yuv_rgb.g7b"
+#include "exa_wm_write.g7b"
+};
+
+#define KERNEL(kernel_enum, kernel, masked) \
+ [GEN7_WM_KERNEL_##kernel_enum] = {#kernel_enum, kernel, sizeof(kernel), masked}
+static const struct wm_kernel_info {
+ const char *name;
+ const void *data;
+ unsigned int size;
+ Bool has_mask;
+} wm_kernels[] = {
+ KERNEL(NOMASK, ps_kernel_nomask_affine, FALSE),
+#if 0
+ KERNEL(NOMASK_PROJECTIVE, ps_kernel_nomask_projective, FALSE),
+
+ KERNEL(MASK, ps_kernel_masknoca_affine, TRUE),
+ KERNEL(MASK_PROJECTIVE, ps_kernel_masknoca_projective, TRUE),
+
+ KERNEL(MASKCA, ps_kernel_maskca_affine, TRUE),
+ KERNEL(MASKCA_PROJECTIVE, ps_kernel_maskca_projective, TRUE),
+
+ KERNEL(MASKCA_SRCALPHA, ps_kernel_maskca_srcalpha_affine, TRUE),
+ KERNEL(MASKCA_SRCALPHA_PROJECTIVE, ps_kernel_maskca_srcalpha_projective, TRUE),
+#endif
+
+ KERNEL(VIDEO_PLANAR, ps_kernel_planar, FALSE),
+ KERNEL(VIDEO_PACKED, ps_kernel_packed, FALSE),
+};
+#undef KERNEL
+
+static const struct blendinfo {
+ Bool src_alpha;
+ uint32_t src_blend;
+ uint32_t dst_blend;
+} gen7_blend_op[] = {
+ /* Clear */ {0, GEN7_BLENDFACTOR_ZERO, GEN7_BLENDFACTOR_ZERO},
+ /* Src */ {0, GEN7_BLENDFACTOR_ONE, GEN7_BLENDFACTOR_ZERO},
+ /* Dst */ {0, GEN7_BLENDFACTOR_ZERO, GEN7_BLENDFACTOR_ONE},
+ /* Over */ {1, GEN7_BLENDFACTOR_ONE, GEN7_BLENDFACTOR_INV_SRC_ALPHA},
+ /* OverReverse */ {0, GEN7_BLENDFACTOR_INV_DST_ALPHA, GEN7_BLENDFACTOR_ONE},
+ /* In */ {0, GEN7_BLENDFACTOR_DST_ALPHA, GEN7_BLENDFACTOR_ZERO},
+ /* InReverse */ {1, GEN7_BLENDFACTOR_ZERO, GEN7_BLENDFACTOR_SRC_ALPHA},
+ /* Out */ {0, GEN7_BLENDFACTOR_INV_DST_ALPHA, GEN7_BLENDFACTOR_ZERO},
+ /* OutReverse */ {1, GEN7_BLENDFACTOR_ZERO, GEN7_BLENDFACTOR_INV_SRC_ALPHA},
+ /* Atop */ {1, GEN7_BLENDFACTOR_DST_ALPHA, GEN7_BLENDFACTOR_INV_SRC_ALPHA},
+ /* AtopReverse */ {1, GEN7_BLENDFACTOR_INV_DST_ALPHA, GEN7_BLENDFACTOR_SRC_ALPHA},
+ /* Xor */ {1, GEN7_BLENDFACTOR_INV_DST_ALPHA, GEN7_BLENDFACTOR_INV_SRC_ALPHA},
+ /* Add */ {0, GEN7_BLENDFACTOR_ONE, GEN7_BLENDFACTOR_ONE},
+};
+
+/**
+ * Highest-valued BLENDFACTOR used in gen7_blend_op.
+ *
+ * This leaves out GEN7_BLENDFACTOR_INV_DST_COLOR,
+ * GEN7_BLENDFACTOR_INV_CONST_{COLOR,ALPHA},
+ * GEN7_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA}
+ */
+#define GEN7_BLENDFACTOR_COUNT (GEN7_BLENDFACTOR_INV_DST_ALPHA + 1)
+
+/* FIXME: surface format defined in gen7_defines.h, shared Sampling engine
+ * 1.7.2
+ */
+static const struct formatinfo {
+ CARD32 pict_fmt;
+ uint32_t card_fmt;
+} gen7_tex_formats[] = {
+ {PICT_a8, GEN7_SURFACEFORMAT_A8_UNORM},
+ {PICT_a8r8g8b8, GEN7_SURFACEFORMAT_B8G8R8A8_UNORM},
+ {PICT_x8r8g8b8, GEN7_SURFACEFORMAT_B8G8R8X8_UNORM},
+ {PICT_a8b8g8r8, GEN7_SURFACEFORMAT_R8G8B8A8_UNORM},
+ {PICT_x8b8g8r8, GEN7_SURFACEFORMAT_R8G8B8X8_UNORM},
+ {PICT_r8g8b8, GEN7_SURFACEFORMAT_R8G8B8_UNORM},
+ {PICT_r5g6b5, GEN7_SURFACEFORMAT_B5G6R5_UNORM},
+ {PICT_a1r5g5b5, GEN7_SURFACEFORMAT_B5G5R5A1_UNORM},
+ {PICT_a2r10g10b10, GEN7_SURFACEFORMAT_B10G10R10A2_UNORM},
+ {PICT_x2r10g10b10, GEN7_SURFACEFORMAT_B10G10R10X2_UNORM},
+ {PICT_a2b10g10r10, GEN7_SURFACEFORMAT_R10G10B10A2_UNORM},
+ {PICT_x2r10g10b10, GEN7_SURFACEFORMAT_B10G10R10X2_UNORM},
+ {PICT_a4r4g4b4, GEN7_SURFACEFORMAT_B4G4R4A4_UNORM},
+};
+
+#define GEN7_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen7_blend_state), 64)
+
+#define BLEND_OFFSET(s, d) \
+ (((s) * GEN7_BLENDFACTOR_COUNT + (d)) * GEN7_BLEND_STATE_PADDED_SIZE)
+
+#define SAMPLER_OFFSET(sf, se, mf, me) \
+ (((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) * 2 * sizeof(struct gen7_sampler_state))
+
+#define OUT_BATCH(v) batch_emit(sna, v)
+#define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y)
+#define OUT_VERTEX_F(v) vertex_emit(sna, v)
+
+static uint32_t gen7_get_blend(int op,
+ Bool has_component_alpha,
+ uint32_t dst_format)
+{
+ uint32_t src, dst;
+
+ src = gen7_blend_op[op].src_blend;
+ dst = gen7_blend_op[op].dst_blend;
+
+ /* If there's no dst alpha channel, adjust the blend op so that
+ * we'll treat it always as 1.
+ */
+ if (PICT_FORMAT_A(dst_format) == 0) {
+ if (src == GEN7_BLENDFACTOR_DST_ALPHA)
+ src = GEN7_BLENDFACTOR_ONE;
+ else if (src == GEN7_BLENDFACTOR_INV_DST_ALPHA)
+ src = GEN7_BLENDFACTOR_ZERO;
+ }
+
+ /* If the source alpha is being used, then we should only be in a
+ * case where the source blend factor is 0, and the source blend
+ * value is the mask channels multiplied by the source picture's alpha.
+ */
+ if (has_component_alpha && gen7_blend_op[op].src_alpha) {
+ if (dst == GEN7_BLENDFACTOR_SRC_ALPHA)
+ dst = GEN7_BLENDFACTOR_SRC_COLOR;
+ else if (dst == GEN7_BLENDFACTOR_INV_SRC_ALPHA)
+ dst = GEN7_BLENDFACTOR_INV_SRC_COLOR;
+ }
+
+ DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n",
+ op, dst_format, PICT_FORMAT_A(dst_format),
+ src, dst, (int)BLEND_OFFSET(src, dst)));
+ return BLEND_OFFSET(src, dst);
+}
+
+static uint32_t gen7_get_dest_format(PictFormat format)
+{
+ switch (format) {
+ default:
+ assert(0);
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ return GEN7_SURFACEFORMAT_B8G8R8A8_UNORM;
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ return GEN7_SURFACEFORMAT_R8G8B8A8_UNORM;
+ case PICT_a2r10g10b10:
+ case PICT_x2r10g10b10:
+ return GEN7_SURFACEFORMAT_B10G10R10A2_UNORM;
+ case PICT_r5g6b5:
+ return GEN7_SURFACEFORMAT_B5G6R5_UNORM;
+ case PICT_x1r5g5b5:
+ case PICT_a1r5g5b5:
+ return GEN7_SURFACEFORMAT_B5G5R5A1_UNORM;
+ case PICT_a8:
+ return GEN7_SURFACEFORMAT_A8_UNORM;
+ case PICT_a4r4g4b4:
+ case PICT_x4r4g4b4:
+ return GEN7_SURFACEFORMAT_B4G4R4A4_UNORM;
+ }
+}
+
+static Bool gen7_check_dst_format(PictFormat format)
+{
+ switch (format) {
+ case PICT_a8r8g8b8:
+ case PICT_x8r8g8b8:
+ case PICT_a8b8g8r8:
+ case PICT_x8b8g8r8:
+ case PICT_a2r10g10b10:
+ case PICT_x2r10g10b10:
+ case PICT_r5g6b5:
+ case PICT_x1r5g5b5:
+ case PICT_a1r5g5b5:
+ case PICT_a8:
+ case PICT_a4r4g4b4:
+ case PICT_x4r4g4b4:
+ return TRUE;
+ }
+ return FALSE;
+}
+
+static uint32_t gen7_get_dest_format_for_depth(int depth)
+{
+ switch (depth) {
+ default: assert(0);
+ case 32:
+ case 24: return GEN7_SURFACEFORMAT_B8G8R8A8_UNORM;
+ case 30: return GEN7_SURFACEFORMAT_B10G10R10A2_UNORM;
+ case 16: return GEN7_SURFACEFORMAT_B5G6R5_UNORM;
+ case 8: return GEN7_SURFACEFORMAT_A8_UNORM;
+ }
+}
+
+static uint32_t gen7_get_card_format_for_depth(int depth)
+{
+ switch (depth) {
+ default: assert(0);
+ case 32: return GEN7_SURFACEFORMAT_B8G8R8A8_UNORM;
+ case 30: return GEN7_SURFACEFORMAT_B10G10R10A2_UNORM;
+ case 24: return GEN7_SURFACEFORMAT_B8G8R8X8_UNORM;
+ case 16: return GEN7_SURFACEFORMAT_B5G6R5_UNORM;
+ case 8: return GEN7_SURFACEFORMAT_A8_UNORM;
+ }
+}
+
+static bool gen7_format_is_dst(uint32_t format)
+{
+ switch (format) {
+ case GEN7_SURFACEFORMAT_B8G8R8A8_UNORM:
+ case GEN7_SURFACEFORMAT_R8G8B8A8_UNORM:
+ case GEN7_SURFACEFORMAT_B10G10R10A2_UNORM:
+ case GEN7_SURFACEFORMAT_B5G6R5_UNORM:
+ case GEN7_SURFACEFORMAT_B5G5R5A1_UNORM:
+ case GEN7_SURFACEFORMAT_A8_UNORM:
+ case GEN7_SURFACEFORMAT_B4G4R4A4_UNORM:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static uint32_t gen7_filter(uint32_t filter)
+{
+ switch (filter) {
+ default:
+ assert(0);
+ case PictFilterNearest:
+ return SAMPLER_FILTER_NEAREST;
+ case PictFilterBilinear:
+ return SAMPLER_FILTER_BILINEAR;
+ }
+}
+
+static uint32_t gen7_check_filter(PicturePtr picture)
+{
+ switch (picture->filter) {
+ case PictFilterNearest:
+ case PictFilterBilinear:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+static uint32_t gen7_repeat(uint32_t repeat)
+{
+ switch (repeat) {
+ default:
+ assert(0);
+ case RepeatNone:
+ return SAMPLER_EXTEND_NONE;
+ case RepeatNormal:
+ return SAMPLER_EXTEND_REPEAT;
+ case RepeatPad:
+ return SAMPLER_EXTEND_PAD;
+ case RepeatReflect:
+ return SAMPLER_EXTEND_REFLECT;
+ }
+}
+
+static bool gen7_check_repeat(PicturePtr picture)
+{
+ if (!picture->repeat)
+ return TRUE;
+
+ switch (picture->repeatType) {
+ case RepeatNone:
+ case RepeatNormal:
+ case RepeatPad:
+ case RepeatReflect:
+ return TRUE;
+ default:
+ return FALSE;
+ }
+}
+
+static int
+gen7_choose_composite_kernel(int op, Bool has_mask, Bool is_ca, Bool is_affine)
+{
+ int base;
+
+ if (has_mask) {
+ if (is_ca) {
+ if (gen7_blend_op[op].src_alpha)
+ base = GEN7_WM_KERNEL_MASKCA_SRCALPHA;
+ else
+ base = GEN7_WM_KERNEL_MASKCA;
+ } else
+ base = GEN7_WM_KERNEL_MASK;
+ } else
+ base = GEN7_WM_KERNEL_NOMASK;
+
+ return base + !is_affine;
+}
+
+static void
+gen7_emit_sip(struct sna *sna)
+{
+ /* Set system instruction pointer */
+ OUT_BATCH(GEN7_STATE_SIP | 0);
+ OUT_BATCH(0);
+}
+
+static void
+gen7_emit_urb(struct sna *sna)
+{
+ OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2));
+ OUT_BATCH(8); /* in 1KBs */
+
+ /* num of VS entries must be divisible by 8 if size < 9 */
+ OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2));
+ OUT_BATCH((32 << GEN7_URB_ENTRY_NUMBER_SHIFT) | /* at least 32 */
+ (2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT |
+ (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (2 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+
+ OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2));
+ OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
+ (1 << GEN7_URB_STARTING_ADDRESS_SHIFT));
+}
+
+static void
+gen7_emit_state_base_address(struct sna *sna)
+{
+ OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(0); /* general */
+ OUT_BATCH(kgem_add_reloc(&sna->kgem, /* surface */
+ sna->kgem.nbatch,
+ NULL,
+ I915_GEM_DOMAIN_INSTRUCTION << 16,
+ BASE_ADDRESS_MODIFY));
+ OUT_BATCH(kgem_add_reloc(&sna->kgem, /* instruction */
+ sna->kgem.nbatch,
+ sna->render_state.gen7.general_bo,
+ I915_GEM_DOMAIN_INSTRUCTION << 16,
+ BASE_ADDRESS_MODIFY));
+ OUT_BATCH(0); /* indirect */
+ OUT_BATCH(kgem_add_reloc(&sna->kgem,
+ sna->kgem.nbatch,
+ sna->render_state.gen7.general_bo,
+ I915_GEM_DOMAIN_INSTRUCTION << 16,
+ BASE_ADDRESS_MODIFY));
+
+ /* upper bounds, disable */
+ OUT_BATCH(0);
+ OUT_BATCH(BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0);
+ OUT_BATCH(BASE_ADDRESS_MODIFY);
+}
+
+static void
+gen7_disable_vs(struct sna *sna)
+{
+ OUT_BATCH(GEN7_3DSTATE_VS | (6 - 2));
+ OUT_BATCH(0); /* no VS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+
+#if 0
+ OUT_BATCH(GEN7_3DSTATE_CONSTANT_VS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS | (2 - 2));
+ OUT_BATCH(0);
+#endif
+}
+
+static void
+gen7_disable_hs(struct sna *sna)
+{
+ OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2));
+ OUT_BATCH(0); /* no HS kernel */
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* pass-through */
+
+#if 0
+ OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2));
+ OUT_BATCH(0);
+
+ OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS | (2 - 2));
+ OUT_BATCH(0);
+#endif
+}
+
+static void
+gen7_disable_te(struct sna *sna)
+{
+ OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+}
+
+static void
+gen7_disable_ds(struct sna *sna)
+{
+ OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+
+#if 0
+ OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2));
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