xserver-xorg-video-intel: Changes to 'upstream-unstable'
Makefile.am | 1
NEWS | 220 ++
autogen.sh | 14
configure.ac | 54
m4/.gitignore | 5
man/intel.man | 6
src/Makefile.am | 5
src/brw_structs.h | 100 +
src/common.h | 7
src/i830_reg.h | 2
src/i830_render.c | 26
src/i915_render.c | 18
src/i965_reg.h | 98 +
src/i965_render.c | 1422 +++++++++++++------
src/i965_video.c | 814 +++++++++-
src/intel.h | 133 -
src/intel_batchbuffer.c | 90 -
src/intel_batchbuffer.h | 16
src/intel_display.c | 120 +
src/intel_dri.c | 366 +++-
src/intel_driver.c | 442 ++---
src/intel_driver.h | 106 -
src/intel_hwmc.c | 14
src/intel_memory.c | 44
src/intel_module.c | 153 +-
src/intel_shadow.c | 204 ++
src/intel_uxa.c | 441 ++---
src/intel_video.c | 67
src/intel_video.h | 7
src/legacy/i810/i810.h | 3
src/legacy/i810/i810_dri.c | 4
src/legacy/i810/i810_reg.h | 32
src/render_program/Makefile.am | 45
src/render_program/exa_wm_ca.g6a | 1
src/render_program/exa_wm_ca.g6b | 4
src/render_program/exa_wm_ca_srcalpha.g6a | 1
src/render_program/exa_wm_ca_srcalpha.g6b | 4
src/render_program/exa_wm_mask_affine.g6a | 47
src/render_program/exa_wm_mask_affine.g6b | 4
src/render_program/exa_wm_mask_projective.g6a | 63
src/render_program/exa_wm_mask_projective.g6b | 12
src/render_program/exa_wm_mask_sample_a.g4a | 3
src/render_program/exa_wm_mask_sample_a.g4b | 3
src/render_program/exa_wm_mask_sample_a.g4b.gen5 | 3
src/render_program/exa_wm_mask_sample_a.g6a | 1
src/render_program/exa_wm_mask_sample_a.g6b | 3
src/render_program/exa_wm_mask_sample_argb.g4a | 3
src/render_program/exa_wm_mask_sample_argb.g4b | 3
src/render_program/exa_wm_mask_sample_argb.g4b.gen5 | 3
src/render_program/exa_wm_mask_sample_argb.g6a | 1
src/render_program/exa_wm_mask_sample_argb.g6b | 3
src/render_program/exa_wm_noca.g6a | 1
src/render_program/exa_wm_noca.g6b | 4
src/render_program/exa_wm_src_affine.g6a | 47
src/render_program/exa_wm_src_affine.g6b | 4
src/render_program/exa_wm_src_projective.g6a | 63
src/render_program/exa_wm_src_projective.g6b | 12
src/render_program/exa_wm_src_sample_a.g4a | 3
src/render_program/exa_wm_src_sample_a.g4b | 3
src/render_program/exa_wm_src_sample_a.g4b.gen5 | 3
src/render_program/exa_wm_src_sample_a.g6a | 1
src/render_program/exa_wm_src_sample_a.g6b | 3
src/render_program/exa_wm_src_sample_argb.g4a | 3
src/render_program/exa_wm_src_sample_argb.g4b | 3
src/render_program/exa_wm_src_sample_argb.g4b.gen5 | 3
src/render_program/exa_wm_src_sample_argb.g6a | 1
src/render_program/exa_wm_src_sample_argb.g6b | 3
src/render_program/exa_wm_src_sample_planar.g4a | 7
src/render_program/exa_wm_src_sample_planar.g4b | 7
src/render_program/exa_wm_src_sample_planar.g4b.gen5 | 7
src/render_program/exa_wm_src_sample_planar.g6a | 1
src/render_program/exa_wm_src_sample_planar.g6b | 5
src/render_program/exa_wm_write.g6a | 77 +
src/render_program/exa_wm_write.g6b | 17
src/render_program/exa_wm_yuv_rgb.g6a | 1
src/render_program/exa_wm_yuv_rgb.g6b | 12
src/xvmc/i915_xvmc.c | 3
src/xvmc/intel_batchbuffer.c | 2
src/xvmc/intel_batchbuffer.h | 2
src/xvmc/intel_xvmc.c | 21
src/xvmc/intel_xvmc_dump.c | 2
src/xvmc/xvmc_vld.c | 5
uxa/uxa-accel.c | 10
uxa/uxa-glyphs.c | 27
uxa/uxa-priv.h | 1
uxa/uxa-render.c | 60
uxa/uxa.c | 3
87 files changed, 4139 insertions(+), 1529 deletions(-)
New commits:
commit 34f9a3335f96b16ef9df6213eb0a586c94f8f05b
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Mar 2 17:46:19 2011 +0000
configure: Bump for 2.14.901 snapshot
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/configure.ac b/configure.ac
index 5a1baac..e837738 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.63])
AC_INIT([xf86-video-intel],
- [2.14.0],
+ [2.14.901],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-intel])
AC_CONFIG_SRCDIR([Makefile.am])
commit 057783937d7a42a766d0e45174c4c2dc0ffacd40
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Wed Mar 2 17:45:43 2011 +0000
NEWS: Add entry for 2.14.901 snapshot
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/NEWS b/NEWS
index 4a98c0b..c897bfd 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,34 @@
+Snapshot 2.14.901 (2011-03-02)
+==============================
+This is the first release candidate in preparation for the upcoming
+2.15.0 release. We will appreciate any feedback we can get from
+testing of this snapshot.
+
+Still no further along my grandiose plans to improve Render performance,
+aside from the performance tuning lower in the stack, instead we have had
+a steady stream of bug fixes.
+
+Bugs fixed in this snapshot (compared to 2.14.0)
+------------------------------------------------
+
+* Green pixels within partially off-screen video playback
+ https://bugs.freedesktop.org/show_bug.cgi?id=24767
+
+* Defer creation of the glyph cache to generation startup
+ https://bugs.freedesktop.org/show_bug.cgi?id=33412
+
+* Incorrect maximum addresses for video decoder state
+ https://bugs.freedesktop.org/show_bug.cgi?id=34017
+
+* Failure to handle oversized temporary surfaces
+ https://bugs.freedesktop.org/show_bug.cgi?id=34399
+
+* Relaxed tiling corruption on gen2
+
+* Crash when destroying a foreign DRI drawable
+ https://bugs.freedesktop.org/show_bug.cgi?id=34787
+
+
Release 2.14.0 (2011-01-07)
===========================
We are pleased to announce this major release of the xf86-video-intel
commit e889d3a709b55a0731ab098b17a3364b9bf39387
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sun Feb 27 10:51:50 2011 +0000
dri: Protect against destroying a foreign DRI drawable
I have no clue as to how such an alien drawable reached us, but we have
the evidence of a segfault to say it can happen.
Reported-by: Bernie Innocenti <bernie@codewiz.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34787
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/intel_dri.c b/src/intel_dri.c
index 65c8f39..88d49bd 100644
--- a/src/intel_dri.c
+++ b/src/intel_dri.c
@@ -383,17 +383,17 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment,
static void I830DRI2DestroyBuffer(DrawablePtr drawable, DRI2Buffer2Ptr buffer)
{
- if (buffer) {
+ if (buffer && buffer->driverPrivate) {
I830DRI2BufferPrivatePtr private = buffer->driverPrivate;
if (--private->refcnt == 0) {
ScreenPtr screen = private->pixmap->drawable.pScreen;
-
screen->DestroyPixmap(private->pixmap);
free(private);
free(buffer);
}
- }
+ } else
+ free(buffer);
}
#endif
commit d21d781466785c317131a8a57606925867265dc8
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Tue Feb 22 18:31:44 2011 +0100
Fix relaxed tiling on gen2
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/src/intel_uxa.c b/src/intel_uxa.c
index 9341b91..754bb4e 100644
--- a/src/intel_uxa.c
+++ b/src/intel_uxa.c
@@ -195,12 +195,16 @@ intel_uxa_pixmap_compute_size(PixmapPtr pixmap,
*tiling = I915_TILING_NONE;
if (*tiling != I915_TILING_NONE) {
- int aligned_h;
+ int aligned_h, tile_height;
if (*tiling == I915_TILING_X)
- aligned_h = ALIGN(h, 8);
+ tile_height = 8;
else
- aligned_h = ALIGN(h, 32);
+ tile_height = 32;
+ /* i8xx has a 2-row interleaved tile layout */
+ if (IS_GEN2(intel))
+ tile_height *= 2;
+ aligned_h = ALIGN(h, tile_height);
*stride = intel_get_fence_pitch(intel,
ALIGN(pitch, 512),
commit 9599fde65a0d8b7e7c85199346f7b620bdd8388d
Author: Bryce Harrington <bryce@canonical.com>
Date: Tue Feb 15 22:30:18 2011 -0800
Quell excessively verbose vblank counter failed error messages
Certain error situations can result in the following printed to
Xorg.0.log at a high enough rate to make log file size a problem.
(WW) intel(0): I830DRI2GetMSC:1062 get vblank counter failed: Invalid argument
(WW) intel(0): I830DRI2ScheduleWaitMSC:1118 get vblank counter failed: Invalid argument
Following in the tradition of commit 0ad6d6e1, limit the warnings to be
output 5 times, then quell the remainder.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34322
Ref.: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/710594
Signed-off-by: Bryce Harrington <bryce@canonical.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/intel_dri.c b/src/intel_dri.c
index 7b60e14..65c8f39 100644
--- a/src/intel_dri.c
+++ b/src/intel_dri.c
@@ -1057,10 +1057,14 @@ I830DRI2GetMSC(DrawablePtr draw, CARD64 *ust, CARD64 *msc)
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
if (ret) {
- xf86DrvMsg(scrn->scrnIndex, X_WARNING,
- "%s:%d get vblank counter failed: %s\n",
- __FUNCTION__, __LINE__,
- strerror(errno));
+ static int limit = 5;
+ if (limit) {
+ xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+ "%s:%d get vblank counter failed: %s\n",
+ __FUNCTION__, __LINE__,
+ strerror(errno));
+ limit--;
+ }
return FALSE;
}
@@ -1113,10 +1117,14 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw, CARD64 target_msc,
vbl.request.sequence = 0;
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
if (ret) {
- xf86DrvMsg(scrn->scrnIndex, X_WARNING,
- "%s:%d get vblank counter failed: %s\n",
- __FUNCTION__, __LINE__,
- strerror(errno));
+ static int limit = 5;
+ if (limit) {
+ xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+ "%s:%d get vblank counter failed: %s\n",
+ __FUNCTION__, __LINE__,
+ strerror(errno));
+ limit--;
+ }
goto out_complete;
}
@@ -1143,10 +1151,14 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw, CARD64 target_msc,
vbl.request.signal = (unsigned long)wait_info;
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
if (ret) {
- xf86DrvMsg(scrn->scrnIndex, X_WARNING,
- "%s:%d get vblank counter failed: %s\n",
- __FUNCTION__, __LINE__,
- strerror(errno));
+ static int limit = 5;
+ if (limit) {
+ xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+ "%s:%d get vblank counter failed: %s\n",
+ __FUNCTION__, __LINE__,
+ strerror(errno));
+ limit--;
+ }
goto out_complete;
}
@@ -1178,10 +1190,14 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw, CARD64 target_msc,
vbl.request.signal = (unsigned long)wait_info;
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
if (ret) {
- xf86DrvMsg(scrn->scrnIndex, X_WARNING,
- "%s:%d get vblank counter failed: %s\n",
- __FUNCTION__, __LINE__,
- strerror(errno));
+ static int limit = 5;
+ if (limit) {
+ xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+ "%s:%d get vblank counter failed: %s\n",
+ __FUNCTION__, __LINE__,
+ strerror(errno));
+ limit--;
+ }
goto out_complete;
}
commit 0ca595e9d533019b241666d29b421c7b36f9647a
Author: Adam Jackson <ajax@redhat.com>
Date: Thu Feb 17 15:26:35 2011 -0500
Fix IGD and IGDNG constants to be comprehensible
Since, with GPU-on-package, it's hard to talk about a model number for
a specific chipset like 855GM, just use the platform names.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/i965_render.c b/src/i965_render.c
index b1ac6ba..e42a8c4 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -401,7 +401,7 @@ static const uint32_t ps_kernel_masknoca_projective_static[][4] = {
#include "exa_wm_write.g4b"
};
-/* new programs for IGDNG */
+/* new programs for Ironlake */
static const uint32_t sf_kernel_static_gen5[][4] = {
#include "exa_sf.g4b.gen5"
};
@@ -993,7 +993,7 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn,
}
/* binding table entry count is only used for prefetching, and it has to
- * be set 0 for IGDNG
+ * be set 0 for Ironlake
*/
if (IS_GEN5(intel))
wm_state->thread1.binding_table_entry_count = 0;
@@ -1386,7 +1386,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
if (IS_GEN5(intel)) {
/*
* The reason to add this extra vertex element in the header is that
- * IGDNG has different vertex header definition and origin method to
+ * Ironlake has different vertex header definition and origin method to
* set destination element offset doesn't exist anymore, which means
* hardware requires a predefined vertex element layout.
*
diff --git a/src/i965_video.c b/src/i965_video.c
index e16a575..38c8100 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -113,7 +113,7 @@ static const uint32_t ps_kernel_planar_static[][4] = {
#include "exa_wm_write.g4b"
};
-/* new program for IGDNG */
+/* new program for Ironlake */
static const uint32_t sf_kernel_static_gen5[][4] = {
#include "exa_sf.g4b.gen5"
};
@@ -675,7 +675,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn,
wm_state->thread1.binding_table_entry_count = 7;
/* binding table entry count is only used for prefetching, and it has to
- * be set 0 for IGDNG
+ * be set 0 for Ironlake
*/
if (IS_GEN5(intel))
wm_state->thread1.binding_table_entry_count = 0;
diff --git a/src/intel_driver.h b/src/intel_driver.h
index be8ec5f..d7f5dfa 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -76,11 +76,11 @@
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
-#ifndef PCI_CHIP_IGD_GM
-#define PCI_CHIP_IGD_GM 0xA011
-#define PCI_CHIP_IGD_GM_BRIDGE 0xA010
-#define PCI_CHIP_IGD_G 0xA001
-#define PCI_CHIP_IGD_G_BRIDGE 0xA000
+#ifndef PCI_CHIP_PINEVIEW_M
+#define PCI_CHIP_PINEVIEW_M 0xA011
+#define PCI_CHIP_PINEVIEW_M_BRIDGE 0xA010
+#define PCI_CHIP_PINEVIEW_G 0xA001
+#define PCI_CHIP_PINEVIEW_G_BRIDGE 0xA000
#endif
#ifndef PCI_CHIP_G35_G
@@ -133,9 +133,9 @@
#define PCI_CHIP_GM45_BRIDGE 0x2A40
#endif
-#ifndef PCI_CHIP_IGD_E_G
-#define PCI_CHIP_IGD_E_G 0x2E02
-#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00
+#ifndef PCI_CHIP_G45_E_G
+#define PCI_CHIP_G45_E_G 0x2E02
+#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00
#endif
#ifndef PCI_CHIP_G45_G
@@ -163,14 +163,14 @@
#define PCI_CHIP_B43_G1_BRIDGE 0x2E90
#endif
-#ifndef PCI_CHIP_IGDNG_D_G
-#define PCI_CHIP_IGDNG_D_G 0x0042
-#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040
+#ifndef PCI_CHIP_IRONLAKE_D_G
+#define PCI_CHIP_IRONLAKE_D_G 0x0042
+#define PCI_CHIP_IRONLAKE_D_G_BRIDGE 0x0040
#endif
-#ifndef PCI_CHIP_IGDNG_M_G
-#define PCI_CHIP_IGDNG_M_G 0x0046
-#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044
+#ifndef PCI_CHIP_IRONLAKE_M_G
+#define PCI_CHIP_IRONLAKE_M_G 0x0046
+#define PCI_CHIP_IRONLAKE_M_G_BRIDGE 0x0044
#endif
#ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE
diff --git a/src/intel_module.c b/src/intel_module.c
index 528ecf4..f6cc6d4 100644
--- a/src/intel_module.c
+++ b/src/intel_module.c
@@ -87,8 +87,8 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I945_GME, "945GME"},
- {PCI_CHIP_IGD_GM, "Pineview GM"},
- {PCI_CHIP_IGD_G, "Pineview G"},
+ {PCI_CHIP_PINEVIEW_M, "Pineview GM"},
+ {PCI_CHIP_PINEVIEW_G, "Pineview G"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_G35_G, "G35"},
{PCI_CHIP_I965_Q, "965Q"},
@@ -99,14 +99,14 @@ static const SymTabRec _intel_chipsets[] = {
{PCI_CHIP_Q35_G, "Q35"},
{PCI_CHIP_Q33_G, "Q33"},
{PCI_CHIP_GM45_GM, "GM45"},
- {PCI_CHIP_IGD_E_G, "4 Series"},
+ {PCI_CHIP_G45_E_G, "4 Series"},
{PCI_CHIP_G45_G, "G45/G43"},
{PCI_CHIP_Q45_G, "Q45/Q43"},
{PCI_CHIP_G41_G, "G41"},
{PCI_CHIP_B43_G, "B43"},
{PCI_CHIP_B43_G1, "B43"},
- {PCI_CHIP_IGDNG_D_G, "Clarkdale"},
- {PCI_CHIP_IGDNG_M_G, "Arrandale"},
+ {PCI_CHIP_IRONLAKE_D_G, "Clarkdale"},
+ {PCI_CHIP_IRONLAKE_M_G, "Arrandale"},
{PCI_CHIP_SANDYBRIDGE_GT1, "Sandybridge" },
{PCI_CHIP_SANDYBRIDGE_GT2, "Sandybridge" },
{PCI_CHIP_SANDYBRIDGE_GT2_PLUS, "Sandybridge" },
@@ -137,8 +137,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ),
@@ -149,13 +149,13 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ),
- INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, 0 ),
+ INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, 0 ),
INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, 0 ),
@@ -182,8 +182,8 @@ static PciChipsets intel_pci_chipsets[] = {
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, NULL},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, NULL},
{PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, NULL},
- {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, NULL},
- {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, NULL},
+ {PCI_CHIP_PINEVIEW_M, PCI_CHIP_PINEVIEW_M, NULL},
+ {PCI_CHIP_PINEVIEW_G, PCI_CHIP_PINEVIEW_G, NULL},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, NULL},
{PCI_CHIP_G35_G, PCI_CHIP_G35_G, NULL},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, NULL},
@@ -194,13 +194,13 @@ static PciChipsets intel_pci_chipsets[] = {
{PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, NULL},
{PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, NULL},
{PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, NULL},
- {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, NULL},
+ {PCI_CHIP_G45_E_G, PCI_CHIP_G45_E_G, NULL},
{PCI_CHIP_G45_G, PCI_CHIP_G45_G, NULL},
{PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, NULL},
{PCI_CHIP_G41_G, PCI_CHIP_G41_G, NULL},
{PCI_CHIP_B43_G, PCI_CHIP_B43_G, NULL},
- {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, NULL},
- {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, NULL},
+ {PCI_CHIP_IRONLAKE_D_G, PCI_CHIP_IRONLAKE_D_G, NULL},
+ {PCI_CHIP_IRONLAKE_M_G, PCI_CHIP_IRONLAKE_M_G, NULL},
{PCI_CHIP_SANDYBRIDGE_GT1, PCI_CHIP_SANDYBRIDGE_GT1, NULL},
{PCI_CHIP_SANDYBRIDGE_GT2, PCI_CHIP_SANDYBRIDGE_GT2, NULL},
{PCI_CHIP_SANDYBRIDGE_GT2_PLUS, PCI_CHIP_SANDYBRIDGE_GT2_PLUS, NULL},
@@ -301,11 +301,11 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
chipset->name = "945GME";
chipset->info = &intel_i915_info;
break;
- case PCI_CHIP_IGD_GM:
+ case PCI_CHIP_PINEVIEW_M:
chipset->name = "Pineview GM";
chipset->info = &intel_g33_info;
break;
- case PCI_CHIP_IGD_G:
+ case PCI_CHIP_PINEVIEW_G:
chipset->name = "Pineview G";
chipset->info = &intel_g33_info;
break;
@@ -349,7 +349,7 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
chipset->name = "GM45";
chipset->info = &intel_g4x_info;
break;
- case PCI_CHIP_IGD_E_G:
+ case PCI_CHIP_G45_E_G:
chipset->name = "4 Series";
chipset->info = &intel_g4x_info;
break;
@@ -369,11 +369,11 @@ void intel_detect_chipset(ScrnInfoPtr scrn,
chipset->name = "B43";
chipset->info = &intel_g4x_info;
break;
- case PCI_CHIP_IGDNG_D_G:
+ case PCI_CHIP_IRONLAKE_D_G:
chipset->name = "Clarkdale";
chipset->info = &intel_ironlake_info;
break;
- case PCI_CHIP_IGDNG_M_G:
+ case PCI_CHIP_IRONLAKE_M_G:
chipset->name = "Arrandale";
chipset->info = &intel_ironlake_info;
break;
diff --git a/src/legacy/i810/i810_reg.h b/src/legacy/i810/i810_reg.h
index 2b67934..54faeb3 100644
--- a/src/legacy/i810/i810_reg.h
+++ b/src/legacy/i810/i810_reg.h
@@ -982,18 +982,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
# define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15
-/* IGDNG */
+/* Ironlake */
# define DPLL_FPA0_P1_POST_DIV_SHIFT 16
# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
# define PLL_REF_INPUT_DREFCLK (0 << 13)
# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
-# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* IGDNG: 120M SSC */
+# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* Ironlake: 120M SSC */
# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
# define PLL_REF_INPUT_MASK (3 << 13)
-# define PLL_REF_INPUT_DMICLK (5 << 13) /* IGDNG: DMI refclk */
+# define PLL_REF_INPUT_DMICLK (5 << 13) /* Ironlake: DMI refclk */
# define PLL_LOAD_PULSE_PHASE_SHIFT 9
/*
* Parallel to Serial Load Pulse phase selection.
@@ -1003,7 +1003,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
-/* IGDNG */
+/* Ironlake */
# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT)
@@ -2157,7 +2157,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PIPEACONF_PIPE_LOCKED (1<<25)
#define PIPEACONF_PALETTE 0
#define PIPEACONF_GAMMA (1<<24)
-/* IGDNG: gamma */
+/* Ironlake: gamma */
#define PIPECONF_PALETTE_8BIT (0<<24)
#define PIPECONF_PALETTE_10BIT (1<<24)
#define PIPECONF_PALETTE_12BIT (2<<24)
@@ -2165,7 +2165,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define PIPECONF_PROGRESSIVE (0 << 21)
#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
-/* IGDNG */
+/* Ironlake */
#define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */
#define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16)
#define PIPECONF_NO_ROTATION (0<<14)
@@ -2319,9 +2319,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DISPPLANE_8BPP (0x2<<26)
#define DISPPLANE_15_16BPP (0x4<<26)
#define DISPPLANE_16BPP (0x5<<26)
-#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) /* IGDNG: BGRX */
-#define DISPPLANE_32BPP (0x7<<26) /* IGDNG: not support */
-/* IGDNG */
+#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) /* Ironlake: BGRX */
+#define DISPPLANE_32BPP (0x7<<26) /* Ironlake: not support */
+/* Ironlake */
#define DISPPLANE_32BPP_10 (0x8<<26) /* 2:10:10:10 */
#define DISPPLANE_32BPP_BGRX (0xa<<26)
#define DISPPLANE_64BPP (0xc<<26)
@@ -2329,11 +2329,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DISPPLANE_STEREO_ENABLE (1<<25)
#define DISPPLANE_STEREO_DISABLE 0
#define DISPPLANE_SEL_PIPE_MASK (1<<24)
-#define DISPPLANE_SEL_PIPE_A 0 /* IGDNG: don't use */
+#define DISPPLANE_SEL_PIPE_A 0 /* Ironlake: don't use */
#define DISPPLANE_SEL_PIPE_B (1<<24)
#define DISPPLANE_NORMAL_RANGE (0<<25)
#define DISPPLANE_EXT_RANGE (1<<25)
-/* IGDNG */
+/* Ironlake */
#define DISPPLANE_CSC_BYPASS (0<<24)
#define DISPPLANE_CSC_PASSTHROUGH (1<<24)
#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
@@ -2347,17 +2347,17 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DISPPLANE_ALPHA_TRANS_DISABLE 0
#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
-/* IGDNG */
+/* Ironlake */
#define DISPPLANE_X_TILE (1<<10)
#define DISPPLANE_LINEAR (0<<10)
#define DSPABASE 0x70184
-/* IGDNG */
+/* Ironlake */
#define DSPALINOFF 0x70184
#define DSPASTRIDE 0x70188
#define DSPBBASE 0x71184
-/* IGDNG */
+/* Ironlake */
#define DSPBLINOFF 0x71184
#define DSPBADDR DSPBBASE
#define DSPBSTRIDE 0x71188
@@ -2721,7 +2721,7 @@ typedef enum {
#define MCHBAR_RENDER_STANDBY 0x111B8
#define RENDER_STANDBY_ENABLE (1 << 30)
-/* IGDNG */
+/* Ironlake */
/* warmup time in us */
#define WARMUP_PCH_REF_CLK_SSC_MOD 1
@@ -3054,7 +3054,7 @@ typedef enum {
#define FDI_DP_PORT_WIDTH_X3 (2<<19)
#define FDI_DP_PORT_WIDTH_X4 (3<<19)
#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
-/* IGDNG: hardwired to 1 */
+/* Ironlake: hardwired to 1 */
#define FDI_TX_PLL_ENABLE (1<<14)
/* both Tx and Rx */
#define FDI_SCRAMBLING_ENABLE (0<<7)
diff --git a/src/xvmc/xvmc_vld.c b/src/xvmc/xvmc_vld.c
index d72e105..570e9b6 100644
--- a/src/xvmc/xvmc_vld.c
+++ b/src/xvmc/xvmc_vld.c
@@ -120,7 +120,7 @@ static uint32_t field_f_b_kernel[][4] = {
#include "shader/vld/field_f_b.g4b"
};
-/* on IGDNG */
+/* on Ironlake */
static uint32_t lib_kernel_gen5[][4] = {
#include "shader/vld/lib.g4b.gen5"
};
@@ -186,7 +186,7 @@ static uint32_t field_f_b_kernel_idct[][4] = {
#include "shader/mc/field_f_b_igd.g4b"
};
-/* on IGDNG */
+/* on Ironlake */
static uint32_t lib_kernel_idct_gen5[][4] = {
#include "shader/mc/lib_igd.g4b.gen5"
};
commit 4c66b28870b050493ad96f7b0fe2d70d7ee539c7
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Feb 17 16:48:24 2011 +0000
uxa: Fallback if the temporary is too large
If the render operation requires a temporary source Picture and the
operation is large, larger than the maximum permitted bo, then we will
fail to allocate the bo. In this case, we need to fallback and perform
the operation on the CPU rather than dereference a NULL bo.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34399
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/uxa/uxa-render.c b/uxa/uxa-render.c
index 0f06e82..b26be80 100644
--- a/uxa/uxa-render.c
+++ b/uxa/uxa-render.c
@@ -460,12 +460,12 @@ uxa_try_driver_solid_fill(PicturePtr pSrc,
}
static PicturePtr
-uxa_picture_for_pixman_format(ScreenPtr pScreen,
+uxa_picture_for_pixman_format(ScreenPtr screen,
pixman_format_code_t format,
int width, int height)
{
- PicturePtr pPicture;
- PixmapPtr pPixmap;
+ PicturePtr picture;
+ PixmapPtr pixmap;
int error;
if (format == PIXMAN_a1)
@@ -475,24 +475,29 @@ uxa_picture_for_pixman_format(ScreenPtr pScreen,
if (PIXMAN_FORMAT_A(format) == 0)
format = PIXMAN_a8r8g8b8;
- pPixmap = (*pScreen->CreatePixmap)(pScreen, width, height,
- PIXMAN_FORMAT_DEPTH(format),
- UXA_CREATE_PIXMAP_FOR_MAP);
- if (!pPixmap)
+ pixmap = screen->CreatePixmap(screen, width, height,
+ PIXMAN_FORMAT_DEPTH(format),
+ UXA_CREATE_PIXMAP_FOR_MAP);
+ if (!pixmap)
return 0;
- pPicture = CreatePicture(0, &pPixmap->drawable,
- PictureMatchFormat(pScreen,
- PIXMAN_FORMAT_DEPTH(format),
- format),
- 0, 0, serverClient, &error);
- (*pScreen->DestroyPixmap) (pPixmap);
- if (!pPicture)
+ if (!uxa_pixmap_is_offscreen(pixmap)) {
+ screen->DestroyPixmap(pixmap);
+ return 0;
+ }
+
+ picture = CreatePicture(0, &pixmap->drawable,
+ PictureMatchFormat(screen,
+ PIXMAN_FORMAT_DEPTH(format),
+ format),
+ 0, 0, serverClient, &error);
+ screen->DestroyPixmap(pixmap);
+ if (!picture)
return 0;
- ValidatePicture(pPicture);
+ ValidatePicture(picture);
- return pPicture;
+ return picture;
}
static PicturePtr
commit 23f9b14df7c102c1036134835dd5d1a508059858
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Sat Feb 12 10:42:34 2011 +0000
i965: Remove broken maximum base addresses from video
WRONG.
The hardware was never limited to 0x1000000 and the kernel can quite
rightly place objects above that limit. Specifying such had no relation
to reality, so why did we do it? TWICE!
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34017
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/src/i965_video.c b/src/i965_video.c
index a7374a2..e16a575 100644
--- a/src/i965_video.c
+++ b/src/i965_video.c
@@ -821,20 +821,20 @@ i965_emit_video_setup(ScrnInfoPtr scrn, drm_intel_bo * surface_state_binding_tab
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */
/* general state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
/* media object state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
/* Instruction max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
} else {
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
/* general state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
/* media object state max addr, disabled */
- OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
}
/* Set system instruction pointer */
commit 9184af921bc2f332fcb6c9b47001414378eab8e2
Author: Javier Jardón <jjardon@gnome.org>
Date: Wed Feb 9 00:36:37 2011 +0000
Update autotools configuration
Use new libtool syntax and silent-rules to silent
the build output a bit (linux-like)
diff --git a/Makefile.am b/Makefile.am
index f4239de..83948ab 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -18,6 +18,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ACLOCAL_AMFLAGS = -I m4 ${ACLOCAL_FLAGS}
SUBDIRS = uxa src man
MAINTAINERCLEANFILES = ChangeLog INSTALL
diff --git a/autogen.sh b/autogen.sh
index 904cd67..30d679f 100755
--- a/autogen.sh
+++ b/autogen.sh
@@ -1,12 +1,6 @@
#! /bin/sh
-srcdir=`dirname $0`
-test -z "$srcdir" && srcdir=.
-
-ORIGDIR=`pwd`
-cd $srcdir
-
-autoreconf -v --install || exit 1
-cd $ORIGDIR || exit $?
-
-$srcdir/configure --enable-maintainer-mode "$@"
+test -n "$srcdir" || srcdir=`dirname "$0"`
+test -n "$srcdir" || srcdir=.
+autoreconf --force --install --verbose "$srcdir"
+test -n "$NOCONFIGURE" || "$srcdir/configure" "$@"
diff --git a/configure.ac b/configure.ac
index 13a801a..5a1baac 100644
--- a/configure.ac
+++ b/configure.ac
@@ -21,18 +21,24 @@
# Process this file with autoconf to produce a configure script
# Initialize Autoconf
-AC_PREREQ([2.60])
+AC_PREREQ([2.63])
AC_INIT([xf86-video-intel],
[2.14.0],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-intel])
AC_CONFIG_SRCDIR([Makefile.am])
AC_CONFIG_HEADERS([config.h])
-AC_CONFIG_AUX_DIR(.)
+AC_CONFIG_AUX_DIR([build-aux])
+AC_CONFIG_MACRO_DIR([m4])
# Initialize Automake
-AM_INIT_AUTOMAKE([foreign dist-bzip2])
-AM_MAINTAINER_MODE
+AM_INIT_AUTOMAKE([1.10 foreign dist-bzip2])
+AM_MAINTAINER_MODE([enable])
+
+# Support silent build rules, requires at least automake-1.11. Disable
+# by either passing --disable-silent-rules to configure or passing V=1
+# to make
+m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
# Require X.Org macros 1.8 or later for MAN_SUBSTS set by XORG_MANPAGE_SECTIONS
m4_ifndef([XORG_MACROS_VERSION],
@@ -50,8 +56,8 @@ m4_ifndef([XORG_DRIVER_CHECK_EXT],
depending on your distribution, try package 'xserver-xorg-dev' or 'xorg-x11-server-devel'])])
# Initialize libtool
-AC_DISABLE_STATIC
-AC_PROG_LIBTOOL
+LT_PREREQ([2.2])
+LT_INIT([disable-static])
PKG_CHECK_MODULES(GEN4ASM, [intel-gen4asm >= 1.1], [gen4asm=yes], [gen4asm=no])
AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes)
diff --git a/m4/.gitignore b/m4/.gitignore
new file mode 100644
index 0000000..464ba5c
--- /dev/null
+++ b/m4/.gitignore
@@ -0,0 +1,5 @@
+libtool.m4
+lt~obsolete.m4
+ltoptions.m4
+ltsugar.m4
+ltversion.m4
commit 6e721e098b9181e8e77e314f966729d28e705582
Author: Bryce Harrington <bryce@canonical.com>
Date: Fri Feb 4 00:15:13 2011 -0800
Check return value of uxa_acquire_solid() since it can return NULL
uxa_acquire_solid returns NULL under OOM. Thus the value of solid
must be checked before dereferencing it in the uxa_get_offscreen()
call.
Signed-off-by: Bryce Harrington <bryce@canonical.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
diff --git a/uxa/uxa-accel.c b/uxa/uxa-accel.c
index a5066c8..0650ac2 100644
--- a/uxa/uxa-accel.c
+++ b/uxa/uxa-accel.c
@@ -120,6 +120,10 @@ uxa_fill_spans(DrawablePtr pDrawable, GCPtr pGC, int n,
solid = uxa_acquire_solid(screen, src->pSourcePict);
FreePicture(src, 0);
+ if (!solid) {
+ FreePicture(dst, 0);
+ goto solid;
+ }
src = solid;
src_pixmap = uxa_get_offscreen_pixmap(src->pDrawable,
@@ -1110,6 +1114,10 @@ try_solid:
solid = uxa_acquire_solid(screen, src->pSourcePict);
FreePicture(src, 0);
+ if (!solid) {
+ FreePicture(dst, 0);
+ goto err;
+ }
src = solid;
src_pixmap = uxa_get_offscreen_pixmap(src->pDrawable,
diff --git a/uxa/uxa-render.c b/uxa/uxa-render.c
index 02bfa03..0f06e82 100644
--- a/uxa/uxa-render.c
+++ b/uxa/uxa-render.c
@@ -1061,6 +1061,8 @@ try_solid:
int src_off_x, src_off_y;
solid = uxa_acquire_solid(screen, src->pSourcePict);
+ if (!solid)
+ goto err_src;
FreePicture(src, 0);
src = solid;
commit da990536eca09c6de74627541cd56ecfad925eda
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Feb 3 09:41:48 2011 +0000
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