xserver-xorg-video-ati: Changes to 'upstream-experimental'
.gitignore | 84
Makefile.am | 12
README | 13
configure.ac | 93
man/Makefile.am | 41
man/radeon.man | 77
src/.gitignore | 3
src/AtomBios/CD_Operations.c | 7
src/AtomBios/includes/Decoder.h | 1
src/AtomBios/includes/ObjectID.h | 127
src/AtomBios/includes/atombios.h | 1289 +++++++-
src/Makefile.am | 33
src/ati_pciids_gen.h | 35
src/atombios_crtc.c | 1378 +++++++--
src/atombios_output.c | 1417 ++++++++-
src/drmmode_display.c | 1356 +++++++++
src/drmmode_display.h | 86
src/legacy_crtc.c | 94
src/legacy_output.c | 50
src/pcidb/ati_pciids.csv | 35
src/pcidb/parse_pci_ids.pl | 2
src/r600_exa.c | 1333 +++++---
src/r600_reg_r6xx.h | 6
src/r600_shader.c | 1112 ++++---
src/r600_state.h | 61
src/r600_textured_videofuncs.c | 342 +-
src/r6xx_accel.c | 585 ++-
src/radeon.h | 337 +-
src/radeon_accel.c | 168 -
src/radeon_accelfuncs.c | 5
src/radeon_atombios.c | 391 ++
src/radeon_atombios.h | 18
src/radeon_bios.c | 119
src/radeon_chipinfo_gen.h | 37
src/radeon_chipset_gen.h | 35
src/radeon_commonfuncs.c | 518 ++-
src/radeon_crtc.c | 306 +-
src/radeon_cursor.c | 74
src/radeon_dga.c | 466 ---
src/radeon_dri.c | 77
src/radeon_dri2.c | 375 ++
src/radeon_dri2.h | 42
src/radeon_driver.c | 712 +---
src/radeon_drm.h | 153 +
src/radeon_dummy_bufmgr.h | 62
src/radeon_exa.c | 228 +
src/radeon_exa_funcs.c | 541 ++-
src/radeon_exa_render.c | 845 +++--
src/radeon_kms.c | 1010 ++++++
src/radeon_legacy_memory.c | 22
src/radeon_macros.h | 49
src/radeon_modes.c | 16
src/radeon_output.c | 283 +
src/radeon_pci_chipset_gen.h | 35
src/radeon_pci_device_match_gen.h | 35
src/radeon_pm.c | 886 +++++
src/radeon_probe.c | 79
src/radeon_probe.h | 41
src/radeon_reg.h | 278 +
src/radeon_textured_video.c | 624 ++--
src/radeon_textured_videofuncs.c | 5705 ++++++++++++++++++++++++--------------
src/radeon_vbo.c | 206 +
src/radeon_vbo.h | 62
src/radeon_video.c | 119
src/radeon_video.h | 25
src/simple_list.h | 202 +
66 files changed, 18743 insertions(+), 6115 deletions(-)
New commits:
commit a887818f491f6c7315c56c4e0d0b702c4c6aa4ac
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Feb 1 11:01:47 2010 -0500
evergreen: add pci ids
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 3f9691e..3dd36da 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -453,3 +453,38 @@
#define PCI_CHIP_RS880_9712 0x9712
#define PCI_CHIP_RS880_9713 0x9713
#define PCI_CHIP_RS880_9714 0x9714
+#define PCI_CHIP_CYPRESS_6880 0x6880
+#define PCI_CHIP_CYPRESS_6888 0x6888
+#define PCI_CHIP_CYPRESS_6889 0x6889
+#define PCI_CHIP_CYPRESS_688A 0x688A
+#define PCI_CHIP_CYPRESS_6898 0x6898
+#define PCI_CHIP_CYPRESS_6899 0x6899
+#define PCI_CHIP_CYPRESS_689E 0x689E
+#define PCI_CHIP_HEMLOCK_689C 0x689C
+#define PCI_CHIP_HEMLOCK_689D 0x689D
+#define PCI_CHIP_JUNIPER_68A0 0x68A0
+#define PCI_CHIP_JUNIPER_68A1 0x68A1
+#define PCI_CHIP_JUNIPER_68A8 0x68A8
+#define PCI_CHIP_JUNIPER_68A9 0x68A9
+#define PCI_CHIP_JUNIPER_68B0 0x68B0
+#define PCI_CHIP_JUNIPER_68B8 0x68B8
+#define PCI_CHIP_JUNIPER_68B9 0x68B9
+#define PCI_CHIP_JUNIPER_68BE 0x68BE
+#define PCI_CHIP_REDWOOD_68C0 0x68C0
+#define PCI_CHIP_REDWOOD_68C1 0x68C1
+#define PCI_CHIP_REDWOOD_68C8 0x68C8
+#define PCI_CHIP_REDWOOD_68C9 0x68C9
+#define PCI_CHIP_REDWOOD_68D8 0x68D8
+#define PCI_CHIP_REDWOOD_68D9 0x68D9
+#define PCI_CHIP_REDWOOD_68DA 0x68DA
+#define PCI_CHIP_REDWOOD_68DE 0x68DE
+#define PCI_CHIP_CEDAR_68E0 0x68E0
+#define PCI_CHIP_CEDAR_68E1 0x68E1
+#define PCI_CHIP_CEDAR_68E4 0x68E4
+#define PCI_CHIP_CEDAR_68E5 0x68E5
+#define PCI_CHIP_CEDAR_68E8 0x68E8
+#define PCI_CHIP_CEDAR_68E9 0x68E9
+#define PCI_CHIP_CEDAR_68F1 0x68F1
+#define PCI_CHIP_CEDAR_68F8 0x68F8
+#define PCI_CHIP_CEDAR_68F9 0x68F9
+#define PCI_CHIP_CEDAR_68FE 0x68FE
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 695d9a6..9c72c40 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -454,3 +454,38 @@
"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD 4200"
"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100"
"0x9714","RS880_9714","RS880",,1,,,1,"ATI RS880"
+"0x6880","CYPRESS_6880","CYPRESS",1,,,,,"CYPRESS"
+"0x6888","CYPRESS_6888","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x6889","CYPRESS_6889","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x688A","CYPRESS_688A","CYPRESS",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x6898","CYPRESS_6898","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
+"0x6899","CYPRESS_6899","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
+"0x689E","CYPRESS_689E","CYPRESS",,,,,,"ATI Radeon HD 5800 Series"
+"0x689C","HEMLOCK_689C","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series"
+"0x689D","HEMLOCK_689D","HEMLOCK",,,,,,"ATI Radeon HD 5900 Series"
+"0x68A0","JUNIPER_68A0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
+"0x68A1","JUNIPER_68A1","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
+"0x68A8","JUNIPER_68A8","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68A9","JUNIPER_68A9","JUNIPER",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68B0","JUNIPER_68B0","JUNIPER",1,,,,,"ATI Mobility Radeon HD 5800 Series"
+"0x68B8","JUNIPER_68B8","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
+"0x68B9","JUNIPER_68B9","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
+"0x68BE","JUNIPER_68BE","JUNIPER",,,,,,"ATI Radeon HD 5700 Series"
+"0x68C0","REDWOOD_68C0","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68C1","REDWOOD_68C1","REDWOOD",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68C8","REDWOOD_68C8","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68C9","REDWOOD_68C9","REDWOOD",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68D8","REDWOOD_68D8","REDWOOD",,,,,,"ATI Radeon HD 5670"
+"0x68D9","REDWOOD_68D9","REDWOOD",,,,,,"ATI Radeon HD 5570"
+"0x68DA","REDWOOD_68DA","REDWOOD",,,,,,"ATI Radeon HD 5500 Series"
+"0x68DE","REDWOOD_68DE","REDWOOD",,,,,,"REDWOOD"
+"0x68E0","CEDAR_68E0","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68E1","CEDAR_68E1","CEDAR",1,,,,,"ATI Mobility Radeon HD 5000 Series"
+"0x68E4","CEDAR_68E4","CEDAR",1,,,,,"CEDAR"
+"0x68E5","CEDAR_68E5","CEDAR",1,,,,,"CEDAR"
+"0x68E8","CEDAR_68E8","CEDAR",,,,,,"CEDAR"
+"0x68E9","CEDAR_68E9","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68F1","CEDAR_68F1","CEDAR",,,,,,"ATI FirePro (FireGL) Graphics Adapter"
+"0x68F8","CEDAR_68F8","CEDAR",,,,,,"CEDAR"
+"0x68F9","CEDAR_68F9","CEDAR",,,,,,"ATI Radeon HD 5450"
+"0x68FE","CEDAR_68FE","CEDAR",,,,,,"CEDAR"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 41144c7..bdbd358 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -373,4 +373,39 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x9712, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9713, CHIP_FAMILY_RS880, 1, 1, 0, 0, 1 },
{ 0x9714, CHIP_FAMILY_RS880, 0, 1, 0, 0, 1 },
+ { 0x6880, CHIP_FAMILY_CYPRESS, 1, 0, 0, 0, 0 },
+ { 0x6888, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x6889, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x688A, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x6898, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x6899, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x689E, CHIP_FAMILY_CYPRESS, 0, 0, 0, 0, 0 },
+ { 0x689C, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 },
+ { 0x689D, CHIP_FAMILY_HEMLOCK, 0, 0, 0, 0, 0 },
+ { 0x68A0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
+ { 0x68A1, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
+ { 0x68A8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68A9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68B0, CHIP_FAMILY_JUNIPER, 1, 0, 0, 0, 0 },
+ { 0x68B8, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68B9, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68BE, CHIP_FAMILY_JUNIPER, 0, 0, 0, 0, 0 },
+ { 0x68C0, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 },
+ { 0x68C1, CHIP_FAMILY_REDWOOD, 1, 0, 0, 0, 0 },
+ { 0x68C8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68C9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68D8, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68D9, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68DA, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68DE, CHIP_FAMILY_REDWOOD, 0, 0, 0, 0, 0 },
+ { 0x68E0, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E1, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E4, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E5, CHIP_FAMILY_CEDAR, 1, 0, 0, 0, 0 },
+ { 0x68E8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68E9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68F1, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68F8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68F9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x68FE, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index fc41c3d..da0d3b4 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -373,5 +373,40 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD 4200" },
{ PCI_CHIP_RS880_9713, "ATI Mobility Radeon 4100" },
{ PCI_CHIP_RS880_9714, "ATI RS880" },
+ { PCI_CHIP_CYPRESS_6880, "CYPRESS" },
+ { PCI_CHIP_CYPRESS_6888, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CYPRESS_6889, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CYPRESS_688A, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CYPRESS_6898, "ATI Radeon HD 5800 Series" },
+ { PCI_CHIP_CYPRESS_6899, "ATI Radeon HD 5800 Series" },
+ { PCI_CHIP_CYPRESS_689E, "ATI Radeon HD 5800 Series" },
+ { PCI_CHIP_HEMLOCK_689C, "ATI Radeon HD 5900 Series" },
+ { PCI_CHIP_HEMLOCK_689D, "ATI Radeon HD 5900 Series" },
+ { PCI_CHIP_JUNIPER_68A0, "ATI Mobility Radeon HD 5800 Series" },
+ { PCI_CHIP_JUNIPER_68A1, "ATI Mobility Radeon HD 5800 Series" },
+ { PCI_CHIP_JUNIPER_68A8, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_JUNIPER_68A9, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_JUNIPER_68B0, "ATI Mobility Radeon HD 5800 Series" },
+ { PCI_CHIP_JUNIPER_68B8, "ATI Radeon HD 5700 Series" },
+ { PCI_CHIP_JUNIPER_68B9, "ATI Radeon HD 5700 Series" },
+ { PCI_CHIP_JUNIPER_68BE, "ATI Radeon HD 5700 Series" },
+ { PCI_CHIP_REDWOOD_68C0, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_REDWOOD_68C1, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_REDWOOD_68C8, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_REDWOOD_68C9, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_REDWOOD_68D8, "ATI Radeon HD 5670" },
+ { PCI_CHIP_REDWOOD_68D9, "ATI Radeon HD 5570" },
+ { PCI_CHIP_REDWOOD_68DA, "ATI Radeon HD 5500 Series" },
+ { PCI_CHIP_REDWOOD_68DE, "REDWOOD" },
+ { PCI_CHIP_CEDAR_68E0, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_CEDAR_68E1, "ATI Mobility Radeon HD 5000 Series" },
+ { PCI_CHIP_CEDAR_68E4, "CEDAR" },
+ { PCI_CHIP_CEDAR_68E5, "CEDAR" },
+ { PCI_CHIP_CEDAR_68E8, "CEDAR" },
+ { PCI_CHIP_CEDAR_68E9, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CEDAR_68F1, "ATI FirePro (FireGL) Graphics Adapter" },
+ { PCI_CHIP_CEDAR_68F8, "CEDAR" },
+ { PCI_CHIP_CEDAR_68F9, "ATI Radeon HD 5450" },
+ { PCI_CHIP_CEDAR_68FE, "CEDAR" },
{ -1, NULL }
};
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 1b85dcc..1f1b97e 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -373,5 +373,40 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RS880_9712, PCI_CHIP_RS880_9712, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9713, PCI_CHIP_RS880_9713, RES_SHARED_VGA },
{ PCI_CHIP_RS880_9714, PCI_CHIP_RS880_9714, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6880, PCI_CHIP_CYPRESS_6880, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6888, PCI_CHIP_CYPRESS_6888, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6889, PCI_CHIP_CYPRESS_6889, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_688A, PCI_CHIP_CYPRESS_688A, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6898, PCI_CHIP_CYPRESS_6898, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_6899, PCI_CHIP_CYPRESS_6899, RES_SHARED_VGA },
+ { PCI_CHIP_CYPRESS_689E, PCI_CHIP_CYPRESS_689E, RES_SHARED_VGA },
+ { PCI_CHIP_HEMLOCK_689C, PCI_CHIP_HEMLOCK_689C, RES_SHARED_VGA },
+ { PCI_CHIP_HEMLOCK_689D, PCI_CHIP_HEMLOCK_689D, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A0, PCI_CHIP_JUNIPER_68A0, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A1, PCI_CHIP_JUNIPER_68A1, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A8, PCI_CHIP_JUNIPER_68A8, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68A9, PCI_CHIP_JUNIPER_68A9, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68B0, PCI_CHIP_JUNIPER_68B0, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68B8, PCI_CHIP_JUNIPER_68B8, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68B9, PCI_CHIP_JUNIPER_68B9, RES_SHARED_VGA },
+ { PCI_CHIP_JUNIPER_68BE, PCI_CHIP_JUNIPER_68BE, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C0, PCI_CHIP_REDWOOD_68C0, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C1, PCI_CHIP_REDWOOD_68C1, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C8, PCI_CHIP_REDWOOD_68C8, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68C9, PCI_CHIP_REDWOOD_68C9, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68D8, PCI_CHIP_REDWOOD_68D8, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68D9, PCI_CHIP_REDWOOD_68D9, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68DA, PCI_CHIP_REDWOOD_68DA, RES_SHARED_VGA },
+ { PCI_CHIP_REDWOOD_68DE, PCI_CHIP_REDWOOD_68DE, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E0, PCI_CHIP_CEDAR_68E0, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E1, PCI_CHIP_CEDAR_68E1, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E4, PCI_CHIP_CEDAR_68E4, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E5, PCI_CHIP_CEDAR_68E5, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E8, PCI_CHIP_CEDAR_68E8, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68E9, PCI_CHIP_CEDAR_68E9, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68F1, PCI_CHIP_CEDAR_68F1, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68F8, PCI_CHIP_CEDAR_68F8, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68F9, PCI_CHIP_CEDAR_68F9, RES_SHARED_VGA },
+ { PCI_CHIP_CEDAR_68FE, PCI_CHIP_CEDAR_68FE, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 64127bd..fa44875 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -373,5 +373,40 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9712, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9713, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS880_9714, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6880, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6888, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6889, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_688A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6898, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_6899, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CYPRESS_689E, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689C, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_HEMLOCK_689D, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68A9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68B9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_JUNIPER_68BE, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68C9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68D9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DA, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_REDWOOD_68DE, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E4, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E5, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68E9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FE, 0 ),
{ 0, 0, 0 }
};
commit cb2772b69480268c059766c4f6b209ce590ede0e
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Fri Jan 29 12:59:46 2010 -0500
evergreen: add atombios crtc/pll functions
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index f832374..4044202 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -290,7 +290,146 @@ atombios_set_crtc_dtd_timing(xf86CrtcPtr crtc, DisplayModePtr mode)
return ATOM_NOT_IMPLEMENTED;
}
-void
+static void
+atombios_pick_pll(xf86CrtcPtr crtc)
+{
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
+ xf86OutputPtr output;
+ RADEONOutputPrivatePtr radeon_output;
+ int o, c;
+ uint32_t pll_use_mask = 0;
+ Bool is_dp = FALSE;
+
+ if (IS_DCE4_VARIANT) {
+ for (o = 0; o < xf86_config->num_output; o++) {
+ output = xf86_config->output[o];
+ if (output->crtc == crtc) {
+ int mode = atombios_get_encoder_mode(output);
+ radeon_output = output->driver_private;
+
+ if (mode == ATOM_ENCODER_MODE_DP) {
+ is_dp = TRUE;
+ break;
+ } else {
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr test_crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_test_crtc = test_crtc->driver_private;
+
+ if (crtc != test_crtc && (radeon_test_crtc->pll_id >= 0))
+ pll_use_mask |= (1 << radeon_test_crtc->pll_id);
+
+ }
+ }
+ }
+ }
+ if (is_dp)
+ radeon_crtc->pll_id = 2;
+ else if (!(pll_use_mask & 1))
+ radeon_crtc->pll_id = 0;
+ else
+ radeon_crtc->pll_id = 1;
+ } else
+ radeon_crtc->pll_id = radeon_crtc->crtc_id;
+
+ ErrorF("Picked PLL %d\n", radeon_crtc->pll_id);
+
+ for (o = 0; o < xf86_config->num_output; o++) {
+ output = xf86_config->output[o];
+ if (output->crtc == crtc) {
+ radeon_output = output->driver_private;
+ radeon_output->pll_id = radeon_crtc->pll_id;
+ }
+ }
+}
+
+static void
+atombios_crtc_set_dcpll(xf86CrtcPtr crtc)
+{
+ RADEONInfoPtr info = RADEONPTR(crtc->scrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(crtc->scrn);
+ xf86OutputPtr output = NULL;
+ RADEONOutputPrivatePtr radeon_output = NULL;
+ radeon_encoder_ptr radeon_encoder = NULL;
+ int index;
+ int major, minor, i;
+ PIXEL_CLOCK_PARAMETERS_V5 args;
+ AtomBiosArgRec data;
+ unsigned char *space;
+
+ memset(&args, 0, sizeof(args));
+
+ for (i = 0; i < xf86_config->num_output; i++) {
+ output = xf86_config->output[i];
+ if (output->crtc == crtc) {
+ radeon_output = output->driver_private;
+ radeon_encoder = radeon_get_encoder(output);
+ break;
+ }
+ }
+
+ if (radeon_output == NULL) {
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No output assigned to crtc!\n");
+ return;
+ }
+
+ if (radeon_encoder == NULL) {
+ xf86DrvMsg(crtc->scrn->scrnIndex, X_ERROR, "No encoder assigned to output!\n");
+ return;
+ }
+
+ index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
+
+ /*ErrorF("table is %d %d\n", major, minor);*/
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 5:
+ args.ucCRTC = ATOM_CRTC_INVALID;
+ args.usPixelClock = 60000; // 600 Mhz
+ args.ucPostDiv = info->pll.pll_out_max / 60000;
+ if (info->pll.reference_freq == 10000) {
+ // 100 Mhz ref clock
+ args.ucRefDiv = 7;
+ args.usFbDiv = cpu_to_le16(84);
+ args.ulFbDivDecFrac = cpu_to_le32(0);
+ } else {
+ // 27 Mhz ref clock
+ args.ucRefDiv = 2;
+ args.usFbDiv = cpu_to_le16(88);
+ args.ulFbDivDecFrac = cpu_to_le32(888889);
+ }
+ args.ucPpll = ATOM_DCPLL;
+ args.ucMiscInfo = 0; //HDMI depth
+ args.ucTransmitterID = radeon_encoder->encoder_id;
+ args.ucEncoderMode = atombios_get_encoder_mode(output);
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &args;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Set DCPLL success\n");
+ return;
+ }
+
+ ErrorF("Set DCPLL failed\n");
+ return;
+}
+
+static void
atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
{
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
@@ -304,15 +443,18 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
+ PIXEL_CLOCK_PARAMETERS_V5 *spc5_ptr;
xf86OutputPtr output = NULL;
RADEONOutputPrivatePtr radeon_output = NULL;
radeon_encoder_ptr radeon_encoder = NULL;
int pll_flags = 0;
uint32_t temp;
- void *ptr;
AtomBiosArgRec data;
unsigned char *space;
+ if (IS_DCE4_VARIANT)
+ atombios_crtc_set_dcpll(crtc);
+
memset(&spc_param, 0, sizeof(spc_param));
if (IS_AVIVO_VARIANT) {
if ((info->ChipFamily == CHIP_FAMILY_RS600) ||
@@ -338,12 +480,23 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
}
/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
- if (radeon_crtc->crtc_id == 0) {
- temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ if (IS_DCE4_VARIANT) {
+ /* XXX 6 crtcs, but only 2 plls */
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(EVERGREEN_P1PLL_SS_CNTL);
+ OUTREG(EVERGREEN_P1PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
+ } else {
+ temp = INREG(EVERGREEN_P2PLL_SS_CNTL);
+ OUTREG(EVERGREEN_P2PLL_SS_CNTL, temp & ~EVERGREEN_PxPLL_SS_EN);
+ }
} else {
- temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
- OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ if (radeon_crtc->crtc_id == 0) {
+ temp = INREG(AVIVO_P1PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
+ } else {
+ temp = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ OUTREG(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
+ }
}
} else {
pll_flags |= RADEON_PLL_LEGACY;
@@ -369,7 +522,8 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
if (IS_DCE3_VARIANT) {
ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_param;
- index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
+ ADJUST_DISPLAY_PLL_PS_ALLOCATION *adp_ptr;
+ ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 *adp3_ptr;
/* Can't really do cloning easily on DCE3 cards */
for (i = 0; i < xf86_config->num_output; i++) {
@@ -377,6 +531,11 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
if (output->crtc == crtc) {
radeon_output = output->driver_private;
radeon_encoder = radeon_get_encoder(output);
+ /* no need to set pll for DP */
+ if (IS_DCE4_VARIANT) {
+ if (atombios_get_encoder_mode(output) == ATOM_ENCODER_MODE_DP)
+ return;
+ }
break;
}
}
@@ -392,19 +551,67 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
}
memset(&adjust_pll_param, 0, sizeof(adjust_pll_param));
- adjust_pll_param.usPixelClock = cpu_to_le16(sclock / 10);
- adjust_pll_param.ucTransmitterID = radeon_encoder->encoder_id;
- adjust_pll_param.ucEncodeMode = atombios_get_encoder_mode(output);
+
+ index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
+ atombios_get_command_table_version(info->atomBIOS, index, &major, &minor);
data.exec.index = index;
data.exec.dataSpace = (void *)&space;
data.exec.pspace = &adjust_pll_param;
- ErrorF("before %d\n", adjust_pll_param.usPixelClock);
- if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
- sclock = le16_to_cpu(adjust_pll_param.usPixelClock) * 10;
+ switch(major) {
+ case 1:
+ switch(minor) {
+ case 1:
+ case 2:
+ adp_ptr = (ADJUST_DISPLAY_PLL_PS_ALLOCATION*)&adjust_pll_param.usPixelClock;
+ adp_ptr->usPixelClock = cpu_to_le16(sclock / 10);
+ adp_ptr->ucTransmitterID = radeon_encoder->encoder_id;
+ adp_ptr->ucEncodeMode = atombios_get_encoder_mode(output);
+
+ ErrorF("before %d\n", adp_ptr->usPixelClock);
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ sclock = le16_to_cpu(adp_ptr->usPixelClock) * 10;
+ }
+ ErrorF("after %d\n", adp_ptr->usPixelClock);
+ break;
+ case 3:
+ adp3_ptr = (ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3*)&adjust_pll_param.usPixelClock;
+ adp3_ptr->sInput.usPixelClock = cpu_to_le16(sclock / 10);
+ adp3_ptr->sInput.ucTransmitterID = radeon_encoder->encoder_id;
+ adp3_ptr->sInput.ucEncodeMode = atombios_get_encoder_mode(output);
+ adp3_ptr->sInput.ucDispPllConfig = 0;
+ if (radeon_output->coherent_mode)
+ adp3_ptr->sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE;
+ if (sclock > 165000)
+ adp3_ptr->sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK;
+ // if SS
+ // adp3_ptr->sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE;
+
+ ErrorF("before %d 0x%x\n", adp3_ptr->sInput.usPixelClock, adp3_ptr->sInput.ucDispPllConfig);
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ sclock = adp3_ptr->sOutput.ulDispPllFreq * 10;
+ if (adp3_ptr->sOutput.ucRefDiv) {
+ pll_flags |= RADEON_PLL_USE_REF_DIV;
+ info->pll.reference_div = adp3_ptr->sOutput.ucRefDiv;
+ }
+ if (adp3_ptr->sOutput.ucPostDiv) {
+ pll_flags |= RADEON_PLL_USE_POST_DIV;
+ info->pll.post_div = adp3_ptr->sOutput.ucPostDiv;
+ }
+ ErrorF("after %d %d %d\n", adp3_ptr->sOutput.ulDispPllFreq,
+ adp3_ptr->sOutput.ucRefDiv, adp3_ptr->sOutput.ucPostDiv);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
+ }
+ break;
+ default:
+ ErrorF("Unknown table version\n");
+ exit(-1);
}
- ErrorF("after %d\n", adjust_pll_param.usPixelClock);
}
if (IS_AVIVO_VARIANT) {
@@ -439,10 +646,9 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
spc2_ptr->ucFracFbDiv = frac_fb_div;
spc2_ptr->ucPostDiv = post_div;
- spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc2_ptr->ucPpll = radeon_crtc->pll_id;
spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
spc2_ptr->ucRefDivSrc = 1;
- ptr = &spc_param;
break;
case 3:
spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
@@ -451,12 +657,23 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
spc3_ptr->ucFracFbDiv = frac_fb_div;
spc3_ptr->ucPostDiv = post_div;
- spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+ spc3_ptr->ucPpll = radeon_crtc->pll_id;
spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
spc3_ptr->ucEncoderMode = atombios_get_encoder_mode(output);
-
- ptr = &spc_param;
+ break;
+ case 5:
+ spc5_ptr = (PIXEL_CLOCK_PARAMETERS_V5*)&spc_param.sPCLKInput;
+ spc5_ptr->ucCRTC = radeon_crtc->crtc_id;
+ spc5_ptr->usPixelClock = cpu_to_le16(mode->Clock / 10);
+ spc5_ptr->ucRefDiv = ref_div;
+ spc5_ptr->usFbDiv = cpu_to_le16(fb_div);
+ spc5_ptr->ulFbDivDecFrac = cpu_to_le32(frac_fb_div);
+ spc5_ptr->ucPostDiv = post_div;
+ spc5_ptr->ucPpll = radeon_crtc->pll_id;
+ spc5_ptr->ucMiscInfo = 0; //HDMI depth
+ spc5_ptr->ucTransmitterID = radeon_encoder->encoder_id;
+ spc5_ptr->ucEncoderMode = atombios_get_encoder_mode(output);
break;
default:
ErrorF("Unknown table version\n");
@@ -470,7 +687,7 @@ atombios_crtc_set_pll(xf86CrtcPtr crtc, DisplayModePtr mode)
data.exec.index = index;
data.exec.dataSpace = (void *)&space;
- data.exec.pspace = ptr;
+ data.exec.pspace = &spc_param;
if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
ErrorF("Set CRTC %d PLL success\n", radeon_crtc->crtc_id);
@@ -756,10 +973,15 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
RADEONInitMemMapRegisters(pScrn, info->ModeReg, info);
RADEONRestoreMemMapRegisters(pScrn, info->ModeReg);
+ atombios_pick_pll(crtc);
atombios_crtc_set_pll(crtc, adjusted_mode);
- atombios_set_crtc_timing(crtc, adjusted_mode);
- if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0))
+ if (IS_DCE4_VARIANT)
atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
+ else {
+ atombios_set_crtc_timing(crtc, adjusted_mode);
+ if (!IS_AVIVO_VARIANT && (radeon_crtc->crtc_id == 0))
+ atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
+ }
if (IS_DCE4_VARIANT)
evergreen_set_base_format(crtc, mode, adjusted_mode, x, y);
diff --git a/src/atombios_output.c b/src/atombios_output.c
index b56d8a0..d7c396b 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -765,11 +765,8 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
//if (radeon_output->dig_encoder)
// disp_data.v2.acConfig.ucEncoderSel = 1;
- // XXX select the PLL
- if (radeon_output->dig_encoder)
- disp_data.v3.acConfig.ucRefClkSource = 1; // PLL2
- else
- disp_data.v3.acConfig.ucRefClkSource = 0; // PLL1
+ // select the PLL
+ disp_data.v3.acConfig.ucRefClkSource = radeon_output->pll_id;
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index b5ce9f6..556b461 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -773,6 +773,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[0]->can_tile = 1;
else
pRADEONEnt->Controller[0]->can_tile = 0;
+ pRADEONEnt->Controller[0]->pll_id = -1;
}
if (mask & 2) {
@@ -801,6 +802,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[1]->can_tile = 1;
else
pRADEONEnt->Controller[1]->can_tile = 0;
+ pRADEONEnt->Controller[1]->pll_id = -1;
}
/* 6 crtcs on DCE4 chips */
@@ -844,6 +846,7 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
pRADEONEnt->Controller[i]->can_tile = 1;
else
pRADEONEnt->Controller[i]->can_tile = 0;
+ pRADEONEnt->Controller[i]->pll_id = -1;
}
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 7cdf2de..dc02bdf 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -163,6 +163,7 @@ typedef struct _RADEONCrtcPrivateRec {
Bool scaler_enabled;
float vsc;
float hsc;
+ int pll_id;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct _radeon_encoder {
@@ -299,6 +300,7 @@ typedef struct _RADEONOutputPrivateRec {
int dp_lane_count;
int dp_clock;
uint8_t hpd_id;
+ int pll_id;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
struct avivo_pll_state {
commit bd8e04cb7b39f38b6958273582a9b324a9f0759a
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Feb 1 10:07:43 2010 -0500
evergreen: add atom support for digital outputs
analog is already supported by the existing code.
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 6a769b0..b56d8a0 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -645,9 +645,58 @@ atombios_output_dig_encoder_setup(xf86OutputPtr output, int action)
}
+static int
+atombios_dce4_output_dig_encoder_setup(xf86OutputPtr output, int action)
+{
+ RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(output->scrn);
+ radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
+ DIG_ENCODER_CONTROL_PARAMETERS_V3 disp_data;
+ AtomBiosArgRec data;
+ unsigned char *space;
+ int index;
+ int clock = radeon_output->pixel_clock;
+
+ if (radeon_encoder == NULL)
+ return ATOM_NOT_IMPLEMENTED;
+
+ memset(&disp_data,0, sizeof(disp_data));
+
+ index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
+
+ disp_data.ucAction = action;
+ disp_data.usPixelClock = cpu_to_le16(clock / 10);
+ disp_data.ucEncoderMode = atombios_get_encoder_mode(output);
+ disp_data.acConfig.ucDigSel = radeon_output->dig_encoder;
+
+ if (disp_data.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
+ if (dp_link_clock_for_mode_clock(radeon_output, clock) == 27000)
+ disp_data.acConfig.ucDPLinkRate = 1;
+ disp_data.ucLaneNum = dp_lanes_for_mode_clock(radeon_output, clock);
+ } else if (clock > 165000)
+ disp_data.ucLaneNum = 8;
+ else
+ disp_data.ucLaneNum = 4;
+
+ disp_data.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+
+ data.exec.index = index;
+ data.exec.dataSpace = (void *)&space;
+ data.exec.pspace = &disp_data;
+
+ if (RHDAtomBiosFunc(info->atomBIOS->scrnIndex, info->atomBIOS, ATOMBIOS_EXEC, &data) == ATOM_SUCCESS) {
+ ErrorF("Output DIG%d encoder setup success\n", radeon_output->dig_encoder);
+ return ATOM_SUCCESS;
+ }
+
+ ErrorF("Output DIG%d setup failed\n", radeon_output->dig_encoder);
+ return ATOM_NOT_IMPLEMENTED;
+}
+
union dig_transmitter_control {
DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
+ DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
};
static int
@@ -668,7 +717,7 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
memset(&disp_data,0, sizeof(disp_data));
- if (IS_DCE32_VARIANT)
+ if (IS_DCE32_VARIANT || IS_DCE4_VARIANT)
index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
else {
switch (radeon_encoder->encoder_id) {
@@ -685,7 +734,65 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
disp_data.v1.ucAction = action;
- if (IS_DCE32_VARIANT) {
+ if (IS_DCE4_VARIANT) {
+ if (action == ATOM_TRANSMITTER_ACTION_INIT) {
+ disp_data.v3.usInitInfo = radeon_output->connector_object_id;
+ } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
+ disp_data.v3.asMode.ucLaneSel = lane_num;
+ disp_data.v3.asMode.ucLaneSet = lane_set;
+ } else {
+ if (radeon_output->MonType == MT_DP) {
+ disp_data.v3.usPixelClock =
+ cpu_to_le16(dp_link_clock_for_mode_clock(radeon_output, clock));
+ } else if (clock > 165000) {
+ disp_data.v3.usPixelClock = cpu_to_le16((clock / 2) / 10);
+ disp_data.v3.acConfig.fDualLinkConnector = 1;
+ } else {
+ disp_data.v3.usPixelClock = cpu_to_le16(clock / 10);
+ }
+ }
+
+ if (radeon_output->MonType == MT_DP)
+ disp_data.v3.ucLaneNum = dp_lanes_for_mode_clock(radeon_output, clock);
+ else if (clock > 165000)
+ disp_data.v3.ucLaneNum = 8;
+ else
+ disp_data.v3.ucLaneNum = 4;
+
+ if (radeon_output->linkb)
+ disp_data.v3.acConfig.ucLinkSel = 1;
+
+ //if (radeon_output->dig_encoder)
+ // disp_data.v2.acConfig.ucEncoderSel = 1;
+
+ // XXX select the PLL
+ if (radeon_output->dig_encoder)
+ disp_data.v3.acConfig.ucRefClkSource = 1; // PLL2
+ else
+ disp_data.v3.acConfig.ucRefClkSource = 0; // PLL1
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ disp_data.v3.acConfig.ucTransmitterSel = 0;
+ num = 0;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ disp_data.v3.acConfig.ucTransmitterSel = 1;
+ num = 1;
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ disp_data.v3.acConfig.ucTransmitterSel = 2;
+ num = 2;
+ break;
+ }
+
+ if (radeon_output->MonType == MT_DP)
+ disp_data.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
+ else if (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT)) {
+ if (radeon_output->coherent_mode)
+ disp_data.v3.acConfig.fCoherentMode = 1;
+ }
+ } else if (IS_DCE32_VARIANT) {
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
disp_data.v2.usInitInfo = radeon_output->connector_object_id;
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
@@ -736,8 +843,8 @@ atombios_output_dig_transmitter_setup(xf86OutputPtr output, int action, uint8_t
if (action == ATOM_TRANSMITTER_ACTION_INIT) {
disp_data.v1.usInitInfo = radeon_output->connector_object_id;
} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
- disp_data.v2.asMode.ucLaneSel = lane_num;
- disp_data.v2.asMode.ucLaneSet = lane_set;
+ disp_data.v1.asMode.ucLaneSel = lane_num;
+ disp_data.v1.asMode.ucLaneSet = lane_set;
} else {
if (radeon_output->MonType == MT_DP)
disp_data.v1.usPixelClock =
@@ -1443,10 +1550,26 @@ atombios_set_output_crtc_source(xf86OutputPtr output)
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
- if (radeon_output->dig_encoder)
- crtc_src_param2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
- else
- crtc_src_param2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
+ switch (radeon_output->dig_encoder) {
+ case 0:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
+ break;
+ case 1:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
+ break;
+ case 2:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
+ break;
+ case 3:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
+ break;
+ case 4:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
+ break;
+ case 5:
+ crtc_src_param2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
+ break;
+ }
break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT))
@@ -1517,7 +1640,9 @@ atombios_apply_output_quirks(xf86OutputPtr output, DisplayModePtr mode)
OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
}
- if (IS_DCE32_VARIANT && (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
+ if (IS_DCE32_VARIANT &&
+ (!IS_DCE4_VARIANT) &&
+ (radeon_output->active_device & (ATOM_DEVICE_DFP_SUPPORT))) {
radeon_encoder_ptr radeon_encoder = radeon_get_encoder(output);
if (radeon_encoder == NULL)
return;
@@ -1536,6 +1661,7 @@ atombios_pick_dig_encoder(xf86OutputPtr output)
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(output->scrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
+ radeon_encoder_ptr radeon_encoder = NULL;
Bool is_lvtma = FALSE;
int i, mode;
uint32_t dig_enc_use_mask = 0;
@@ -1547,6 +1673,35 @@ atombios_pick_dig_encoder(xf86OutputPtr output)
mode == ATOM_ENCODER_MODE_CV)
return;
+ if (IS_DCE4_VARIANT) {
+ radeon_encoder = radeon_get_encoder(output);
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ if (radeon_output->linkb)
+ radeon_output->dig_encoder = 1;
+ else
+ radeon_output->dig_encoder = 0;
+ break;
Reply to: