xserver-xorg-video-ati: Changes to 'debian-unstable'
ChangeLog | 208 +++++++++++++++++++++++++++++++++++++++
configure.ac | 24 ++--
debian/changelog | 9 +
man/radeon.man | 4
src/AtomBios/CD_Operations.c | 7 +
src/AtomBios/includes/Decoder.h | 1
src/AtomBios/includes/ObjectID.h | 127 +++++++++++++++++++++++
src/AtomBios/includes/atombios.h | 199 +++++++++++++++++++++++++++++++++++++
src/atombios_output.c | 12 ++
src/legacy_crtc.c | 17 ++-
src/legacy_output.c | 27 ++++-
src/r600_exa.c | 10 +
src/radeon_driver.c | 27 ++++-
src/radeon_exa_render.c | 28 ++++-
src/radeon_modes.c | 14 ++
src/radeon_output.c | 56 ++++++++++
16 files changed, 738 insertions(+), 32 deletions(-)
New commits:
commit 372823c9658c6d9aaa9277491ab566b82ca60a0e
Author: Brice Goglin <bgoglin@debian.org>
Date: Wed Jan 27 16:44:34 2010 +0100
Prepare changelog for upload
diff --git a/debian/changelog b/debian/changelog
index f52bf69..962db64 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-xserver-xorg-video-ati (1:6.12.4-3) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.12.4-3) unstable; urgency=low
[ Julien Cristau ]
* Rename the build directory to not include DEB_BUILD_GNU_TYPE for no
@@ -8,7 +8,7 @@ xserver-xorg-video-ati (1:6.12.4-3) UNRELEASED; urgency=low
* Pull upstream 6.12-branch up to commit 712ac98a.
+ Some EXA fixes, closes: #565506.
- -- Julien Cristau <jcristau@debian.org> Sat, 16 Jan 2010 16:57:39 +0000
+ -- Brice Goglin <bgoglin@debian.org> Wed, 27 Jan 2010 16:44:30 +0100
xserver-xorg-video-ati (1:6.12.4-2) unstable; urgency=low
commit 8b8e5dc8cc8a196b2a0080ad847eef463c1e0081
Author: Brice Goglin <bgoglin@debian.org>
Date: Wed Jan 27 16:41:38 2010 +0100
New upstream snapshot
diff --git a/ChangeLog b/ChangeLog
index ef0f5f3..81ff17e 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,211 @@
+commit 712ac98af7cd862e802a8f735318dfb9c6a7ad28
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Jan 19 11:59:38 2010 -0500
+
+ ATOM: Upstream parser updates
+
+commit 664ab901c09872c27d3d2ed76c9a48c10ce274da
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Thu Jan 7 01:52:35 2010 -0500
+
+ radeon: updated ObjectID.h
+
+commit 687521bd16027c26e1b9f206cdedb19e2fce8910
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Dec 21 17:32:40 2009 -0500
+
+ ATOM: add new power table defs
+
+commit a89b7b880a464cbd416c1ad23663d07efb07c9af
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Jan 11 15:13:45 2010 -0500
+
+ rv100: fix typo in fix for bug 25992
+
+ Noticed by Maarten Maathuis.
+
+commit 6065ca92763fef1a08185854fc07fb60259ca99e
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Jan 4 11:05:44 2010 -0500
+
+ radeon: fix LVDS power sequence on Mac cards
+
+ Noticed by John R. Dunning. Fix taken from radeonfb.
+
+ I'm not sure if this sequence would be useful on any PC
+ laptops or not so make it mac specific for now.
+
+commit e8b9de06482ff792b8d7fa40ce3bc024caca62f6
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Jan 11 12:40:06 2010 -0500
+
+ rv100: reject modes >135 Mhz with DVI
+
+ Due to heat issues. fixes bug 25992
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 587f693886e9025ba6fc30a8405902c43b2fcfb2
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Dec 22 08:45:27 2009 -0500
+
+ radeon: add cvt timing if we only have panel w/h
+
+ fixes mac laptops without an edid
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit e7b26abc3c20fb53bf2cd02404ac5e0654fee18d
+Author: Matthias Hopf <mhopf@suse.de>
+Date: Tue Dec 15 10:53:48 2009 -0500
+
+ fix 200M freezes on VT switch if CRTC is disabled
+
+ It appears that RS4xx chips need to have the crtc
+ enabled when the timing is programmed.
+
+ agd5f: minor fixes/cleanup of the original patch
+
+commit 45edca0e9d7b833b9de3037e94f293122c922e42
+Author: Michel Dänzer <daenzer@vmware.com>
+Date: Thu Sep 3 14:55:05 2009 +0200
+
+ EXA: Check for solid/gradient pictures the same way for all generations.
+
+ In particular, also catch them for >= R300.
+
+commit 3d59746808bc5f335104d27a8dce0fe94ab3cb78
+Author: Matthijs Kooijman <matthijs@stdin.nl>
+Date: Thu Dec 3 12:10:14 2009 -0500
+
+ radeon: fix crtc2 dpms
+
+ noticed by Matthijs Kooijman on fdo bug 22140
+
+commit 26ecf3aad5f3a70b3267614bff6030604820f4d9
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Nov 23 12:54:41 2009 -0500
+
+ DCE3.2: fix uniphy2 dvi issues
+
+ In some cases the atom transmitter table sets the
+ golden value of this reg differently which some monitors
+ don't like. I haven't had time to dig further, so this
+ works around it for now.
+
+ Fixes fdo bug 24313
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 51266161f70baf4ddbf79ba6225ee2ae107a9f36
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Nov 17 14:16:22 2009 -0500
+
+ radeon: deal with connectors sourced to the same encoder
+
+ Some systems have multiple connectors connected to the
+ same encoder; e.g., DVI and HDMI connected to the same
+ encoder with the same ddc line. Since we expose
+ connectors as xrandr outputs, randr treats them separately
+ which results in it trying to source the same encoder to
+ different crtcs. If we have an HDMI and DVI-D port on the
+ same encoder, pick the one to be considered connected
+ based on the edid (HDMI if edid indicates HDMI, DVI
+ otherwise). Also, don't turn off (dpms) encoders that are
+ shared.
+
+ Fixes fdo bug 21767.
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit c2892cbd18e0f25401b615055425f727e096b7cd
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Tue Nov 17 11:45:09 2009 -0500
+
+ radeon: fix potential memory leak in ddc code
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit 93de38348fa77987297c3977d5acddbae54fbc10
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Thu Nov 12 11:11:17 2009 -0500
+
+ radeon: man page updates
+
+commit 6dc632e2e91b6a7159ab3a27617b031713d8b8c4
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Mon Nov 9 15:09:34 2009 -0500
+
+ IGP: some IGP chips report as AGP
+
+ Set bus type appropriately. fixes bug 25002
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit eab41805c0e6cc6deb7eca9342457b690834d7d2
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Thu Nov 5 10:23:03 2009 -0500
+
+ EXA: fallback if no pMaskPicture->pDrawable
+
+ A solid or gradient mask could be used for blending
+ the source picture onto the destination picture.
+
+ Fixes fdo bug 24838
+
+ Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
+
+commit ca9c619c9c085fac3bea486cfce1c8b5ba09cd52
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Fri Oct 30 17:36:29 2009 -0400
+
+ radeon: clamp the internal FB map to the aperture size v2
+
+ We don't use the invisible memory yet and on cards with
+ large amounts of vram this can cause the top of GART
+ calculation to overflow.
+
+ Fixes bug fdo bug 24301:
+ http://bugs.freedesktop.org/show_bug.cgi?id=24301
+
+ v2: only clamp cards with more than 512 MB. This seems
+ to cause problems on some older cards due to the way the
+ drm and ddx set up the internal memory map.
+
+commit 0db4b1708c2e5f3c14f48de186ee866ab8d9d5a9
+Author: Alex Deucher <alexdeucher@gmail.com>
+Date: Wed Oct 7 17:01:55 2009 -0400
+
+ radeon: clamp the internal FB map to the aperture size
+
+ We don't use the invisible memory yet and on cards with
+ large amounts of vram this can cause the top of GART
+ calculation to overflow.
+
+ Fixes bug fdo bug 24301:
+ http://bugs.freedesktop.org/show_bug.cgi?id=24301
+
+commit ecc192e2e5d72090bb35b142c6dc4639ec2542f0
+Author: Dave Airlie <airlied@linux.ie>
+Date: Sat Sep 26 06:03:51 2009 +1000
+
+ radeon: fix zaphod
+
+commit d1d3681748251fb7e95b8d56e6c37847ca6b1a8d
+Author: Michael Olbrich <m.olbrich@pengutronix.de>
+Date: Sun Sep 20 14:19:41 2009 +0200
+
+ use AC_CHECK_HEADER instead of AC_CHECK_FILE
+
+ AC_CHECK_FILE is not possible when cross-compiling. Use AC_CHECK_HEADER /
+ AC_PREPROC_IFELSE instead.
+
+ [ Michel Dänzer: Shuffled things around slightly to make it work on my setup ]
+
+ Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
+ Signed-off-by: Michel Dänzer <daenzer@vmware.com>
+ (cherry picked from commit 97a4e747bfac14f34646c55ddf639e8fe22f2f55)
+
commit b7c14b00ff6a217cb69727b384cc4f4b433a907e
Author: Dave Airlie <airlied@redhat.com>
Date: Fri Sep 11 09:31:46 2009 +1000
diff --git a/debian/changelog b/debian/changelog
index 41f1d85..f52bf69 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,8 +1,13 @@
xserver-xorg-video-ati (1:6.12.4-3) UNRELEASED; urgency=low
+ [ Julien Cristau ]
* Rename the build directory to not include DEB_BUILD_GNU_TYPE for no
good reason. Thanks, Colin Watson!
+ [ Brice Goglin ]
+ * Pull upstream 6.12-branch up to commit 712ac98a.
+ + Some EXA fixes, closes: #565506.
+
-- Julien Cristau <jcristau@debian.org> Sat, 16 Jan 2010 16:57:39 +0000
xserver-xorg-video-ati (1:6.12.4-2) unstable; urgency=low
commit 712ac98af7cd862e802a8f735318dfb9c6a7ad28
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Jan 19 11:59:38 2010 -0500
ATOM: Upstream parser updates
diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
index 6b28560..c1279b8 100644
--- a/src/AtomBios/CD_Operations.c
+++ b/src/AtomBios/CD_Operations.c
@@ -300,6 +300,9 @@ VOID PutDataWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
case WS_ATTRIBUTES_C:
pParserTempData->AttributesData=(UINT16)pParserTempData->DestData32;
break;
+ case WS_REGPTR_C:
+ pParserTempData->CurrentRegBlock=(UINT16)pParserTempData->DestData32;
+ break;
}
}
@@ -390,6 +393,8 @@ UINT32 GetParametersWS(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
return pParserTempData->CurrentFB_Window;
case WS_ATTRIBUTES_C:
return pParserTempData->AttributesData;
+ case WS_REGPTR_C:
+ return (UINT32)pParserTempData->CurrentRegBlock;
}
return 0;
@@ -502,7 +507,7 @@ VOID ProcessMask(PARSER_TEMP_DATA STACK_BASED * pParserTempData)
pParserTempData->DestData32=GetDestination[pParserTempData->ParametersType.Destination](pParserTempData);
pParserTempData->SourceData32=GetParametersDirect(pParserTempData);
- pParserTempData->Index=GetParametersDirect(pParserTempData);
+ pParserTempData->Index=GetSource[pParserTempData->ParametersType.Source](pParserTempData);
pParserTempData->SourceData32 <<= DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment];
pParserTempData->SourceData32 |= ~(AlignmentMask[pParserTempData->CD_Mask.SrcAlignment] << DestinationAlignmentShift[pParserTempData->CD_Mask.DestAlignment]);
pParserTempData->DestData32 &= pParserTempData->SourceData32;
diff --git a/src/AtomBios/includes/Decoder.h b/src/AtomBios/includes/Decoder.h
index 1e143f0..cc533ef 100644
--- a/src/AtomBios/includes/Decoder.h
+++ b/src/AtomBios/includes/Decoder.h
@@ -44,6 +44,7 @@ NEG:27.08.2002 Initiated.
#define WS_AND_MASK_C (WS_OR_MASK_C+1)
#define WS_FB_WINDOW_C (WS_AND_MASK_C+1)
#define WS_ATTRIBUTES_C (WS_FB_WINDOW_C+1)
+#define WS_REGPTR_C (WS_ATTRIBUTES_C+1)
#define PARSER_VERSION_MAJOR 0x00000000
#define PARSER_VERSION_MINOR 0x0000000E
#define PARSER_VERSION (PARSER_VERSION_MAJOR | PARSER_VERSION_MINOR)
commit 664ab901c09872c27d3d2ed76c9a48c10ce274da
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Thu Jan 7 01:52:35 2010 -0500
radeon: updated ObjectID.h
diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h
index f1f18a4..c714179 100644
--- a/src/AtomBios/includes/ObjectID.h
+++ b/src/AtomBios/includes/ObjectID.h
@@ -106,6 +106,8 @@
#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11
#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12
#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
+#define CONNECTOR_OBJECT_ID_eDP 0x14
+#define CONNECTOR_OBJECT_ID_MXM 0x15
/* deleted */
@@ -116,7 +118,15 @@
#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01
/****************************************************/
-// Graphics Object ENUM ID Definition */
+/* Generic Object ID Definition */
+/****************************************************/
+#define GENERIC_OBJECT_ID_NONE 0x00
+#define GENERIC_OBJECT_ID_GLSYNC 0x01
+#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02
+#define GENERIC_OBJECT_ID_MXM_OPM 0x03
+
+/****************************************************/
+/* Graphics Object ENUM ID Definition */
/****************************************************/
#define GRAPH_OBJECT_ENUM_ID1 0x01
#define GRAPH_OBJECT_ENUM_ID2 0x02
@@ -124,6 +134,7 @@
#define GRAPH_OBJECT_ENUM_ID4 0x04
#define GRAPH_OBJECT_ENUM_ID5 0x05
#define GRAPH_OBJECT_ENUM_ID6 0x06
+#define GRAPH_OBJECT_ENUM_ID7 0x07
/****************************************************/
/* Graphics Object ID Bit definition */
@@ -374,6 +385,18 @@
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+#define CONNECTOR_LVDS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
+
#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
@@ -402,6 +425,14 @@
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
@@ -414,37 +445,76 @@
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+#define CONNECTOR_COMPOSITE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+#define CONNECTOR_SVIDEO_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+#define CONNECTOR_YPbPr_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+#define CONNECTOR_D_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+#define CONNECTOR_9PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+#define CONNECTOR_SCART_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@@ -487,6 +557,42 @@
GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+#define CONNECTOR_DISPLAYPORT_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_MXM_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_A
+
+#define CONNECTOR_MXM_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_B
+
+#define CONNECTOR_MXM_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_C
+
+#define CONNECTOR_MXM_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_D
+
+#define CONNECTOR_MXM_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_TXxx
+
+#define CONNECTOR_MXM_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_UXxx
+
+#define CONNECTOR_MXM_ENUM_ID7 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
+ CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC
+
/****************************************************/
/* Router Object ID definition - Shared with BIOS */
/****************************************************/
@@ -497,6 +603,25 @@
/* deleted */
/****************************************************/
+/* Generic Object ID definition - Shared with BIOS */
+/****************************************************/
+#define GENERICOBJECT_GLSYNC_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+ GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
+
+#define GENERICOBJECT_MXM_OPM_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
+ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+ GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
+
+/****************************************************/
/* Object Cap definition - Shared with BIOS */
/****************************************************/
#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L
commit 687521bd16027c26e1b9f206cdedb19e2fce8910
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Dec 21 17:32:40 2009 -0500
ATOM: add new power table defs
diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h
index 7a3afa8..4a1f019 100644
--- a/src/AtomBios/includes/atombios.h
+++ b/src/AtomBios/includes/atombios.h
@@ -4926,7 +4926,204 @@ typedef struct _ATOM_POWERPLAY_INFO_V3
ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
}ATOM_POWERPLAY_INFO_V3;
-
+/* New PPlib */
+/**************************************************************************/
+typedef struct _ATOM_PPLIB_THERMALCONTROLLER
+
+{
+ UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_*
+ UCHAR ucI2cLine; // as interpreted by DAL I2C
+ UCHAR ucI2cAddress;
+ UCHAR ucFanParameters; // Fan Control Parameters.
+ UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only.
+ UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only.
+ UCHAR ucReserved; // ----
+ UCHAR ucFlags; // to be defined
+} ATOM_PPLIB_THERMALCONTROLLER;
+
+#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
+#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller.
+
+#define ATOM_PP_THERMALCONTROLLER_NONE 0
+#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_LM64 5
+#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib
+#define ATOM_PP_THERMALCONTROLLER_RV6xx 7
+#define ATOM_PP_THERMALCONTROLLER_RV770 8
+#define ATOM_PP_THERMALCONTROLLER_ADT7473 9
+
+typedef struct _ATOM_PPLIB_STATE
+{
+ UCHAR ucNonClockStateIndex;
+ UCHAR ucClockStateIndices[1]; // variable-sized
+} ATOM_PPLIB_STATE;
+
+//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
+#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
+#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
+#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
+#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
+#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
+#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
+#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
+#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
+#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
+#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
+#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
+#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
+
+typedef struct _ATOM_PPLIB_POWERPLAYTABLE
+{
+ ATOM_COMMON_TABLE_HEADER sHeader;
+
+ UCHAR ucDataRevision;
+
+ UCHAR ucNumStates;
+ UCHAR ucStateEntrySize;
+ UCHAR ucClockInfoSize;
+ UCHAR ucNonClockSize;
+
+ // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
+ USHORT usStateArrayOffset;
+
+ // offset from start of this table to array of ASIC-specific structures,
+ // currently ATOM_PPLIB_CLOCK_INFO.
+ USHORT usClockInfoArrayOffset;
+
+ // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
+ USHORT usNonClockInfoArrayOffset;
+
+ USHORT usBackbiasTime; // in microseconds
+ USHORT usVoltageTime; // in microseconds
+ USHORT usTableSize; //the size of this structure, or the extended structure
+
+ ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_*
+
+ ATOM_PPLIB_THERMALCONTROLLER sThermalController;
+
+ USHORT usBootClockInfoOffset;
+ USHORT usBootNonClockInfoOffset;
+
+} ATOM_PPLIB_POWERPLAYTABLE;
+
+//// ATOM_PPLIB_NONCLOCK_INFO::usClassification
+#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007
+#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0
+#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0
+#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1
+#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3
+#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5
+// 2, 4, 6, 7 are reserved
+
+#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008
+#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010
+#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020
+#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040
+#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080
+#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100
+#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200
+#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400
+#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800
+#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000
+// remaining 3 bits are reserved
+
+//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
+#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001
+#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002
+
+// 0 is 2.5Gb/s, 1 is 5Gb/s
+#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004
+#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2
+
+// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
+#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8
+#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3
+
+// lookup into reduced refresh-rate table
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
+
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0
+#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1
+// 2-15 TBD as needed.
+
+#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000
+#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000
+#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000
+
+#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000
+
+// Contained in an array starting at the offset
+// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
+// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
+typedef struct _ATOM_PPLIB_NONCLOCK_INFO
+{
+ USHORT usClassification;
+ UCHAR ucMinTemperature;
+ UCHAR ucMaxTemperature;
+ ULONG ulCapsAndSettings;
+ UCHAR ucRequiredPower;
+ UCHAR ucUnused1[3];
+} ATOM_PPLIB_NONCLOCK_INFO;
+
+// Contained in an array starting at the offset
+// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
+// referenced from ATOM_PPLIB_STATE::ucClockStateIndices
+typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
+{
+ USHORT usEngineClockLow;
+ UCHAR ucEngineClockHigh;
+
+ USHORT usMemoryClockLow;
+ UCHAR ucMemoryClockHigh;
+
+ USHORT usVDDC;
+ USHORT usUnused1;
+ USHORT usUnused2;
+
+ ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
+
+} ATOM_PPLIB_R600_CLOCK_INFO;
+
+// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
+#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1
+#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2
+#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4
+#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8
+#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16
+
+typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
+
+{
+ USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600).
+ UCHAR ucLowEngineClockHigh;
+ USHORT usHighEngineClockLow; // High Engine clock in MHz.
+ UCHAR ucHighEngineClockHigh;
+ USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
+ UCHAR ucMemoryClockHigh; // Currentyl unused.
+ UCHAR ucPadding; // For proper alignment and size.
+ USHORT usVDDC; // For the 780, use: None, Low, High, Variable
+ UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
+ UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
+ USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
+ ULONG ulFlags;
+} ATOM_PPLIB_RS780_CLOCK_INFO;
+
+#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
+#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
+#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
+#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
+
+#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
+#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
+#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
+
+#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
+#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
+#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
/**************************************************************************/
commit a89b7b880a464cbd416c1ad23663d07efb07c9af
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Jan 11 15:13:45 2010 -0500
rv100: fix typo in fix for bug 25992
Noticed by Maarten Maathuis.
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 4ff34b4..741589f 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -437,12 +437,14 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
}
}
- /* single link DVI check */
- if (pMode->Clock > 165000 && radeon_output->MonType == MT_DFP) {
- /* clocks over 135 MHz have heat issues with DVI on RV100 */
- if ((info->ChipFamily == CHIP_FAMILY_RV100) && (pMode->Clock > 135000))
+ /* clocks over 135 MHz have heat issues with DVI on RV100 */
+ if ((radeon_output->MonType == MT_DFP) &&
+ (info->ChipFamily == CHIP_FAMILY_RV100) &&
+ (pMode->Clock > 135000))
return MODE_CLOCK_HIGH;
+ /* single link DVI check */
+ if (pMode->Clock > 165000 && radeon_output->MonType == MT_DFP) {
/* DP->DVI converter */
if (radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT)
return MODE_CLOCK_HIGH;
commit 6065ca92763fef1a08185854fc07fb60259ca99e
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Jan 4 11:05:44 2010 -0500
radeon: fix LVDS power sequence on Mac cards
Noticed by John R. Dunning. Fix taken from radeonfb.
I'm not sure if this sequence would be useful on any PC
laptops or not so make it mac specific for now.
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 7134ee1..9123d58 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -912,6 +912,11 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
ErrorF("enable LVDS\n");
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+#if defined(__powerpc__)
+ /* not sure if this is needed on non-Macs */
+ if (info->MacModel)
+ tmp |= RADEON_LVDS_BL_MOD_EN;
+#endif
tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
usleep (lvds->PanelPwrDly * 1000);
OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
@@ -1001,10 +1006,24 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
*/
OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
}
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+#if defined(__powerpc__)
+ /* not sure if this is needed on non-Macs */
+ if (info->MacModel) {
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~RADEON_LVDS_BL_MOD_EN;
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ usleep(100);
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ } else
+#endif
+ {
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ }
save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
if (info->IsMobility || info->IsIGP) {
commit e8b9de06482ff792b8d7fa40ce3bc024caca62f6
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Jan 11 12:40:06 2010 -0500
rv100: reject modes >135 Mhz with DVI
Due to heat issues. fixes bug 25992
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 6b6ba70..4ff34b4 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -439,6 +439,10 @@ radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
/* single link DVI check */
if (pMode->Clock > 165000 && radeon_output->MonType == MT_DFP) {
+ /* clocks over 135 MHz have heat issues with DVI on RV100 */
+ if ((info->ChipFamily == CHIP_FAMILY_RV100) && (pMode->Clock > 135000))
+ return MODE_CLOCK_HIGH;
+
/* DP->DVI converter */
if (radeon_output->ConnectorType == CONNECTOR_DISPLAY_PORT)
return MODE_CLOCK_HIGH;
commit 587f693886e9025ba6fc30a8405902c43b2fcfb2
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Dec 22 08:45:27 2009 -0500
radeon: add cvt timing if we only have panel w/h
fixes mac laptops without an edid
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
diff --git a/src/radeon_modes.c b/src/radeon_modes.c
index ec60cc9..ce55c9f 100644
--- a/src/radeon_modes.c
+++ b/src/radeon_modes.c
@@ -169,6 +169,20 @@ static DisplayModePtr RADEONFPNativeMode(xf86OutputPtr output)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added native panel mode: %dx%d\n",
native_mode->PanelXRes, native_mode->PanelYRes);
+ } else if (native_mode->PanelXRes != 0 &&
+ native_mode->PanelYRes != 0) {
+
+ new = xf86CVTMode(native_mode->PanelXRes, native_mode->PanelYRes, 60.0, TRUE, FALSE);
+
+ if (new) {
+ new->type = M_T_DRIVER | M_T_PREFERRED;
+
+ new->next = NULL;
+ new->prev = NULL;
+ }
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Added native panel mode using CVT: %dx%d\n",
+ native_mode->PanelXRes, native_mode->PanelYRes);
}
return new;
commit e7b26abc3c20fb53bf2cd02404ac5e0654fee18d
Author: Matthias Hopf <mhopf@suse.de>
Date: Tue Dec 15 10:53:48 2009 -0500
fix 200M freezes on VT switch if CRTC is disabled
It appears that RS4xx chips need to have the crtc
enabled when the timing is programmed.
agd5f: minor fixes/cleanup of the original patch
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index aee3d15..ba3b102 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -912,6 +912,11 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save,
? RADEON_CRTC_INTERLACE_EN
: 0));
+ /* 200M freezes on VT switch sometimes if CRTC is disabled */
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480))
+ save->crtc_gen_cntl |= RADEON_CRTC_EN;
+
save->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN|
RADEON_CRTC_VSYNC_DIS |
RADEON_CRTC_HSYNC_DIS |
@@ -1162,6 +1167,11 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
? RADEON_CRTC2_INTERLACE_EN
: 0));
+ /* 200M freezes on VT switch sometimes if CRTC is disabled */
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480))
+ save->crtc2_gen_cntl |= RADEON_CRTC2_EN;
+
save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl;
save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
commit 45edca0e9d7b833b9de3037e94f293122c922e42
Author: Michel Dänzer <daenzer@vmware.com>
Date: Thu Sep 3 14:55:05 2009 +0200
EXA: Check for solid/gradient pictures the same way for all generations.
In particular, also catch them for >= R300.
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 9aeb862..54d91e8 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1313,6 +1313,9 @@ static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskP
if (op >= (int) (sizeof(R600BlendOp) / sizeof(R600BlendOp[0])))
RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
+ if (!pSrcPicture->pDrawable)
+ RADEON_FALLBACK(("Solid or gradient pictures not supported yet\n"));
+
pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
max_tex_w = 8192;
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 660ec43..e663b54 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -478,7 +478,7 @@ static Bool R100CheckComposite(int op, PicturePtr pSrcPicture,
RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
if (!pSrcPicture->pDrawable)
Reply to: