Bug#498632: Bug in reading Maximum Pixel Clock rate from DVI EDID
I have a thread at
http://www.nvnews.net/vbulletin/showthread.php?p=2162379&posted=1#post2162379
describing this problem for the closed source driver.
I can now summarize the problem very compactly:
1) The EDID block read from the SP2309W monitor is:
0000000 ff00 ffff ffff 00ff ac10 d01c 5253 3044
0000010 132c 0301 3380 781d 18ea a955 3753 25ad
0000020 5013 a554 004b 4f71 8081 00b3 0101 0101
0000030 0101 0101 0101 3d3b a000 8080 4021 2030
0000040 0035 22fe 0011 1a00 0000 ff00 5400 3439
0000050 4630 4139 3054 5244 0a53 0000 fd00 3800
0000060 1e55 115c 0a00 2020 2020 2020 0000 fc00
0000070 4400 4c45 204c 5053 3332 3930 0a57 db00
2) http://en.wikipedia.org/wiki/Extended_display_identification_data
tells me:
54–71: DESCRIPTOR BLOCK 1
54–55: Pixel Clock (in 10 kHz) or 0 (55 MSB 54 LSB)
Bytes 54-55 above are 3d3b, ie exactly 156.75MHz.
3) The native resolution for this monitor matches
"2048x1152"x0.0 156.75 2048 2096 2128 2208 1152 1155 1160 1185 +hsync -vsync (71.0 kHz)
Thus the monitor is giving the correct (Maximum) pixel rate.
4) However the nv driver shows in Xorg.0.log:-
(II) NV(0): EDID (in hex):
(II) NV(0): 00ffffffffffff0010ac1cd053524430
(II) NV(0): 2c13010380331d78ea1855a95337ad25
(II) NV(0): 135054a54b00714f8180b30001010101
(II) NV(0): 0101010101013b3d00a0808021403020 <== byte 54 = 3b, byte 55 = 3d
(II) NV(0): 3500fe221100001a000000ff00543934
(II) NV(0): 3046394154304452530a000000fd0038
(II) NV(0): 551e5c11000a202020202020000000fc
(II) NV(0): 0044454c4c20535032333039570a00db
(II) NV(0): Dell SP2309W: Using maximum pixel clock of 170.00 MHz
and later:-
(II) NV(0): Not using driver mode "2048x1152" (exceeds panel dimensions)
(II) NV(0): Not using driver mode "1680x1050" (exceeds panel dimensions)
(WW) NV(0): Shrinking virtual size estimate from 2048x1152 to 1280x1024
5) The closed source nvidia driver misreads the max pixel clock rate as 155MHz, but
as above, nv gets 170.0 MHz. Both are clearly wrong. And given that this is a
simple offset into the edid block, it surely can't a difficult problem to fix?
Clearly the nv driver has another issue with panel size.
As far as I can see, this part of the edid specification (as on Wikipedia) is
unambiguous so a fix ought to be simple?
ael
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