xserver-xorg-video-ati: Changes to 'upstream-experimental'
README | 20
configure.ac | 2
man/ati.man | 2
man/radeon.man | 2
src/ati_pciids_gen.h | 22
src/atombios_crtc.c | 82 -
src/atombios_output.c | 1250 ++++++++++++++--------
src/legacy_crtc.c | 8
src/legacy_output.c | 880 +++++++++------
src/pcidb/ati_pciids.csv | 22
src/radeon.h | 32
src/radeon_accel.c | 1
src/radeon_atombios.c | 640 +++++++----
src/radeon_atombios.h | 12
src/radeon_bios.c | 409 ++++---
src/radeon_chipinfo_gen.h | 22
src/radeon_chipset_gen.h | 22
src/radeon_dri.c | 10
src/radeon_driver.c | 60 -
src/radeon_exa_funcs.c | 114 --
src/radeon_exa_render.c | 119 +-
src/radeon_modes.c | 189 ++-
src/radeon_output.c | 2134 +++++++++++++++++---------------------
src/radeon_pci_chipset_gen.h | 22
src/radeon_pci_device_match_gen.h | 22
src/radeon_probe.h | 188 +--
src/radeon_reg.h | 21
src/radeon_textured_videofuncs.c | 54
src/radeon_tv.c | 163 +-
src/radeon_video.c | 2
30 files changed, 3706 insertions(+), 2820 deletions(-)
New commits:
commit 610b8b65fd7aa97f9c03b2ff6ae607aa959eab0b
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Mon Feb 9 16:33:20 2009 -0500
Bump for rc release
diff --git a/configure.ac b/configure.ac
index 8a6000a..eeaecbf 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.10.0.99,
+ 6.10.99.0,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit 04859362ce64ed4ae48305a83c92059899c1db4b
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Sun Feb 8 20:13:06 2009 -0500
Add some missing r6xx/r7xx pci ids
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index a32151d..d532f16 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -345,9 +345,15 @@
#define PCI_CHIP_RV770_9456 0x9456
#define PCI_CHIP_RV770_945A 0x945A
#define PCI_CHIP_RV770_945B 0x945B
+#define PCI_CHIP_RV770_946A 0x946A
+#define PCI_CHIP_RV770_946B 0x946B
+#define PCI_CHIP_RV770_947A 0x947A
+#define PCI_CHIP_RV770_947B 0x947B
#define PCI_CHIP_RV730_9487 0x9487
+#define PCI_CHIP_RV730_9489 0x9489
#define PCI_CHIP_RV730_948F 0x948F
#define PCI_CHIP_RV730_9490 0x9490
+#define PCI_CHIP_RV730_9491 0x9491
#define PCI_CHIP_RV730_9498 0x9498
#define PCI_CHIP_RV730_949C 0x949C
#define PCI_CHIP_RV730_949E 0x949E
@@ -363,19 +369,27 @@
#define PCI_CHIP_RV610_94C9 0x94C9
#define PCI_CHIP_RV610_94CB 0x94CB
#define PCI_CHIP_RV610_94CC 0x94CC
+#define PCI_CHIP_RV610_94CD 0x94CD
#define PCI_CHIP_RV670_9500 0x9500
#define PCI_CHIP_RV670_9501 0x9501
+#define PCI_CHIP_RV670_9504 0x9504
#define PCI_CHIP_RV670_9505 0x9505
+#define PCI_CHIP_RV670_9506 0x9506
#define PCI_CHIP_RV670_9507 0x9507
+#define PCI_CHIP_RV670_9508 0x9508
+#define PCI_CHIP_RV670_9509 0x9509
#define PCI_CHIP_RV670_950F 0x950F
#define PCI_CHIP_RV670_9511 0x9511
#define PCI_CHIP_RV670_9515 0x9515
+#define PCI_CHIP_RV670_9517 0x9517
+#define PCI_CHIP_RV670_9519 0x9519
#define PCI_CHIP_RV710_9540 0x9540
#define PCI_CHIP_RV710_9541 0x9541
#define PCI_CHIP_RV710_954E 0x954E
#define PCI_CHIP_RV710_954F 0x954F
#define PCI_CHIP_RV710_9552 0x9552
#define PCI_CHIP_RV710_9553 0x9553
+#define PCI_CHIP_RV710_9555 0x9555
#define PCI_CHIP_RV630_9580 0x9580
#define PCI_CHIP_RV630_9581 0x9581
#define PCI_CHIP_RV630_9583 0x9583
@@ -388,12 +402,16 @@
#define PCI_CHIP_RV630_958C 0x958C
#define PCI_CHIP_RV630_958D 0x958D
#define PCI_CHIP_RV630_958E 0x958E
+#define PCI_CHIP_RV630_958F 0x958F
#define PCI_CHIP_RV710_9542 0x9542
#define PCI_CHIP_RV620_95C0 0x95C0
#define PCI_CHIP_RV620_95C2 0x95C2
#define PCI_CHIP_RV620_95C4 0x95C4
#define PCI_CHIP_RV620_95C5 0x95C5
+#define PCI_CHIP_RV620_95C6 0x95C6
#define PCI_CHIP_RV620_95C7 0x95C7
+#define PCI_CHIP_RV620_95C9 0x95C9
+#define PCI_CHIP_RV620_95CC 0x95CC
#define PCI_CHIP_RV620_95CD 0x95CD
#define PCI_CHIP_RV620_95CE 0x95CE
#define PCI_CHIP_RV620_95CF 0x95CF
@@ -404,6 +422,8 @@
#define PCI_CHIP_RV635_9599 0x9599
#define PCI_CHIP_RV635_9591 0x9591
#define PCI_CHIP_RV635_9593 0x9593
+#define PCI_CHIP_RV635_9595 0x9595
+#define PCI_CHIP_RV635_959B 0x959B
#define PCI_CHIP_RS780_9610 0x9610
#define PCI_CHIP_RS780_9611 0x9611
#define PCI_CHIP_RS780_9612 0x9612
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 57c8ecd..4d4e625 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -346,9 +346,15 @@
"0x9456","RV770_9456","RV770",,,,,,"ATI FirePro V8700 (FireGL)"
"0x945A","RV770_945A","RV770",1,,,,,"ATI Mobility RADEON HD 4870"
"0x945B","RV770_945B","RV770",1,,,,,"ATI Mobility RADEON M98"
+"0x946A","RV770_946A","RV770",1,,,,,"ATI FirePro M7750"
+"0x946B","RV770_946B","RV770",1,,,,,"ATI M98"
+"0x947A","RV770_947A","RV770",1,,,,,"ATI M98"
+"0x947B","RV770_947B","RV770",1,,,,,"ATI M98"
"0x9487","RV730_9487","RV730",,,,,,"ATI Radeon RV730 (AGP)"
+"0x9489","RV730_9489","RV730",1,,,,,"ATI FirePro M5750"
"0x948F","RV730_948F","RV730",,,,,,"ATI Radeon RV730 (AGP)"
"0x9490","RV730_9490","RV730",,,,,,"ATI RV730XT [Radeon HD 4670]"
+"0x9491","RV730_9491","RV730",,,,,,"ATI RADEON E4600"
"0x9498","RV730_9498","RV730",,,,,,"ATI RV730 PRO [Radeon HD 4650]"
"0x949C","RV730_949C","RV730",,,,,,"ATI FirePro V7750 (FireGL)"
"0x949E","RV730_949E","RV730",,,,,,"ATI FirePro V5700 (FireGL)"
@@ -364,19 +370,27 @@
"0x94C9","RV610_94C9","RV610",1,,,,,"ATI Mobility Radeon HD 2400"
"0x94CB","RV610_94CB","RV610",1,,,,,"ATI RADEON E2400"
"0x94CC","RV610_94CC","RV610",,,,,,"ATI RV610"
+"0x94CD","RV610_94CD","RV610",,,,,,"ATI FireMV 2260"
"0x9500","RV670_9500","RV670",,,,,,"ATI RV670"
"0x9501","RV670_9501","RV670",,,,,,"ATI Radeon HD3870"
+"0x9504","RV670_9504","RV670",1,,,,,"ATI Mobility Radeon HD 3850"
"0x9505","RV670_9505","RV670",,,,,,"ATI Radeon HD3850"
+"0x9506","RV670_9506","RV670",1,,,,,"ATI Mobility Radeon HD 3850 X2"
"0x9507","RV670_9507","RV670",,,,,,"ATI RV670"
+"0x9508","RV670_9508","RV670",1,,,,,"ATI Mobility Radeon HD 3870"
+"0x9509","RV670_9509","RV670",1,,,,,"ATI Mobility Radeon HD 3870 X2"
"0x950F","RV670_950F","RV670",,,,,,"ATI Radeon HD3870 X2"
"0x9511","RV670_9511","RV670",,,,,,"ATI FireGL V7700"
"0x9515","RV670_9515","RV670",,,,,,"ATI Radeon HD3850"
+"0x9517","RV670_9517","RV670",,,,,,"ATI Radeon HD3690"
+"0x9519","RV670_9519","RV670",,,,,,"AMD Firestream 9170"
"0x9540","RV710_9540","RV710",,,,,,"ATI Radeon HD 4550"
"0x9541","RV710_9541","RV710",,,,,,"ATI Radeon RV710"
"0x954E","RV710_954E","RV710",,,,,,"ATI Radeon RV710"
"0x954F","RV710_954F","RV710",,,,,,"ATI Radeon HD 4350"
"0x9552","RV710_9552","RV710",1,,,,,"ATI Mobility Radeon 4300 Series"
"0x9553","RV710_9553","RV710",1,,,,,"ATI Mobility Radeon 4500 Series"
+"0x9555","RV710_9555","RV710",1,,,,,"ATI Mobility Radeon 4500 Series"
"0x9580","RV630_9580","RV630",,,,,,"ATI RV630"
"0x9581","RV630_9581","RV630",1,,,,,"ATI Mobility Radeon HD 2600"
"0x9583","RV630_9583","RV630",1,,,,,"ATI Mobility Radeon HD 2600 XT"
@@ -389,12 +403,16 @@
"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600"
"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600"
"0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE"
+"0x958F","RV630_958F","RV630",1,,,,,"ATI Mobility FireGL Graphics Processor"
"0x9542","RV710_9542","RV710",,,,,,"ATI Radeon RV710"
"0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470"
"0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430"
"0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series"
"0x95C5","RV620_95C5","RV620",,,,,,"ATI Radeon HD 3450"
+"0x95C6","RV620_95C6","RV620",,,,,,"ATI Radeon HD 3450"
"0x95C7","RV620_95C7","RV620",,,,,,"ATI Radeon HD 3430"
+"0x95C9","RV620_95C9","RV620",,,,,,"ATI Radeon HD 3450"
+"0x95CC","RV620_95CC","RV620",,,,,,"ATI FirePro V3700"
"0x95CD","RV620_95CD","RV620",,,,,,"ATI FireMV 2450"
"0x95CE","RV620_95CE","RV620",,,,,,"ATI FireMV 2260"
"0x95CF","RV620_95CF","RV620",,,,,,"ATI FireMV 2260"
@@ -405,6 +423,8 @@
"0x9599","RV635_9599","RV635",,,,,,"ATI Radeon HD 3600 PRO"
"0x9591","RV635_9591","RV635",1,,,,,"ATI Mobility Radeon HD 3650"
"0x9593","RV635_9593","RV635",1,,,,,"ATI Mobility Radeon HD 3670"
+"0x9595","RV635_9595","RV635",1,,,,,"ATI Mobility FireGL V5700"
+"0x959B","RV635_959B","RV635",1,,,,,"ATI Mobility FireGL V5725"
"0x9610","RS780_9610","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
"0x9611","RS780_9611","RS780",,1,,,1,"ATI Radeon 3100 Graphics"
"0x9612","RS780_9612","RS780",,1,,,1,"ATI Radeon HD 3200 Graphics"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index ef29957..eb2df17 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -265,9 +265,15 @@ RADEONCardInfo RADEONCards[] = {
{ 0x9456, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 },
{ 0x945A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
{ 0x945B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x946A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x946B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x947A, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
+ { 0x947B, CHIP_FAMILY_RV770, 1, 0, 0, 0, 0 },
{ 0x9487, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
+ { 0x9489, CHIP_FAMILY_RV730, 1, 0, 0, 0, 0 },
{ 0x948F, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x9490, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
+ { 0x9491, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x9498, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x949C, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
{ 0x949E, CHIP_FAMILY_RV730, 0, 0, 0, 0, 0 },
@@ -283,19 +289,27 @@ RADEONCardInfo RADEONCards[] = {
{ 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
{ 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 },
{ 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
+ { 0x94CD, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 },
{ 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9504, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
{ 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9506, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
{ 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9508, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
+ { 0x9509, CHIP_FAMILY_RV670, 1, 0, 0, 0, 0 },
{ 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9517, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
+ { 0x9519, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 },
{ 0x9540, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x9541, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x954E, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x954F, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x9552, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
{ 0x9553, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
+ { 0x9555, CHIP_FAMILY_RV710, 1, 0, 0, 0, 0 },
{ 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
{ 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
@@ -308,12 +322,16 @@ RADEONCardInfo RADEONCards[] = {
{ 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
+ { 0x958F, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 },
{ 0x9542, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
{ 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
{ 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
+ { 0x95C6, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
+ { 0x95C9, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
+ { 0x95CC, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
@@ -324,6 +342,8 @@ RADEONCardInfo RADEONCards[] = {
{ 0x9599, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 },
{ 0x9591, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
{ 0x9593, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
+ { 0x9595, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
+ { 0x959B, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 },
{ 0x9610, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
{ 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 59c424e..3c86ae6 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -265,9 +265,15 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV770_9456, "ATI FirePro V8700 (FireGL)" },
{ PCI_CHIP_RV770_945A, "ATI Mobility RADEON HD 4870" },
{ PCI_CHIP_RV770_945B, "ATI Mobility RADEON M98" },
+ { PCI_CHIP_RV770_946A, "ATI FirePro M7750" },
+ { PCI_CHIP_RV770_946B, "ATI M98" },
+ { PCI_CHIP_RV770_947A, "ATI M98" },
+ { PCI_CHIP_RV770_947B, "ATI M98" },
{ PCI_CHIP_RV730_9487, "ATI Radeon RV730 (AGP)" },
+ { PCI_CHIP_RV730_9489, "ATI FirePro M5750" },
{ PCI_CHIP_RV730_948F, "ATI Radeon RV730 (AGP)" },
{ PCI_CHIP_RV730_9490, "ATI RV730XT [Radeon HD 4670]" },
+ { PCI_CHIP_RV730_9491, "ATI RADEON E4600" },
{ PCI_CHIP_RV730_9498, "ATI RV730 PRO [Radeon HD 4650]" },
{ PCI_CHIP_RV730_949C, "ATI FirePro V7750 (FireGL)" },
{ PCI_CHIP_RV730_949E, "ATI FirePro V5700 (FireGL)" },
@@ -283,19 +289,27 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" },
{ PCI_CHIP_RV610_94CB, "ATI RADEON E2400" },
{ PCI_CHIP_RV610_94CC, "ATI RV610" },
+ { PCI_CHIP_RV610_94CD, "ATI FireMV 2260" },
{ PCI_CHIP_RV670_9500, "ATI RV670" },
{ PCI_CHIP_RV670_9501, "ATI Radeon HD3870" },
+ { PCI_CHIP_RV670_9504, "ATI Mobility Radeon HD 3850" },
{ PCI_CHIP_RV670_9505, "ATI Radeon HD3850" },
+ { PCI_CHIP_RV670_9506, "ATI Mobility Radeon HD 3850 X2" },
{ PCI_CHIP_RV670_9507, "ATI RV670" },
+ { PCI_CHIP_RV670_9508, "ATI Mobility Radeon HD 3870" },
+ { PCI_CHIP_RV670_9509, "ATI Mobility Radeon HD 3870 X2" },
{ PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" },
{ PCI_CHIP_RV670_9511, "ATI FireGL V7700" },
{ PCI_CHIP_RV670_9515, "ATI Radeon HD3850" },
+ { PCI_CHIP_RV670_9517, "ATI Radeon HD3690" },
+ { PCI_CHIP_RV670_9519, "AMD Firestream 9170" },
{ PCI_CHIP_RV710_9540, "ATI Radeon HD 4550" },
{ PCI_CHIP_RV710_9541, "ATI Radeon RV710" },
{ PCI_CHIP_RV710_954E, "ATI Radeon RV710" },
{ PCI_CHIP_RV710_954F, "ATI Radeon HD 4350" },
{ PCI_CHIP_RV710_9552, "ATI Mobility Radeon 4300 Series" },
{ PCI_CHIP_RV710_9553, "ATI Mobility Radeon 4500 Series" },
+ { PCI_CHIP_RV710_9555, "ATI Mobility Radeon 4500 Series" },
{ PCI_CHIP_RV630_9580, "ATI RV630" },
{ PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" },
{ PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" },
@@ -308,12 +322,16 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV630_958C, "ATI FireGL V5600" },
{ PCI_CHIP_RV630_958D, "ATI FireGL V3600" },
{ PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" },
+ { PCI_CHIP_RV630_958F, "ATI Mobility FireGL Graphics Processor" },
{ PCI_CHIP_RV710_9542, "ATI Radeon RV710" },
{ PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" },
{ PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" },
{ PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" },
{ PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" },
+ { PCI_CHIP_RV620_95C6, "ATI Radeon HD 3450" },
{ PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" },
+ { PCI_CHIP_RV620_95C9, "ATI Radeon HD 3450" },
+ { PCI_CHIP_RV620_95CC, "ATI FirePro V3700" },
{ PCI_CHIP_RV620_95CD, "ATI FireMV 2450" },
{ PCI_CHIP_RV620_95CE, "ATI FireMV 2260" },
{ PCI_CHIP_RV620_95CF, "ATI FireMV 2260" },
@@ -324,6 +342,8 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV635_9599, "ATI Radeon HD 3600 PRO" },
{ PCI_CHIP_RV635_9591, "ATI Mobility Radeon HD 3650" },
{ PCI_CHIP_RV635_9593, "ATI Mobility Radeon HD 3670" },
+ { PCI_CHIP_RV635_9595, "ATI Mobility FireGL V5700" },
+ { PCI_CHIP_RV635_959B, "ATI Mobility FireGL V5725" },
{ PCI_CHIP_RS780_9610, "ATI Radeon HD 3200 Graphics" },
{ PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" },
{ PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" },
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 29e853f..31b032a 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -265,9 +265,15 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV770_9456, PCI_CHIP_RV770_9456, RES_SHARED_VGA },
{ PCI_CHIP_RV770_945A, PCI_CHIP_RV770_945A, RES_SHARED_VGA },
{ PCI_CHIP_RV770_945B, PCI_CHIP_RV770_945B, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_946A, PCI_CHIP_RV770_946A, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_946B, PCI_CHIP_RV770_946B, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_947A, PCI_CHIP_RV770_947A, RES_SHARED_VGA },
+ { PCI_CHIP_RV770_947B, PCI_CHIP_RV770_947B, RES_SHARED_VGA },
{ PCI_CHIP_RV730_9487, PCI_CHIP_RV730_9487, RES_SHARED_VGA },
+ { PCI_CHIP_RV730_9489, PCI_CHIP_RV730_9489, RES_SHARED_VGA },
{ PCI_CHIP_RV730_948F, PCI_CHIP_RV730_948F, RES_SHARED_VGA },
{ PCI_CHIP_RV730_9490, PCI_CHIP_RV730_9490, RES_SHARED_VGA },
+ { PCI_CHIP_RV730_9491, PCI_CHIP_RV730_9491, RES_SHARED_VGA },
{ PCI_CHIP_RV730_9498, PCI_CHIP_RV730_9498, RES_SHARED_VGA },
{ PCI_CHIP_RV730_949C, PCI_CHIP_RV730_949C, RES_SHARED_VGA },
{ PCI_CHIP_RV730_949E, PCI_CHIP_RV730_949E, RES_SHARED_VGA },
@@ -283,19 +289,27 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV610_94C9, PCI_CHIP_RV610_94C9, RES_SHARED_VGA },
{ PCI_CHIP_RV610_94CB, PCI_CHIP_RV610_94CB, RES_SHARED_VGA },
{ PCI_CHIP_RV610_94CC, PCI_CHIP_RV610_94CC, RES_SHARED_VGA },
+ { PCI_CHIP_RV610_94CD, PCI_CHIP_RV610_94CD, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9500, PCI_CHIP_RV670_9500, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9501, PCI_CHIP_RV670_9501, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9504, PCI_CHIP_RV670_9504, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9505, PCI_CHIP_RV670_9505, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9506, PCI_CHIP_RV670_9506, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9507, PCI_CHIP_RV670_9507, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9508, PCI_CHIP_RV670_9508, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9509, PCI_CHIP_RV670_9509, RES_SHARED_VGA },
{ PCI_CHIP_RV670_950F, PCI_CHIP_RV670_950F, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9511, PCI_CHIP_RV670_9511, RES_SHARED_VGA },
{ PCI_CHIP_RV670_9515, PCI_CHIP_RV670_9515, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9517, PCI_CHIP_RV670_9517, RES_SHARED_VGA },
+ { PCI_CHIP_RV670_9519, PCI_CHIP_RV670_9519, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9540, PCI_CHIP_RV710_9540, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9541, PCI_CHIP_RV710_9541, RES_SHARED_VGA },
{ PCI_CHIP_RV710_954E, PCI_CHIP_RV710_954E, RES_SHARED_VGA },
{ PCI_CHIP_RV710_954F, PCI_CHIP_RV710_954F, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9552, PCI_CHIP_RV710_9552, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9553, PCI_CHIP_RV710_9553, RES_SHARED_VGA },
+ { PCI_CHIP_RV710_9555, PCI_CHIP_RV710_9555, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9580, PCI_CHIP_RV630_9580, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9581, PCI_CHIP_RV630_9581, RES_SHARED_VGA },
{ PCI_CHIP_RV630_9583, PCI_CHIP_RV630_9583, RES_SHARED_VGA },
@@ -308,12 +322,16 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA },
{ PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA },
{ PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA },
+ { PCI_CHIP_RV630_958F, PCI_CHIP_RV630_958F, RES_SHARED_VGA },
{ PCI_CHIP_RV710_9542, PCI_CHIP_RV710_9542, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C5, PCI_CHIP_RV620_95C5, RES_SHARED_VGA },
+ { PCI_CHIP_RV620_95C6, PCI_CHIP_RV620_95C6, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C7, PCI_CHIP_RV620_95C7, RES_SHARED_VGA },
+ { PCI_CHIP_RV620_95C9, PCI_CHIP_RV620_95C9, RES_SHARED_VGA },
+ { PCI_CHIP_RV620_95CC, PCI_CHIP_RV620_95CC, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95CD, PCI_CHIP_RV620_95CD, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95CE, PCI_CHIP_RV620_95CE, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95CF, PCI_CHIP_RV620_95CF, RES_SHARED_VGA },
@@ -324,6 +342,8 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV635_9599, PCI_CHIP_RV635_9599, RES_SHARED_VGA },
{ PCI_CHIP_RV635_9591, PCI_CHIP_RV635_9591, RES_SHARED_VGA },
{ PCI_CHIP_RV635_9593, PCI_CHIP_RV635_9593, RES_SHARED_VGA },
+ { PCI_CHIP_RV635_9595, PCI_CHIP_RV635_9595, RES_SHARED_VGA },
+ { PCI_CHIP_RV635_959B, PCI_CHIP_RV635_959B, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9610, PCI_CHIP_RS780_9610, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9611, PCI_CHIP_RS780_9611, RES_SHARED_VGA },
{ PCI_CHIP_RS780_9612, PCI_CHIP_RS780_9612, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index c0c4f79..b310ce8 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -265,9 +265,15 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV770_9456, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV770_945A, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV770_945B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_946A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_946B, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_947A, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV770_947B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9487, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV730_9489, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_948F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9490, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV730_9491, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_9498, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_949C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV730_949E, 0 ),
@@ -283,19 +289,27 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94C9, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CB, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CC, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV610_94CD, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9500, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9501, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9504, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9505, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9506, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9507, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9508, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9509, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_950F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9511, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV670_9515, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9517, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV670_9519, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9540, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9541, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_954E, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_954F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9552, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9553, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9555, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9580, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9581, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_9583, 0 ),
@@ -308,12 +322,16 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV630_958F, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV710_9542, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C5, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C6, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C7, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CC, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CD, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CE, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95CF, 0 ),
@@ -324,6 +342,8 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9599, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9591, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV635_9593, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_9595, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV635_959B, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9610, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9611, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RS780_9612, 0 ),
commit bba5d806cc46328ad9e4c521bfeeb2a59f96862b
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Fri Feb 6 19:44:17 2009 -0500
AVIVO: better fix for rotation
This should handle initial rotation as well.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index e86f186..e79ba13 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -455,6 +455,23 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
x = 0;
y = 0;
fb_location = fb_location + (char *)crtc->rotatedData - (char *)info->FB;
+ switch (crtc->rotation) {
+ case RR_Rotate_0:
+ case RR_Rotate_180:
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY);
+ default:
+ break;
+ case RR_Rotate_90:
+ case RR_Rotate_270:
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualY);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualX);
+ break;
+
+ }
+ } else {
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY);
}
OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
@@ -465,11 +482,6 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
- if (crtc->rotatedData == NULL) {
- /* rotation changes the virtualX and virtualY */
- OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX);
- OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY);
- }
OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
commit 28cf3492f431f325cb08d7c6aade43d8886df3f6
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Fri Feb 6 19:20:18 2009 -0500
AVIVO: fix rotation
When rotation is active, virtualX and virtualY change.
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 3299740..e86f186 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -465,8 +465,11 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
OUTREG(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
- OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX);
- OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY);
+ if (crtc->rotatedData == NULL) {
+ /* rotation changes the virtualX and virtualY */
+ OUTREG(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, pScrn->virtualX);
+ OUTREG(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, pScrn->virtualY);
+ }
OUTREG(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
crtc->scrn->displayWidth);
OUTREG(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
commit 16e01a5796a8e8b86ad25d3aa45b9e7044dc72d1
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Feb 3 19:46:10 2009 -0500
Fix encoder accounting
Should fix bug 19924
diff --git a/src/atombios_output.c b/src/atombios_output.c
index 0827d74..653d207 100644
--- a/src/atombios_output.c
+++ b/src/atombios_output.c
@@ -1194,6 +1194,7 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
switch (mode) {
case DPMSModeOn:
+ radeon_encoder->devices |= radeon_output->active_device;
if (is_dig)
(void)atombios_dig_dpms(output, mode);
else {
@@ -1209,12 +1210,12 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
ErrorF("Output %s enable failed\n",
device_name[radeon_get_device_index(radeon_output->active_device)]);
}
- radeon_encoder->use_count++;
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
- if (radeon_encoder->use_count < 2) {
+ radeon_encoder->devices &= ~(radeon_output->active_device);
+ if (!radeon_encoder->devices) {
if (is_dig)
(void)atombios_dig_dpms(output, mode);
else {
@@ -1232,8 +1233,6 @@ atombios_output_dpms(xf86OutputPtr output, int mode)
device_name[radeon_get_device_index(radeon_output->active_device)]);
}
}
- if (radeon_encoder->use_count > 0)
- radeon_encoder->use_count--;
break;
}
}
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 82291e5..6223531 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -903,6 +903,7 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
switch(mode) {
case DPMSModeOn:
+ radeon_encoder->devices |= radeon_output->active_device;
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_LVDS:
{
@@ -984,35 +985,35 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
RADEONDacPowerSet(pScrn, TRUE, FALSE);
break;
}
- radeon_encoder->use_count++;
break;
case DPMSModeOff:
case DPMSModeSuspend:
case DPMSModeStandby:
- switch (radeon_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_LVDS:
- if (radeon_encoder->use_count < 2) {
- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- ErrorF("disable LVDS\n");
- if (info->IsMobility || info->IsIGP) {
- /* Asic bug, when turning off LVDS_ON, we have to make sure
- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
- */
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
- }
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- if (info->IsMobility || info->IsIGP) {
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ radeon_encoder->devices &= ~(radeon_output->active_device);
+ if (!radeon_encoder->devices) {
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+ {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ ErrorF("disable LVDS\n");
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
}
- }
- break;
- case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
- if (radeon_encoder->use_count < 2) {
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
ErrorF("disable FP1\n");
tmp = INREG(RADEON_FP_GEN_CNTL);
tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
@@ -1026,10 +1027,8 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
save->fp_2nd_gen_cntl &= ~(RS400_FP_2ND_ON |
RS400_TMDS_2ND_EN);
}
- }
break;
- case ENCODER_OBJECT_ID_INTERNAL_DVO1:
- if (radeon_encoder->use_count < 2) {
+ case ENCODER_OBJECT_ID_INTERNAL_DVO1:
ErrorF("disable FP2\n");
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp |= RADEON_FP2_BLANK_EN;
@@ -1046,20 +1045,16 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
save->fp2_2_gen_cntl &= ~(RS400_FP2_2_ON | RS400_FP2_2_DVO2_EN);
save->fp2_2_gen_cntl |= RS400_FP2_2_BLANK_EN;
}
- }
- break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC1:
- if (radeon_encoder->use_count < 2) {
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC1:
ErrorF("disable primary dac\n");
tmp = INREG(RADEON_CRTC_EXT_CNTL);
tmp &= ~RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
RADEONDacPowerSet(pScrn, FALSE, TRUE);
- }
- break;
- case ENCODER_OBJECT_ID_INTERNAL_DAC2:
- if (radeon_encoder->use_count < 2) {
+ break;
+ case ENCODER_OBJECT_ID_INTERNAL_DAC2:
if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
ErrorF("disable TV\n");
tmp = INREG(RADEON_TV_MASTER_CNTL);
@@ -1081,11 +1076,9 @@ legacy_output_dpms(xf86OutputPtr output, int mode)
}
}
RADEONDacPowerSet(pScrn, FALSE, FALSE);
+ break;
}
- break;
}
- if (radeon_encoder->use_count > 0)
- radeon_encoder->use_count--;
break;
}
}
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 61eb62b..87e89ba 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1644,7 +1644,7 @@ radeon_add_encoder(ScrnInfoPtr pScrn, uint32_t encoder_id, uint32_t device_suppo
info->encoders[device_index] = (radeon_encoder_ptr)xcalloc(1,sizeof(radeon_encoder_rec));
if (info->encoders[device_index] != NULL) {
info->encoders[device_index]->encoder_id = encoder_id;
- info->encoders[device_index]->use_count = 0;
+ info->encoders[device_index]->devices = 0;
info->encoders[device_index]->dev_priv = NULL;
// add dev_priv stuff
switch (encoder_id) {
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index a1b261f..1b6ed7b 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -161,7 +161,7 @@ typedef struct _RADEONCrtcPrivateRec {
typedef struct _radeon_encoder {
uint16_t encoder_id;
- int use_count;
+ int devices;
void *dev_priv;
} radeon_encoder_rec, *radeon_encoder_ptr;
commit 9abb09d5f43320bd27b336612d39d264fe93549f
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Tue Feb 3 11:17:13 2009 -0500
Fix bad rv710 pci id
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 6f23628..a32151d 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -388,7 +388,7 @@
#define PCI_CHIP_RV630_958C 0x958C
#define PCI_CHIP_RV630_958D 0x958D
#define PCI_CHIP_RV630_958E 0x958E
-#define PCI_CHIP_RV710_9592 0x9592
+#define PCI_CHIP_RV710_9542 0x9542
#define PCI_CHIP_RV620_95C0 0x95C0
#define PCI_CHIP_RV620_95C2 0x95C2
#define PCI_CHIP_RV620_95C4 0x95C4
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index aea0931..57c8ecd 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -389,7 +389,7 @@
"0x958C","RV630_958C","RV630",,,,,,"ATI FireGL V5600"
"0x958D","RV630_958D","RV630",,,,,,"ATI FireGL V3600"
"0x958E","RV630_958E","RV630",,,,,,"ATI Radeon HD 2600 LE"
-"0x9592","RV710_9592","RV710",,,,,,"ATI Radeon RV710"
+"0x9542","RV710_9542","RV710",,,,,,"ATI Radeon RV710"
"0x95C0","RV620_95C0","RV620",,,,,,"ATI Radeon HD 3470"
"0x95C2","RV620_95C2","RV620",1,,,,,"ATI Mobility Radeon HD 3430"
"0x95C4","RV620_95C4","RV620",1,,,,,"ATI Mobility Radeon HD 3400 Series"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 627520b..ef29957 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -308,7 +308,7 @@ RADEONCardInfo RADEONCards[] = {
{ 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
{ 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 },
- { 0x9592, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
+ { 0x9542, CHIP_FAMILY_RV710, 0, 0, 0, 0, 0 },
{ 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 },
{ 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
{ 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index b8a8a65..59c424e 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -308,7 +308,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RV630_958C, "ATI FireGL V5600" },
{ PCI_CHIP_RV630_958D, "ATI FireGL V3600" },
{ PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" },
- { PCI_CHIP_RV710_9592, "ATI Radeon RV710" },
+ { PCI_CHIP_RV710_9542, "ATI Radeon RV710" },
{ PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" },
{ PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" },
{ PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" },
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index 525eafa..29e853f 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -308,7 +308,7 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_RV630_958C, PCI_CHIP_RV630_958C, RES_SHARED_VGA },
{ PCI_CHIP_RV630_958D, PCI_CHIP_RV630_958D, RES_SHARED_VGA },
{ PCI_CHIP_RV630_958E, PCI_CHIP_RV630_958E, RES_SHARED_VGA },
- { PCI_CHIP_RV710_9592, PCI_CHIP_RV710_9592, RES_SHARED_VGA },
+ { PCI_CHIP_RV710_9542, PCI_CHIP_RV710_9542, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C0, PCI_CHIP_RV620_95C0, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C2, PCI_CHIP_RV620_95C2, RES_SHARED_VGA },
{ PCI_CHIP_RV620_95C4, PCI_CHIP_RV620_95C4, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h b/src/radeon_pci_device_match_gen.h
index 878fe56..c0c4f79 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -308,7 +308,7 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958C, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV630_958E, 0 ),
- ATI_DEVICE_MATCH( PCI_CHIP_RV710_9592, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_RV710_9542, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C0, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C2, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_RV620_95C4, 0 ),
commit c88c3ef6f3db266c1aacba5297b8dfc8b66bf00e
Author: Wolke Liu <wolke.liu@amd.com>
Date: Mon Feb 2 17:01:34 2009 -0500
AVIVO: Save/restore vga pll registers
This fixes some VT switch issues on some chips
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index eda7b77..b0817b0 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4232,6 +4232,27 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL);
state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL);
+ state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC);
+ state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV);
+ state->vga25_ppll.fb_div = INREG(AVIVO_VGA25_PPLL_FB_DIV);
+ state->vga25_ppll.post_div_src = INREG(AVIVO_VGA25_PPLL_POST_DIV_SRC);
+ state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV);
+ state->vga25_ppll.pll_cntl = INREG(AVIVO_VGA25_PPLL_CNTL);
+
+ state->vga28_ppll.ref_div_src = INREG(AVIVO_VGA28_PPLL_REF_DIV_SRC);
+ state->vga28_ppll.ref_div = INREG(AVIVO_VGA28_PPLL_REF_DIV);
+ state->vga28_ppll.fb_div = INREG(AVIVO_VGA28_PPLL_FB_DIV);
+ state->vga28_ppll.post_div_src = INREG(AVIVO_VGA28_PPLL_POST_DIV_SRC);
+ state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV);
+ state->vga28_ppll.pll_cntl = INREG(AVIVO_VGA28_PPLL_CNTL);
+
+ state->vga41_ppll.ref_div_src = INREG(AVIVO_VGA41_PPLL_REF_DIV_SRC);
+ state->vga41_ppll.ref_div = INREG(AVIVO_VGA41_PPLL_REF_DIV);
+ state->vga41_ppll.fb_div = INREG(AVIVO_VGA41_PPLL_FB_DIV);
+ state->vga41_ppll.post_div_src = INREG(AVIVO_VGA41_PPLL_POST_DIV_SRC);
+ state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV);
+ state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL);
+
state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL);
state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL);
@@ -4602,6 +4623,28 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source);
OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
+ /* Set the vga PLL */
+ OUTREG(AVIVO_VGA25_PPLL_REF_DIV_SRC, state->vga25_ppll.ref_div_src);
+ OUTREG(AVIVO_VGA25_PPLL_REF_DIV, state->vga25_ppll.ref_div);
+ OUTREG(AVIVO_VGA25_PPLL_FB_DIV, state->vga25_ppll.fb_div);
+ OUTREG(AVIVO_VGA25_PPLL_POST_DIV_SRC, state->vga25_ppll.post_div_src);
+ OUTREG(AVIVO_VGA25_PPLL_POST_DIV, state->vga25_ppll.post_div);
+ OUTREG(AVIVO_VGA25_PPLL_CNTL, state->vga25_ppll.pll_cntl);
+
+ OUTREG(AVIVO_VGA28_PPLL_REF_DIV_SRC, state->vga28_ppll.ref_div_src);
+ OUTREG(AVIVO_VGA28_PPLL_REF_DIV, state->vga28_ppll.ref_div);
+ OUTREG(AVIVO_VGA28_PPLL_FB_DIV, state->vga28_ppll.fb_div);
+ OUTREG(AVIVO_VGA28_PPLL_POST_DIV_SRC, state->vga28_ppll.post_div_src);
+ OUTREG(AVIVO_VGA28_PPLL_POST_DIV, state->vga28_ppll.post_div);
+ OUTREG(AVIVO_VGA28_PPLL_CNTL, state->vga28_ppll.pll_cntl);
+
+ OUTREG(AVIVO_VGA41_PPLL_REF_DIV_SRC, state->vga41_ppll.ref_div_src);
+ OUTREG(AVIVO_VGA41_PPLL_REF_DIV, state->vga41_ppll.ref_div);
+ OUTREG(AVIVO_VGA41_PPLL_FB_DIV, state->vga41_ppll.fb_div);
+ OUTREG(AVIVO_VGA41_PPLL_POST_DIV_SRC, state->vga41_ppll.post_div_src);
+ OUTREG(AVIVO_VGA41_PPLL_POST_DIV, state->vga41_ppll.post_div);
+ OUTREG(AVIVO_VGA41_PPLL_CNTL, state->vga41_ppll.pll_cntl);
+
/* Set the CRTC */
OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total);
OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end);
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 28df696..a1b261f 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -341,6 +341,10 @@ struct avivo_state
struct avivo_pll_state pll1;
struct avivo_pll_state pll2;
+ struct avivo_pll_state vga25_ppll;
+ struct avivo_pll_state vga28_ppll;
+ struct avivo_pll_state vga41_ppll;
+
struct avivo_crtc_state crtc1;
struct avivo_crtc_state crtc2;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 1987d61..7b8840b 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3495,6 +3495,25 @@
# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
#define AVIVO_D2VGA_CONTROL 0x0338
+#define AVIVO_VGA25_PPLL_REF_DIV_SRC 0x0360
+#define AVIVO_VGA25_PPLL_REF_DIV 0x0364
+#define AVIVO_VGA28_PPLL_REF_DIV_SRC 0x0368
+#define AVIVO_VGA28_PPLL_REF_DIV 0x036c
+#define AVIVO_VGA41_PPLL_REF_DIV_SRC 0x0370
+#define AVIVO_VGA41_PPLL_REF_DIV 0x0374
+#define AVIVO_VGA25_PPLL_FB_DIV 0x0378
+#define AVIVO_VGA28_PPLL_FB_DIV 0x037c
+#define AVIVO_VGA41_PPLL_FB_DIV 0x0380
+#define AVIVO_VGA25_PPLL_POST_DIV_SRC 0x0384
+#define AVIVO_VGA25_PPLL_POST_DIV 0x0388
+#define AVIVO_VGA28_PPLL_POST_DIV_SRC 0x038c
+#define AVIVO_VGA28_PPLL_POST_DIV 0x0390
+#define AVIVO_VGA41_PPLL_POST_DIV_SRC 0x0394
+#define AVIVO_VGA41_PPLL_POST_DIV 0x0398
+#define AVIVO_VGA25_PPLL_CNTL 0x039c
+#define AVIVO_VGA28_PPLL_CNTL 0x03a0
+#define AVIVO_VGA41_PPLL_CNTL 0x03a4
+
#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
#define AVIVO_EXT1_PPLL_REF_DIV 0x404
#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
commit 6fac3cefd1f46161c1e276ba40e72da2823aa9f6
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Sat Jan 31 14:21:02 2009 -0500
Return NULL for encoder if no active device is assigned
fixes bug 19855
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 9fe7ec7..61eb62b 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1593,8 +1593,10 @@ radeon_get_encoder(xf86OutputPtr output)
RADEONOutputPrivatePtr radeon_output = output->driver_private;
RADEONInfoPtr info = RADEONPTR(output->scrn);
- return info->encoders[radeon_get_device_index(radeon_output->active_device)];
-
+ if (radeon_output->active_device)
+ return info->encoders[radeon_get_device_index(radeon_output->active_device)];
+ else
+ return NULL;
}
Bool
commit db178c852d00e9b85513d750b5f8f7495f9e3360
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