xserver-xorg-video-intel: Changes to 'upstream-unstable'
Rebased ref, commits from common ancestor:
commit 5d50a949b3c5d0ad2bc4cf48ab25da1f707a4f6f
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jul 20 22:59:37 2009 -0700
Increment version number to 2.8.0 for release.
diff --git a/configure.ac b/configure.ac
index 077c1ff..f7cdf1f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 2.7.99.902,
+ 2.8.0,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
commit b12220bd81f3a0509a3746dac3258e53f3879b23
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jul 20 22:59:02 2009 -0700
NEWS: Add notes for 2.8.0 release
Many thanks to Gordon for his notes from http://intellinuxgraphics.org/2009Q2.html
diff --git a/NEWS b/NEWS
index ddc2f40..3a2b243 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,51 @@
+Release 2.8.0 (2009-07-20)
+==========================
+We are pleased to present this major release of the xf86-video-intel
+driver. This release is very similar to the 2.7.99.902 release
+candidate but includes a couple of additional bug fixes, (for bugs
+#22760 and @22483).
+
+Compared to the 2.7 releases this driver contains several new features
+and many bug fixes. The driver now depends on X server 1.6 or later,
+and eliminates several obsolete code paths, (XAA and EXA removed in
+favor of UXA, DRI1 support eliminated). The driver certainly will work
+best with an i915 module from a recent kernel (2.6.31) and with
+kernel-modesetting (KMS, specified by loading i915 with the option
+"modeset=1").
+
+New features in 2.8.0 compared to 2.7
+-------------------------------------
+* Remove XAA/EXA/DRI1 and NoAccel, and only support UXA/DRI2 now
+ (requiring xserver 1.6).
+
+* VLD support added into XvMC for Mpeg2, which decreases CPU usage
+ when playing video.
+
+Major fixes in 2.8.0 compared to 2.7
+------------------------------------
+* Fix broken front-buffer rendering
+ https://bugs.freedesktop.org/show_bug.cgi?id=19174
+
+* Fix disabling of XvMC disabled
+ https://bugs.freedesktop.org/show_bug.cgi?id=20790
+
+* Fix broken VT switch on some machines
+ https://bugs.freedesktop.org/show_bug.cgi?id=19578
+
+* Improve performance of trapezoid rendering for UXA
+ https://bugs.freedesktop.org/show_bug.cgi?id=21376
+
+* Vblank sync'd GL buffer swap (fixing video tearing under composite)
+ https://bugs.freedesktop.org/show_bug.cgi?id=20664
+
+* Fix G41 DRM support
+ https://bugs.freedesktop.org/show_bug.cgi?id=21095
+
+* Fix crash on some 8xx
+ https://bugs.freedesktop.org/show_bug.cgi?id=18974
+
+Various fixes for GPU hangs, and more...
+
Snapshot 2.7.99.902 (2009-07-13)
--------------------------------
This is the first release candidate in preparation for the upcoming
commit bb3007384298cb57625ec0b3868dff9b23568f3e
Author: Eric Anholt <eric@anholt.net>
Date: Thu Jul 16 12:56:07 2009 -0700
Really fix i915 render. Fail at commit --amend.
diff --git a/src/i830.h b/src/i830.h
index 54dddd8..21c98f5 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -482,8 +482,6 @@ typedef struct _I830Rec {
struct {
int op;
- PicturePtr pSrcPicture, pMaskPicture, pDstPicture;
- PixmapPtr pSrc, pMask, pDst;
uint32_t dst_format;
Bool is_nearest;
Bool needs_emit;
diff --git a/src/i915_render.c b/src/i915_render.c
index 2d11986..c81366a 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -322,6 +322,13 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
i830_get_pixmap_bo(pDst),
};
+ pI830->render_src_picture = pSrcPicture;
+ pI830->render_src = pSrc;
+ pI830->render_mask_picture = pMaskPicture;
+ pI830->render_mask = pMask;
+ pI830->render_dst_picture = pDstPicture;
+ pI830->render_dst = pDst;
+
i830_exa_check_pitch_3d(pSrc);
if (pMask)
i830_exa_check_pitch_3d(pMask);
@@ -351,12 +358,6 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
}
pI830->i915_render_state.op = op;
- pI830->i915_render_state.pSrcPicture = pSrcPicture;
- pI830->i915_render_state.pMaskPicture = pMaskPicture;
- pI830->i915_render_state.pDstPicture = pDstPicture;
- pI830->i915_render_state.pSrc = pSrc;
- pI830->i915_render_state.pMask = pMask;
- pI830->i915_render_state.pDst = pDst;
pI830->i915_render_state.needs_emit = TRUE;
return TRUE;
@@ -367,12 +368,12 @@ i915_emit_composite_setup(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int op = pI830->i915_render_state.op;
- PicturePtr pSrcPicture = pI830->i915_render_state.pSrcPicture;
- PicturePtr pMaskPicture = pI830->i915_render_state.pMaskPicture;
- PicturePtr pDstPicture = pI830->i915_render_state.pDstPicture;
- PixmapPtr pSrc = pI830->i915_render_state.pSrc;
- PixmapPtr pMask = pI830->i915_render_state.pMask;
- PixmapPtr pDst = pI830->i915_render_state.pDst;
+ PicturePtr pSrcPicture = pI830->render_src_picture;
+ PicturePtr pMaskPicture = pI830->render_mask_picture;
+ PicturePtr pDstPicture = pI830->render_dst_picture;
+ PixmapPtr pSrc = pI830->render_src;
+ PixmapPtr pMask = pI830->render_mask;
+ PixmapPtr pDst = pI830->render_dst;
uint32_t dst_format = pI830->i915_render_state.dst_format, dst_pitch;
uint32_t blendctl;
int out_reg = FS_OC;
commit 8dd7ccf37e2de6d80b556e6d18af244cefc1e417
Author: Eric Anholt <eric@anholt.net>
Date: Thu Jul 16 11:40:51 2009 -0700
Fix 915-class Render after the 8xx-class Render fix.
The two shared i830_composite.c, so giving i830 atomic batch support
triggered anger about starting i830's atomic area while in i915's atomic
area. Instead, split the emit-a-primitive stuff from the state emission.
diff --git a/src/i830.h b/src/i830.h
index ec57662..54dddd8 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -788,6 +788,9 @@ i830_transform_is_affine (PictTransformPtr t);
void i830_composite(PixmapPtr pDst, int srcX, int srcY,
int maskX, int maskY, int dstX, int dstY, int w, int h);
+void i830_emit_composite_primitive(PixmapPtr pDst, int srcX, int srcY,
+ int maskX, int maskY, int dstX, int dstY,
+ int w, int h);
void i830_done_composite(PixmapPtr pDst);
/* i915_render.c */
Bool i915_check_composite(int op, PicturePtr pSrc, PicturePtr pMask,
diff --git a/src/i830_render.c b/src/i830_render.c
index ecee6f2..c5196cc 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -581,14 +581,10 @@ i830_emit_composite_state(ScrnInfoPtr pScrn)
}
}
-/**
- * Do a single rectangle composite operation.
- *
- * This function is shared between i830 and i915 generation code.
- */
void
-i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
- int dstX, int dstY, int w, int h)
+i830_emit_composite_primitive(PixmapPtr pDst, int srcX, int srcY,
+ int maskX, int maskY,
+ int dstX, int dstY, int w, int h)
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
@@ -670,15 +666,6 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
num_floats = 3 * per_vertex;
- intel_batch_start_atomic(pScrn,
- 58 + /* invarient */
- 24 + /* setup */
- 20 + /* 2 * setup_texture */
- 6 + num_floats /* verts */);
-
- if (pI830->needs_render_state_emit)
- i830_emit_composite_state(pScrn);
-
BEGIN_BATCH(6 + num_floats);
OUT_BATCH(MI_NOOP);
@@ -740,6 +727,32 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
}
ADVANCE_BATCH();
+}
+
+
+/**
+ * Do a single rectangle composite operation.
+ *
+ * This function is shared between i830 and i915 generation code.
+ */
+void
+i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
+ int dstX, int dstY, int w, int h)
+{
+ ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ intel_batch_start_atomic(pScrn,
+ 58 + /* invarient */
+ 24 + /* setup */
+ 20 + /* 2 * setup_texture */
+ 6 + 30 /* verts */);
+
+ if (pI830->needs_render_state_emit)
+ i830_emit_composite_state(pScrn);
+
+ i830_emit_composite_primitive(pDst, srcX, srcY, maskX, maskY, dstX, dstY,
+ w, h);
intel_batch_end_atomic(pScrn);
diff --git a/src/i915_render.c b/src/i915_render.c
index ab04e9c..2d11986 100644
--- a/src/i915_render.c
+++ b/src/i915_render.c
@@ -556,7 +556,8 @@ i915_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
if (pI830->i915_render_state.needs_emit)
i915_emit_composite_setup(pScrn);
- i830_composite(pDst, srcX, srcY, maskX, maskY, dstX, dstY, w, h);
+ i830_emit_composite_primitive(pDst, srcX, srcY, maskX, maskY, dstX, dstY,
+ w, h);
intel_batch_end_atomic(pScrn);
}
commit a1e6abb5ca89d699144d10fdc4309b3b78f2f7a9
Author: Eric Anholt <eric@anholt.net>
Date: Wed Jul 15 14:15:10 2009 -0700
Use batch_start_atomic to fix batchbuffer wrapping problems with 8xx render.
Bug #22483.
diff --git a/src/i830.h b/src/i830.h
index f7ca687..ec57662 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -468,6 +468,14 @@ typedef struct _I830Rec {
/** Transform pointers for src/mask, or NULL if identity */
PictTransform *transform[2];
float coord_adjust;
+
+ /* i830 render accel state */
+ PixmapPtr render_src, render_mask, render_dst;
+ PicturePtr render_src_picture, render_mask_picture, render_dst_picture;
+ uint32_t render_dst_format;
+ Bool needs_render_state_emit;
+ uint32_t cblend, ablend, s8_blendctl;
+
/* i915 render accel state */
uint32_t mapstate[6];
uint32_t samplerstate[6];
@@ -790,6 +798,7 @@ Bool i915_prepare_composite(int op, PicturePtr pSrc, PicturePtr pMask,
void i915_composite(PixmapPtr pDst, int srcX, int srcY,
int maskX, int maskY, int dstX, int dstY, int w, int h);
void i915_batch_flush_notify(ScrnInfoPtr pScrn);
+void i830_batch_flush_notify(ScrnInfoPtr scrn);
/* i965_render.c */
unsigned int gen4_render_state_size(ScrnInfoPtr pScrn);
void gen4_render_state_init(ScrnInfoPtr pScrn);
diff --git a/src/i830_driver.c b/src/i830_driver.c
index dfc2bdf..33079fe 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2757,7 +2757,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
else if (IS_I9XX(pI830))
pI830->batch_flush_notify = i915_batch_flush_notify;
else
- pI830->batch_flush_notify = NULL;
+ pI830->batch_flush_notify = i830_batch_flush_notify;
miInitializeBackingStore(pScreen);
xf86SetBackingStore(pScreen);
diff --git a/src/i830_render.c b/src/i830_render.c
index b1d6f50..ecee6f2 100644
--- a/src/i830_render.c
+++ b/src/i830_render.c
@@ -255,7 +255,7 @@ i8xx_get_card_format(PicturePtr pPict)
FatalError("Unsupported format type %d\n", pPict->format);
}
-static Bool
+static void
i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
{
@@ -299,7 +299,7 @@ i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
break;
default:
filter = 0;
- I830FALLBACK("Bad filter 0x%x\n", pPict->filter);
+ FatalError("Bad filter 0x%x\n", pPict->filter);
}
filter |= (MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
@@ -344,10 +344,6 @@ i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
TEX_STREAM_MAP_IDX(unit));
ADVANCE_BATCH();
}
-
- i830_debug_sync(pScrn);
-
- return TRUE;
}
Bool
@@ -391,29 +387,27 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
{
ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
- uint32_t dst_format, dst_pitch;
Bool is_affine_src, is_affine_mask;
Bool is_nearest = FALSE;
+ pI830->render_src_picture = pSrcPicture;
+ pI830->render_src = pSrc;
+ pI830->render_mask_picture = pMaskPicture;
+ pI830->render_mask = pMask;
+ pI830->render_dst_picture = pDstPicture;
+ pI830->render_dst = pDst;
+
i830_exa_check_pitch_3d(pSrc);
if (pMask)
i830_exa_check_pitch_3d(pMask);
i830_exa_check_pitch_3d(pDst);
- IntelEmitInvarientState(pScrn);
- pI830->last_3d = LAST_3D_RENDER;
-
- if (!i830_get_dest_format(pDstPicture, &dst_format))
+ if (!i830_get_dest_format(pDstPicture, &pI830->render_dst_format))
return FALSE;
- dst_pitch = intel_get_pixmap_pitch(pDst);
- if (!i830_texture_setup(pSrcPicture, pSrc, 0))
- I830FALLBACK("fail to setup src texture\n");
if (pSrcPicture->filter == PictFilterNearest)
is_nearest = TRUE;
if (pMask != NULL) {
- if (!i830_texture_setup(pMaskPicture, pMask, 1))
- I830FALLBACK("fail to setup mask texture\n");
if (pMaskPicture->filter == PictFilterNearest)
is_nearest = TRUE;
} else {
@@ -434,45 +428,7 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
I830FALLBACK("non-affine transform unsupported on 8xx hardware\n");
{
- uint32_t cblend, ablend, blendctl, vf2;
-
- BEGIN_BATCH(30);
-
- /* color buffer */
- OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
- OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE |
- BUF_3D_PITCH(dst_pitch));
- OUT_RELOC_PIXMAP(pDst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(MI_NOOP);
-
- OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
- OUT_BATCH(dst_format);
-
- /* defaults */
- OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
- OUT_BATCH(0);
-
- OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
- OUT_BATCH(0);
- OUT_BATCH(0); /* ymin, xmin */
- OUT_BATCH(DRAW_YMAX(pDst->drawable.height - 1) |
- DRAW_XMAX(pDst->drawable.width - 1));
- OUT_BATCH(0); /* yorig, xorig */
-
- OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
- I1_LOAD_S(3) | 1);
- if (pMask)
- vf2 = 2 << 12; /* 2 texture coord sets */
- else
- vf2 = 1 << 12;
- OUT_BATCH(vf2); /* TEXCOORDFMT_2D */
- OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
+ uint32_t cblend, ablend, blendctl;
/* If component alpha is active in the mask and the blend operation
* uses the source alpha, then we know we don't need the source
@@ -541,36 +497,90 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
ablend |= TB0A_ARG2_SEL_ONE;
}
- OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
- LOAD_TEXTURE_BLEND_STAGE(0)|1);
- OUT_BATCH(cblend);
- OUT_BATCH(ablend);
- OUT_BATCH(0);
-
blendctl = i830_get_blend_cntl(op, pMaskPicture, pDstPicture->format);
- OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
- OUT_BATCH(MI_NOOP);
- OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
- OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | blendctl |
- S8_ENABLE_COLOR_BUFFER_WRITE);
-
- OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
- DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
- DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
- ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
- /* We have to explicitly say we don't want write disabled */
- OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
- DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
- DISABLE_DITHER | ENABLE_COLOR_WRITE |
- DISABLE_DEPTH_WRITE);
- ADVANCE_BATCH();
+
+ pI830->cblend = cblend;
+ pI830->ablend = ablend;
+ pI830->s8_blendctl = blendctl;
}
i830_debug_sync(pScrn);
+ pI830->needs_render_state_emit = TRUE;
+
return TRUE;
}
+static void
+i830_emit_composite_state(ScrnInfoPtr pScrn)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ uint32_t vf2;
+
+ pI830->needs_render_state_emit = FALSE;
+
+ IntelEmitInvarientState(pScrn);
+ pI830->last_3d = LAST_3D_RENDER;
+
+ BEGIN_BATCH(24);
+
+ OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
+ OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE |
+ BUF_3D_PITCH(intel_get_pixmap_pitch(pI830->render_dst)));
+ OUT_RELOC_PIXMAP(pI830->render_dst,
+ I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+ OUT_BATCH(MI_NOOP);
+
+ OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
+ OUT_BATCH(pI830->render_dst_format);
+
+ OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
+ OUT_BATCH(0);
+ OUT_BATCH(0); /* ymin, xmin */
+ OUT_BATCH(DRAW_YMAX(pI830->render_dst->drawable.height - 1) |
+ DRAW_XMAX(pI830->render_dst->drawable.width - 1));
+ OUT_BATCH(0); /* yorig, xorig */
+
+ OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
+ I1_LOAD_S(2) |
+ I1_LOAD_S(3) | 1);
+ if (pI830->render_mask)
+ vf2 = 2 << 12; /* 2 texture coord sets */
+ else
+ vf2 = 1 << 12;
+ OUT_BATCH(vf2); /* TEXCOORDFMT_2D */
+ OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
+
+ OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
+ OUT_BATCH(MI_NOOP);
+ OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
+ OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | pI830->s8_blendctl |
+ S8_ENABLE_COLOR_BUFFER_WRITE);
+
+ OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
+ LOAD_TEXTURE_BLEND_STAGE(0)|1);
+ OUT_BATCH(pI830->cblend);
+ OUT_BATCH(pI830->ablend);
+ OUT_BATCH(0);
+
+ OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
+ DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
+ DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
+ ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
+ /* We have to explicitly say we don't want write disabled */
+ OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
+ DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
+ DISABLE_DITHER | ENABLE_COLOR_WRITE |
+ DISABLE_DEPTH_WRITE);
+ ADVANCE_BATCH();
+
+ i830_texture_setup(pI830->render_src_picture, pI830->render_src, 0);
+ if (pI830->render_mask) {
+ i830_texture_setup(pI830->render_mask_picture,
+ pI830->render_mask, 1);
+ }
+}
+
/**
* Do a single rectangle composite operation.
*
@@ -582,7 +592,6 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
{
ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
- Bool has_mask;
Bool is_affine_src, is_affine_mask;
int per_vertex, num_floats;
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
@@ -590,12 +599,6 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
is_affine_src = i830_transform_is_affine (pI830->transform[0]);
is_affine_mask = i830_transform_is_affine (pI830->transform[1]);
- if (pI830->scale_units[1][0] == -1 || pI830->scale_units[1][1] == -1) {
- has_mask = FALSE;
- } else {
- has_mask = TRUE;
- }
-
per_vertex = 2; /* dest x/y */
if (is_affine_src)
{
@@ -630,7 +633,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
return;
per_vertex += 4; /* src x/y/z/w */
}
- if (has_mask) {
+ if (pI830->render_mask) {
if (is_affine_mask) {
if (!i830_get_transformed_coordinates(maskX, maskY,
pI830->transform[1],
@@ -666,6 +669,16 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
}
num_floats = 3 * per_vertex;
+
+ intel_batch_start_atomic(pScrn,
+ 58 + /* invarient */
+ 24 + /* setup */
+ 20 + /* 2 * setup_texture */
+ 6 + num_floats /* verts */);
+
+ if (pI830->needs_render_state_emit)
+ i830_emit_composite_state(pScrn);
+
BEGIN_BATCH(6 + num_floats);
OUT_BATCH(MI_NOOP);
@@ -683,7 +696,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[2]);
}
- if (has_mask) {
+ if (pI830->render_mask) {
OUT_BATCH_F(mask_x[2] / pI830->scale_units[1][0]);
OUT_BATCH_F(mask_y[2] / pI830->scale_units[1][1]);
if (!is_affine_mask) {
@@ -700,7 +713,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[1]);
}
- if (has_mask) {
+ if (pI830->render_mask) {
OUT_BATCH_F(mask_x[1] / pI830->scale_units[1][0]);
OUT_BATCH_F(mask_y[1] / pI830->scale_units[1][1]);
if (!is_affine_mask) {
@@ -717,7 +730,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_BATCH_F(0.0);
OUT_BATCH_F(src_w[0]);
}
- if (has_mask) {
+ if (pI830->render_mask) {
OUT_BATCH_F(mask_x[0] / pI830->scale_units[1][0]);
OUT_BATCH_F(mask_y[0] / pI830->scale_units[1][1]);
if (!is_affine_mask) {
@@ -727,4 +740,16 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
}
ADVANCE_BATCH();
+
+ intel_batch_end_atomic(pScrn);
+
+ i830_debug_sync(pScrn);
+}
+
+void
+i830_batch_flush_notify(ScrnInfoPtr scrn)
+{
+ I830Ptr i830 = I830PTR(scrn);
+
+ i830->needs_render_state_emit = TRUE;
}
commit e386e7b14b139f15205e14b173e8222bf38d9e18
Author: Keith Packard <keithp@keithp.com>
Date: Wed Jul 15 09:43:04 2009 -0700
Reset framebuffer offset when rebinding aperture (22760).
scrn->fbOffset may be changed when binding objects to the aperture during
server initialization or VT enter. This was accidentally removed when the
NoAlloc option was eliminated.
Signed-off-by: Keith Packard <keithp@keithp.com>
diff --git a/src/i830_memory.c b/src/i830_memory.c
index f2f3966..cc9d376 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1581,6 +1581,9 @@ i830_bind_all_memory(ScrnInfoPtr pScrn)
i830_update_cursor_offsets(pScrn);
i830_set_max_gtt_map_size(pScrn);
+ if (pI830->front_buffer)
+ pScrn->fbOffset = pI830->front_buffer->offset;
+
return TRUE;
}
commit b74bf3f9a65af9e72921d4e9028d9d4d023f8bc6
Author: Barry Scott <barry.scott@onelan.co.uk>
Date: Mon Jul 13 16:34:20 2009 -0700
Fix XV scan line calculation when rotated.
diff --git a/src/i830_video.c b/src/i830_video.c
index 4bba902..92b6324 100644
--- a/src/i830_video.c
+++ b/src/i830_video.c
@@ -2539,7 +2539,7 @@ I830PutImage(ScrnInfoPtr pScrn,
if (sync) {
BoxPtr box;
- int y1, y2;
+ pixman_box16_t box_in_crtc_coordinates;
int pipe = -1, event, load_scan_lines_pipe;
if (pixmap_is_scanout(pPixmap))
@@ -2555,16 +2555,17 @@ I830PutImage(ScrnInfoPtr pScrn,
}
box = REGION_EXTENTS(unused, clipBoxes);
- y1 = box->y1 - crtc->y;
- y2 = box->y2 - crtc->y;
+ box_in_crtc_coordinates = *box;
+ if (crtc->transform_in_use)
+ pixman_f_transform_bounds (&crtc->f_framebuffer_to_crtc, &box_in_crtc_coordinates);
BEGIN_BATCH(5);
/* The documentation says that the LOAD_SCAN_LINES command
* always comes in pairs. Don't ask me why. */
OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | load_scan_lines_pipe);
- OUT_BATCH((y1 << 16) | y2);
+ OUT_BATCH((box_in_crtc_coordinates.y1 << 16) | box_in_crtc_coordinates.y2);
OUT_BATCH(MI_LOAD_SCAN_LINES_INCL | load_scan_lines_pipe);
- OUT_BATCH((y1 << 16) | y2);
+ OUT_BATCH((box_in_crtc_coordinates.y1 << 16) | box_in_crtc_coordinates.y2);
OUT_BATCH(MI_WAIT_FOR_EVENT | event);
ADVANCE_BATCH();
}
commit 82905c7c0b871a97ec435a765c2ca407903ba595
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jul 13 05:29:49 2009 -0700
Increment version to 2.7.99.902
diff --git a/configure.ac b/configure.ac
index 486fed7..077c1ff 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 2.7.99.901,
+ 2.7.99.902,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
commit 925bc6cbd430a00928fac2ef58724dd37c3bc349
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jul 13 05:27:40 2009 -0700
RELEASING: Fix typo in instructions
diff --git a/RELEASING b/RELEASING
index 2196c8f..e32ecf6 100644
--- a/RELEASING
+++ b/RELEASING
@@ -37,7 +37,7 @@ The process for releasing a new tarball is as follows:
At the very least, add the release notes from the NEWS file.
- The message is generated as xf86-video-inte-<version>.announce
+ The message is generated as xf86-video-intel-<version>.announce
For snapshots and release candidates, mail to:
commit 67c0afc7b7446a7b98aa7c65043ddba4c7c72b82
Author: Carl Worth <cworth@cworth.org>
Date: Mon Jul 13 05:27:06 2009 -0700
NEWS: Add notes for 2.7.99.902
diff --git a/NEWS b/NEWS
index 294a78c..ddc2f40 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,10 @@
+Snapshot 2.7.99.902 (2009-07-13)
+--------------------------------
+This is the first release candidate in preparation for the upcoming
+2.8.0 release. Most major and critical bugs should be fixed, but some
+minor bugs may still be present. We will appreciate any feedback we
+can get from testing of this snapshot to improve the 2.8.0 release.
+
Snapshot 2.7.99.901 (2009-06-10)
--------------------------------
This is the first release candidate in preparation for the upcoming
commit 34c674dd45879b8ba8395b93b16c8a9e7b848f1f
Author: Keith Packard <keithp@keithp.com>
Date: Sat Jul 11 22:53:42 2009 -0700
Remove vestiges of NoAccel options from i830_driver.c
The enum and OptionInfoRec weren't removed in the initial patch
Signed-off-by: Keith Packard <keithp@keithp.com>
diff --git a/src/i830_driver.c b/src/i830_driver.c
index fe2565c..dfc2bdf 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -162,7 +162,6 @@ static PciChipsets I830PciChipsets[] = {
*/
typedef enum {
- OPTION_NOACCEL,
OPTION_DRI,
OPTION_VIDEO_KEY,
OPTION_COLOR_KEY,
@@ -181,7 +180,6 @@ typedef enum {
} I830Opts;
static OptionInfoRec I830Options[] = {
- {OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE},
commit 33d6e7a2355dfb8ad324c4fa28ce61c7e051b435
Author: Keith Packard <keithp@keithp.com>
Date: Sat Jul 11 22:53:11 2009 -0700
intel.man: Mark NoAccel option as i810/i815 only
The NoAccel option is not valid for other chips.
Signed-off-by: Keith Packard <keithp@keithp.com>
diff --git a/man/intel.man b/man/intel.man
index 6330e4b..d498d7e 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -56,11 +56,6 @@ The following driver
.B Options
are supported
.TP
-.BI "Option \*qNoAccel\*q \*q" boolean \*q
-Disable or enable acceleration.
-.IP
-Default: acceleration is enabled.
-.TP
.BI "Option \*qColorKey\*q \*q" integer \*q
This sets the default pixel value for the YUV video overlay key.
.IP
@@ -134,6 +129,11 @@ This option specifies the amount of system memory to use for graphics, in KB.
The default is 8192 if AGP allocable memory is < 128 MB, 16384 if < 192 MB,
24576 if higher. DRI require at least a value of 16384. Higher values may give
better 3D performance, at expense of available system memory.
+.TP
+.BI "Option \*qNoAccel\*q \*q" boolean \*q
+Disable or enable acceleration.
+.IP
+Default: acceleration is enabled.
.PP
The following driver
commit ed8a9a94e1a670ca35311c9ed83d0c479530d41a
Author: Keith Packard <keithp@keithp.com>
Date: Fri Jul 10 17:13:14 2009 -0700
i830_uxa_prepare_access: Flush and wait for idle for non-bo pixmaps
Without kernel support and explicit knowledge about where in the ring the
last rendering operation for a specific pixmap was, we must synchronize with
any outstanding rendering before accessing a pixmap which does not have a
buffer object.
Signed-off-by: Keith Packard <keithp@keithp.com>
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index c3fdcec..2050c48 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -477,13 +477,12 @@ static Bool
i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
{
dri_bo *bo = i830_get_pixmap_bo (pixmap);
+ ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
+
+ intel_batch_flush(scrn, FALSE);
if (bo) {
- ScreenPtr screen = pixmap->drawable.pScreen;
- ScrnInfoPtr scrn = xf86Screens[screen->myNum];
I830Ptr i830 = I830PTR(scrn);
-
- intel_batch_flush(scrn, FALSE);
/* No VT sema or GEM? No GTT mapping. */
if (!scrn->vtSema || !i830->have_gem) {
@@ -517,7 +516,9 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
drm_intel_gem_bo_start_gtt_access(bo, access == UXA_ACCESS_RW);
pixmap->devPrivate.ptr = i830->FbBase + bo->offset;
}
- }
+ } else
+ i830_wait_ring_idle(scrn);
+
return TRUE;
}
commit cb19ac207b784d814f6f389110fd1b21a0f34e8b
Author: Keith Packard <keithp@keithp.com>
Date: Fri Jul 10 14:01:02 2009 -0700
KMS: Keep screen pixmap devPrivate.ptr NULL during init and resize
The frame buffer only has a valid address between prepare_access and
finish_access calls, so remove all other attempts to compute an address from
the driver.
Signed-off-by: Keith Packard <keithp@keithp.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 7cfdc5b..df10fb5 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1056,12 +1056,9 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
goto fail;
i830_set_pixmap_bo(screen->GetScreenPixmap(screen), pI830->front_buffer->bo);
- scrn->fbOffset = pI830->front_buffer->offset;
screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen),
width, height, -1, -1, pitch * pI830->cpp, NULL);
- xf86DrvMsg(scrn->scrnIndex, X_INFO, "New front buffer at 0x%lx\n",
- pI830->front_buffer->offset);
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
commit 704b88dd50a7e7e3f362264b86d0401bee8603aa
Author: Keith Packard <keithp@keithp.com>
Date: Wed Jul 8 13:06:47 2009 -0700
i830_bind_memory: Under UMS: Bind GEM bos with dri_bo_pin, else through the GART
We only need to get static offsets for objects when not running KMS,
otherwise the kernel will manage those as needed for us.
Binding objects is done in one of two ways. For GEM buffer objects, we use
dri_bo_pin. For GART allocated memory, we bind that to the GART.
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 556b511..f2f3966 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -199,10 +199,11 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
{
I830Ptr pI830 = I830PTR(pScrn);
- if (mem == NULL || mem->bound)
+ if (mem == NULL || mem->bound || pI830->use_drm_mode)
return TRUE;
- if (mem->bo != NULL && !pI830->use_drm_mode) {
+ if (pI830->have_gem && mem->bo != NULL) {
+
if (dri_bo_pin(mem->bo, mem->alignment) != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to pin %s: %s\n",
@@ -213,9 +214,7 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
mem->bound = TRUE;
mem->offset = mem->bo->offset;
mem->end = mem->offset + mem->size;
- }
-
- if (!mem->bound) {
+ } else {
if (!pI830->gtt_acquired)
return TRUE;
@@ -228,8 +227,7 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
mem->bound = TRUE;
}
- if (mem->tiling != TILE_NONE && !pI830->use_drm_mode &&
- !pI830->kernel_exec_fencing) {
+ if (mem->tiling != TILE_NONE && !pI830->kernel_exec_fencing) {
mem->fence_nr = i830_set_tiling(pScrn, mem->offset, mem->pitch,
mem->allocated_size, mem->tiling);
}
@@ -1114,7 +1112,7 @@ i830_allocate_framebuffer(ScrnInfoPtr pScrn)
return NULL;
}
- if (!pI830->use_drm_mode && pI830->FbBase && front_buffer->bound)
+ if (pI830->FbBase && front_buffer->bound)
memset (pI830->FbBase + front_buffer->offset, 0, size);
i830_set_max_gtt_map_size(pScrn);
commit 7b273732f70e91df8b41d5c48e1379271557dd8e
Author: Keith Packard <keithp@keithp.com>
Date: Wed Jul 8 11:53:13 2009 -0700
Allocate GTT space for GEM only under UMS
GEM requires GTT space to map objects. Under KMS, the kernel driver has
already provided all available GTT space to GEM, so the X server need not do
anything.
Signed-off-by: Keith Packard <keithp@keithp.com>
diff --git a/src/i830_driver.c b/src/i830_driver.c
index e5e5fd7..fe2565c 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2674,8 +2674,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
if (!pI830->use_drm_mode)
I830MapMMIO(pScrn);
- /* Need FB mapped to set up the fake bufmgr if we end up doing that
- * in i830_memory_init() -> i830_allocator_init().
+ /* Need FB mapped to access non-GEM objects like
+ * a UMS frame buffer, or the fake bufmgr.
*/
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