Bug#508999: more on 508999 (lenny with wrong frequencies on Radeon Xpress 200)

["Bernhard R. Link" <brlink@debian.org>]

* Alex Deucher <alexdeucher@gmail.com> [081222 10:18]:
> We only use the lower 8 bits because bits 9:8 select the pll dividers
> to use; changing it breaks some chips.  Some rv410 chips have a
> similar issue.  Does this patch fix it for you?

The patch does not apply cleanly on the lenny version, it looks like the
first two lines of this are swapped:

>  		RADEONRestoreFP2Registers(pScrn, info->ModeReg);
>  		RADEONRestoreDVOChip(pScrn, output);
> +		if ((radeon_crtc->crtc_id == 0) && info->IsIGP)
> +		    RADEONSelDiv0(pScrn);

Even when I switch those lines so that it applies, it does not work.

> @@ -1419,6 +1423,8 @@ legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode,
>      case MT_LCD:
>  	ErrorF("restore LVDS\n");
>  	RADEONRestoreLVDSRegisters(pScrn, info->ModeReg);
> +	if ((radeon_crtc->crtc_id == 0) && (info->ChipFamily == CHIP_FAMILY_RV410))
> +	    RADEONSelDiv0(pScrn);
>  	break;

The cards I have here are 1002:5974 and grep 5974 src/radeon_chipinfo_gen.h
says:
 { 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 },

Thus I added CHIP_FAMILY_RS480 there and then it seems to work. Modified patch
attached.

BTW: I was quite confused by the "ErrorF" there and first thought that
was an error path normaly not used and thus a bit perplexed why changing
that code even helps, but looking at the Xorg.log, it seems to be
actually called....

Hochachtungsvoll,
	Bernhard R. Link

diff -u -r xserver-xorg-video-ati-6.9.0/src/legacy_output.c xserver-xorg-video-ati-6.9.0/src/legacy_output.c
--- xserver-xorg-video-ati-6.9.0/src/legacy_output.c	2008-12-20 19:06:32.000000000 +0100
+++ xserver-xorg-video-ati-6.9.0/src/legacy_output.c	2008-12-22 10:46:20.000000000 +0100
@@ -153,6 +153,15 @@
 
 }
 
+static void
+RADEONSelDiv0(ScrnInfoPtr pScrn)
+{
+    RADEONInfoPtr  info       = RADEONPTR(pScrn);
+    unsigned char *RADEONMMIO = info->MMIO;
+
+    OUTREG(RADEON_CLOCK_CNTL_INDEX, 0);
+}
+
 /* Write LVDS registers */
 void
 RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore)
@@ -163,12 +172,7 @@
     if (info->IsMobility) {
 	OUTREG(RADEON_LVDS_GEN_CNTL,  restore->lvds_gen_cntl);
 	/*OUTREG(RADEON_LVDS_PLL_CNTL,  restore->lvds_pll_cntl);*/
-
-	if (info->ChipFamily == CHIP_FAMILY_RV410) {
-	    OUTREG(RADEON_CLOCK_CNTL_INDEX, 0);
-	}
     }
-
 }
 
 void
@@ -1417,6 +1421,8 @@
     case MT_LCD:
 	ErrorF("restore LVDS\n");
 	RADEONRestoreLVDSRegisters(pScrn, info->ModeReg);
+	if ((radeon_crtc->crtc_id == 0) && (info->ChipFamily == CHIP_FAMILY_RS480 || info->ChipFamily == CHIP_FAMILY_RV410))
+	    RADEONSelDiv0(pScrn);
 	break;
     case MT_DFP:
 	if (radeon_output->TMDSType == TMDS_INT) {
@@ -1443,8 +1449,10 @@
 		}
 		OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 	    } else {
-		RADEONRestoreDVOChip(pScrn, output);
-		RADEONRestoreFP2Registers(pScrn, info->ModeReg);
+  		RADEONRestoreFP2Registers(pScrn, info->ModeReg);
+  		RADEONRestoreDVOChip(pScrn, output);
+ 		if ((radeon_crtc->crtc_id == 0) && info->IsIGP)
+ 		    RADEONSelDiv0(pScrn);
 	    }
 	}
 	break;