xserver-xorg-video-ati: Changes to 'upstream-unstable'
src/radeon.h | 1 +
src/radeon_bios.c | 41 +++++++++++++++++++++++++----------------
src/radeon_driver.c | 12 ++----------
src/radeon_output.c | 11 ++---------
src/radeon_video.c | 21 +++++++++++++++++++++
5 files changed, 51 insertions(+), 35 deletions(-)
New commits:
commit 1f78f3bd034a128e1a1d6812da0633138300e48c
Author: Bryce Harrington <bryce@bryceharrington.org>
Date: Wed Aug 20 09:46:59 2008 -0400
radeon: Fix pasto in connector table setup for vga powerbooks
fixes bug 17214
(cherry picked from commit 1cf7a5494fa94e8d9f30f9b2905dfbe6d4faa445)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 53a7e42..0d343f5 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2313,8 +2313,8 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[1].ddc_i2c = legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
info->BiosConnector[1].DACType = DAC_PRIMARY;
- info->BiosConnector[1].TMDSType = TMDS_INT;
- info->BiosConnector[1].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[1].TMDSType = TMDS_NONE;
+ info->BiosConnector[1].ConnectorType = CONNECTOR_VGA;
info->BiosConnector[1].valid = TRUE;
info->BiosConnector[2].ConnectorType = CONNECTOR_STV;
commit 96ff37226ef6f06a05535f3a6f73a4c104f4024d
Author: Michel Dänzer <michel@tungstengraphics.com>
Date: Thu Aug 14 15:21:51 2008 -0400
Make sure video offerlay offsets don't exceed the hardware limit of 128 MB.
Always set the overlay base address such that the buffer offsets are as small
as possible. This could still break in theory if the buffers were more than
128 MB apart, but in reality this can't happen ATM because we always allocate
a single memory area for all buffers.
Fixes http://bugs.freedesktop.org/show_bug.cgi?id=16845 .
(cherry picked from commit a55e85f742d1334bf88e4681e553f025d2de38df)
diff --git a/src/radeon_video.c b/src/radeon_video.c
index ac60166..57dcd8a 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -2586,6 +2586,7 @@ RADEONDisplayVideo(
RADEONOutputPrivatePtr radeon_output;
xf86OutputPtr output;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ int base_offset;
is_rgb=0; is_planar=0;
switch(id){
@@ -2715,6 +2716,22 @@ RADEONDisplayVideo(
}
#endif
+ /* Make the overlay base address as close to the buffers as possible to
+ * prevent the buffer offsets from exceeding the hardware limit of 128 MB.
+ * The base address must be aligned to a multiple of 4 MB.
+ */
+ base_offset = ((info->fbLocation +
+ min(offset1, min(offset2, min(offset3, min(offset4,
+ min(offset5, offset6)))))) & (~0 << 22)) -
+ info->fbLocation;
+
+ offset1 -= base_offset;
+ offset2 -= base_offset;
+ offset3 -= base_offset;
+ offset4 -= base_offset;
+ offset5 -= base_offset;
+ offset6 -= base_offset;
+
/* keep everything in 16.16 */
if (is_planar) {
@@ -2846,6 +2863,10 @@ RADEONDisplayVideo(
src_w >>= 1;
OUTREG(RADEON_OV0_P2_X_START_END, (src_w + leftuv - 1) | (leftuv << 16));
OUTREG(RADEON_OV0_P3_X_START_END, (src_w + leftuv - 1) | (leftuv << 16));
+ if (info->ModeReg->ov0_base_addr != (info->fbLocation + base_offset)) {
+ info->ModeReg->ov0_base_addr = info->fbLocation + base_offset;
+ OUTREG(RADEON_OV0_BASE_ADDR, info->ModeReg->ov0_base_addr);
+ }
OUTREG(RADEON_OV0_VID_BUF0_BASE_ADRS, offset1);
OUTREG(RADEON_OV0_VID_BUF1_BASE_ADRS, offset2);
OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset3);
commit caad65eee3124af2a3d4c005707a621ad8420e15
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Wed Aug 6 00:35:15 2008 -0400
Remove un-needed dac check for single crtc cards
Connector tables should be setup properly already and this
check breaks systems with 2 DACs and 1 crtc like the es1000.
(cherry picked from commit 18429390440a829fb24ed3afd99ccf8278138496)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index b22442c..53a7e42 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2749,13 +2749,6 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
RADEONSetupGenericConnectors(pScrn);
}
- if (!pRADEONEnt->HasCRTC2) {
- for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
- if (info->BiosConnector[i].ConnectorType == CONNECTOR_VGA)
- info->BiosConnector[i].DACType = DAC_PRIMARY;
- }
- }
-
/* parse connector table option */
optstr = (char *)xf86GetOptValString(info->Options, OPTION_CONNECTORTABLE);
commit c063add0cd5559f8b5bb2c0d754d962bfdc16682
Author: Alex Deucher <alexdeucher@gmail.com>
Date: Fri Aug 8 15:50:07 2008 -0400
Fix VT switching on M6 chips
Some M6 chips have a faulty MEM_SIZE register that in
some cases reports 0 on 8 MB cards. On EnterVT we check
the MEM_SIZE reg as a check to see if the card is posted or
not. Since this reg returns 0, the driver attempts to post
the card which can lead to a hang. Switch this to check if
either crtc is active as is done in the bios init code.
fixes bug 13994
(cherry picked from commit 268c848130ec1770bb645a74197b6aca7fc95abc)
diff --git a/src/radeon.h b/src/radeon.h
index f68fa0f..5191808 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -901,6 +901,7 @@ extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output);
extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output);
extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output);
extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn);
+extern Bool radeon_card_posted(ScrnInfoPtr pScrn);
/* radeon_commonfuncs.c */
#ifdef XF86DRI
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index adedeb3..66b0995 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -266,6 +266,26 @@ radeon_read_unposted_bios(ScrnInfoPtr pScrn)
return ret;
}
+Bool
+radeon_card_posted(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ uint32_t reg;
+
+ if (IS_AVIVO_VARIANT) {
+ reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL);
+ if (reg & AVIVO_CRTC_EN)
+ return TRUE;
+ } else {
+ reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL);
+ if (reg & RADEON_CRTC_EN)
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
/* Read the Video BIOS block and the FP registers (if applicable). */
Bool
RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
@@ -273,7 +293,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
RADEONInfoPtr info = RADEONPTR(pScrn);
int tmp;
unsigned short dptr;
- Bool unposted = FALSE;
+ Bool posted = TRUE;
#ifdef XSERVER_LIBPCIACCESS
int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ? info->PciInfo->rom_size : RADEON_VBIOS_SIZE;
@@ -292,7 +312,7 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
RADEON_VBIOS_SIZE);
} else if (!radeon_read_bios(pScrn)) {
(void)radeon_read_unposted_bios(pScrn);
- unposted = TRUE;
+ posted = FALSE;
}
}
@@ -387,22 +407,11 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10)
* so let's work around this for now by only POSTing if none of the
* CRTCs are enabled
*/
- if (unposted && info->VBIOS) {
- unsigned char *RADEONMMIO = info->MMIO;
- uint32_t reg;
-
- if (IS_AVIVO_VARIANT) {
- reg = INREG(AVIVO_D1CRTC_CONTROL) | INREG(AVIVO_D2CRTC_CONTROL);
- if (reg & AVIVO_CRTC_EN)
- unposted = FALSE;
- } else {
- reg = INREG(RADEON_CRTC_GEN_CNTL) | INREG(RADEON_CRTC2_GEN_CNTL);
- if (reg & RADEON_CRTC_EN)
- unposted = FALSE;
- }
+ if ((!posted) && info->VBIOS) {
+ posted = radeon_card_posted(pScrn);
}
- if (unposted && info->VBIOS) {
+ if ((!posted) && info->VBIOS) {
if (info->IsAtomBios) {
if (!rhdAtomASICInit(info->atomBIOS))
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index e067cb7..b6e1990 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5371,26 +5371,18 @@ Bool RADEONEnterVT(int scrnIndex, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- uint32_t mem_size;
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"RADEONEnterVT\n");
- if (info->ChipFamily >= CHIP_FAMILY_R600)
- mem_size = INREG(R600_CONFIG_MEMSIZE);
- else
- mem_size = INREG(RADEON_CONFIG_MEMSIZE);
-
- if (mem_size == 0) { /* Softboot V_BIOS */
+ if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */
if (info->IsAtomBios) {
rhdAtomASICInit(info->atomBIOS);
} else {
xf86Int10InfoPtr pInt;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "zero MEMSIZE, probably at D3cold. Re-POSTing via int10.\n");
+
pInt = xf86InitInt10 (info->pEnt->index);
if (pInt) {
pInt->num = 0xe6;
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