xserver-xorg-video-ati: Changes to 'upstream-unstable'
Rebased ref, commits from common ancestor:
commit eb99c3c5c9a2249cb84920f0f225e525fc3a4144
Author: Alex Deucher <alex@botch2.(none)>
Date: Thu Dec 20 18:14:38 2007 -0500
Bump for RC release
diff --git a/configure.ac b/configure.ac
index ae5cb2b..48302d2 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-ati],
- 6.7.196,
+ 6.7.197,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-ati)
commit 8d49ff1da917b7f8240267953ef6ce4ff04daecb
Author: Alex Deucher <alex@botch2.(none)>
Date: Thu Dec 20 01:09:57 2007 -0500
RADEON: check for xf86_crtc_clip_video_helper() in configure.ac
use xf86_crtc_clip_video_helper() from the server if available.
diff --git a/configure.ac b/configure.ac
index cc4d490..ae5cb2b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -209,6 +209,11 @@ AC_CHECK_DECL(xf86ModeBandwidth,
[],
[#include "xf86Modes.h"])
+AC_CHECK_DECL(xf86_crtc_clip_video_helper,
+ [AC_DEFINE(HAVE_XF86CRTCCLIPVIDEOHELPER, 1, [Have xf86_crtc_clip_video_helper prototype])],
+ [],
+ [#include "xf86Crtc.h"])
+
AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 3f0209e..2b5764f 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -119,6 +119,7 @@ static Atom xvOvAlpha, xvGrAlpha, xvAlphaMode;
#define GET_PORT_PRIVATE(pScrn) \
(RADEONPortPrivPtr)((RADEONPTR(pScrn))->adaptor->pPortPrivates[0].ptr)
+#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER
static void
radeon_box_intersect(BoxPtr dest, BoxPtr a, BoxPtr b)
{
@@ -185,17 +186,17 @@ radeon_covering_crtc(ScrnInfoPtr pScrn,
}
static Bool
-radeon_clip_video_helper(ScrnInfoPtr pScrn,
- xf86CrtcPtr *crtc_ret,
- xf86CrtcPtr desired_crtc,
- BoxPtr dst,
- INT32 *xa,
- INT32 *xb,
- INT32 *ya,
- INT32 *yb,
- RegionPtr reg,
- INT32 width,
- INT32 height)
+radeon_crtc_clip_video_helper(ScrnInfoPtr pScrn,
+ xf86CrtcPtr *crtc_ret,
+ xf86CrtcPtr desired_crtc,
+ BoxPtr dst,
+ INT32 *xa,
+ INT32 *xb,
+ INT32 *ya,
+ INT32 *yb,
+ RegionPtr reg,
+ INT32 width,
+ INT32 height)
{
Bool ret;
RegionRec crtc_region_local;
@@ -227,6 +228,31 @@ radeon_clip_video_helper(ScrnInfoPtr pScrn,
return ret;
}
+#endif
+
+static Bool
+radeon_crtc_clip_video(ScrnInfoPtr pScrn,
+ xf86CrtcPtr *crtc_ret,
+ xf86CrtcPtr desired_crtc,
+ BoxPtr dst,
+ INT32 *xa,
+ INT32 *xb,
+ INT32 *ya,
+ INT32 *yb,
+ RegionPtr reg,
+ INT32 width,
+ INT32 height)
+{
+#ifndef HAVE_XF86CRTCCLIPVIDEOHELPER
+ return radeon_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc,
+ dst, xa, xb, ya, yb,
+ reg, width, height);
+#else
+ return xf86_crtc_clip_video_helper(pScrn, crtc_ret, desired_crtc,
+ dst, xa, xb, ya, yb,
+ reg, width, height);
+#endif
+}
#ifdef USE_EXA
static void
@@ -2899,9 +2925,9 @@ RADEONPutImage(
dstBox.y1 = drw_y;
dstBox.y2 = drw_y + drw_h;
- if (!radeon_clip_video_helper(pScrn, &crtc, pPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
+ if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb,
+ clipBoxes, width, height))
return Success;
if (!crtc) {
@@ -3295,9 +3321,9 @@ RADEONDisplaySurface(
dstBox.y1 = drw_y;
dstBox.y2 = drw_y + drw_h;
- if (!radeon_clip_video_helper(pScrn, &crtc, portPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb, clipBoxes,
- surface->width, surface->height))
+ if (!radeon_crtc_clip_video(pScrn, &crtc, portPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb, clipBoxes,
+ surface->width, surface->height))
return Success;
if (!crtc) {
@@ -3438,9 +3464,9 @@ RADEONPutVideo(
else
vbi_line_width = 2000; /* might need adjustment */
- if (!radeon_clip_video_helper(pScrn, &crtc, pPriv->desired_crtc,
- &dstBox, &xa, &xb, &ya, &yb,
- clipBoxes, width, height))
+ if (!radeon_crtc_clip_video(pScrn, &crtc, pPriv->desired_crtc,
+ &dstBox, &xa, &xb, &ya, &yb,
+ clipBoxes, width, height))
return Success;
if (!crtc) {
commit fb7a4e24f2da3561ef81371ca4013a4f13806e91
Author: Adam Jackson <ajax@redhat.com>
Date: Wed Dec 19 19:15:19 2007 -0500
Fix RN50 mode filtering.
The old code would attempt to limit the maximum pixel size of the screen
by limiting the maximum PLL frequency. This ends up confusing the PLL
computation code since sometimes your maximum freq can be lower than your
minimum freq. More to the point it's just wrong, maximum PLL frequency
isn't the same thing as maximum pixel clock, and even that isn't the same
thing as maximum scanout pixels per second.
The correct thing to do is filter by the mode's effective memory bandwidth.
diff --git a/configure.ac b/configure.ac
index 1570e54..cc4d490 100644
--- a/configure.ac
+++ b/configure.ac
@@ -204,6 +204,11 @@ AC_CHECK_DECL(xf86XVFillKeyHelperDrawable,
[],
[#include <xf86xv.h>])
+AC_CHECK_DECL(xf86ModeBandwidth,
+ [AC_DEFINE(HAVE_XF86MODEBANDWIDTH, 1, [Have xf86ModeBandwidth prototype])],
+ [],
+ [#include "xf86Modes.h"])
+
AC_CHECK_DECL(XSERVER_LIBPCIACCESS,
[XSERVER_LIBPCIACCESS=yes],[XSERVER_LIBPCIACCESS=no],
[#include "xorg-server.h"])
diff --git a/src/radeon.h b/src/radeon.h
index 03db360..801d616 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -41,6 +41,7 @@
#include <unistd.h> /* For usleep() */
#include <sys/time.h> /* For gettimeofday() */
+#include "config.h"
#include "xf86str.h"
#include "compiler.h"
#include "xf86fbman.h"
@@ -97,6 +98,11 @@
#define MIN(a,b) ((a)>(b)?(b):(a))
#endif
+#ifndef HAVE_XF86MODEBANDWIDTH
+extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth);
+#define MODE_BANDWIDTH MODE_BAD
+#endif
+
typedef enum {
OPTION_NOACCEL,
OPTION_SW_CURSOR,
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 25b2119..9f9fd90 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1051,18 +1051,6 @@ static void RADEONGetClockInfo(ScrnInfoPtr pScrn)
info->mclk = 200.00;
}
- if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
- /* Avoid RN50 corruption due to memory bandwidth starvation.
- * 18 is an empirical value based on the databook and Windows driver.
- *
- * Empirical value changed to 24 to raise pixel clock limit and
- * allow higher resolution modes on capable monitors
- */
- pll->max_pll_freq = min(pll->max_pll_freq,
- 24 * info->mclk * 100 / pScrn->bitsPerPixel *
- info->RamWidth / 16);
- }
-
/* card limits for computing PLLs */
pll->min_ref_div = 2;
pll->max_ref_div = 0x3ff;
@@ -5380,10 +5368,44 @@ Bool RADEONHandleMessage(int scrnIndex, const char* msgtype,
}
#endif
+#ifndef HAVE_XF86MODEBANDWIDTH
+/** Calculates the memory bandwidth (in MiB/sec) of a mode. */
+_X_HIDDEN unsigned int
+xf86ModeBandwidth(DisplayModePtr mode, int depth)
+{
+ float a_active, a_total, active_percent, pixels_per_second;
+ int bytes_per_pixel = (depth + 7) / 8;
+
+ if (!mode->HTotal || !mode->VTotal || !mode->Clock)
+ return 0;
+
+ a_active = mode->HDisplay * mode->VDisplay;
+ a_total = mode->HTotal * mode->VTotal;
+ active_percent = a_active / a_total;
+ pixels_per_second = active_percent * mode->Clock * 1000.0;
+
+ return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024));
+}
+#endif
+
/* Used to disallow modes that are not supported by the hardware */
ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode,
Bool verbose, int flag)
{
+ ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /*
+ * RN50 has effective maximum mode bandwidth of about 300MiB/s.
+ * XXX should really do this for all chips by properly computing
+ * memory bandwidth and an overhead factor.
+ */
+ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+ if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300)
+ return MODE_BANDWIDTH;
+ }
+
/* There are problems with double scan mode at high clocks
* They're likely related PLL and display buffer settings.
* Disable these modes for now.
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 9850702..64c0438 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -789,6 +789,19 @@ static int
radeon_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
{
RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ ScrnInfoPtr pScrn = output->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /*
+ * RN50 has effective maximum mode bandwidth of about 300MiB/s.
+ * XXX should really do this for all chips by properly computing
+ * memory bandwidth and an overhead factor.
+ */
+ if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
+ if (xf86ModeBandwidth(pMode, pScrn->bitsPerPixel) > 300)
+ return MODE_BANDWIDTH;
+ }
if (radeon_output->type == OUTPUT_STV ||
radeon_output->type == OUTPUT_CTV) {
commit 0e6634870d1ab38ee8c83f6bda1ba60364997853
Author: Alex Deucher <alex@botch2.(none)>
Date: Wed Dec 19 11:54:27 2007 -0500
RADEON: skip empty connectors when creating outputs
diff --git a/src/radeon_output.c b/src/radeon_output.c
index c60ece8..115666d 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -3217,6 +3217,10 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
+
+ if (info->BiosConnector[i].ConnectorType == CONNECTOR_NONE)
+ continue;
+
RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
if (!radeon_output) {
return FALSE;
commit 6afbf718c151dc3c5c59bd3136b58a93a114d798
Author: Alex Deucher <alex@botch2.(none)>
Date: Wed Dec 19 11:48:38 2007 -0500
RADEON: add support for legacy radeons with DVI and no connector table
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index d150c4b..7d4d12a 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -277,7 +277,21 @@ static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "No Connector Info Table found!\n");
- return FALSE;
+
+ /* old radeons and r128 didn't use connector tables you just check
+ * for LVDS, DVI, TV, etc. tables
+ */
+ offset = RADEON_BIOS16(info->ROMHeaderStart + 0x34);
+ if (offset) {
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Found DFP table, assuming DVI connector\n");
+ info->BiosConnector[0].valid = TRUE;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_DVI_I;
+ info->BiosConnector[0].DACType = DAC_PRIMARY;
+ info->BiosConnector[0].TMDSType = TMDS_INT;
+ info->BiosConnector[0].DDCType = DDC_DVI;
+ } else
+ return FALSE;
}
/* check LVDS table */
commit ce4fa1cedec0cf56b9979dfaa12a8d3a7c643df4
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:34:14 2007 -0500
RADEON: fix fd leak in lid detect code
diff --git a/src/radeon_output.c b/src/radeon_output.c
index c60ece8..6454460 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -699,15 +699,18 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn)
while (fgets(lidline, sizeof lidline, f)) {
if (!strncmp(lidline, "state:", strlen ("state:"))) {
if (strstr(lidline, "open")) {
+ fclose(f);
ErrorF("proc lid open\n");
return MT_LCD;
}
else if (strstr(lidline, "closed")) {
+ fclose(f);
ErrorF("proc lid closed\n");
return MT_NONE;
}
}
}
+ fclose(f);
}
#endif
commit 20568f66f9a9a60a33bd9a69ccc14a891c656836
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:32:10 2007 -0500
RADEON: more cleanups and warning fixes
diff --git a/src/atividmem.c b/src/atividmem.c
index 8910c73..986ac0f 100644
--- a/src/atividmem.c
+++ b/src/atividmem.c
@@ -103,14 +103,12 @@ ATIUnmapLinear
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pMemory)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMemory, pATI->LinearSize);
#else
- pci_device_unmap_range(pVideo, pATI->pMemory, pATI->LinearSize);
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemory, pATI->LinearSize);
#endif
#if X_BYTE_ORDER != X_LITTLE_ENDIAN
@@ -120,7 +118,7 @@ ATIUnmapLinear
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMemoryLE, pATI->LinearSize);
#else
- pci_device_unmap_range(pVideo, pATI->pMemoryLE, pATI->LinearSize);
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemoryLE, pATI->LinearSize);
#endif
}
@@ -143,14 +141,12 @@ ATIUnmapMMIO
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pMMIO)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMMIO, getpagesize());
#else
- pci_device_unmap_range(pVideo, pATI->pMMIO, getpagesize());
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, getpagesize());
#endif
}
@@ -169,14 +165,12 @@ ATIUnmapCursor
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pCursorPage)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pCursorPage, getpagesize());
#else
- pci_device_unmap_range(pVideo, pATI->pCursorPage, getpagesize());
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pCursorPage, getpagesize());
#endif
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 41375da..07857dd 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -145,15 +145,13 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
static void
RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
{
- ScrnInfoPtr pScrn = crtc->scrn;
-
save->surface_cntl = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* We must set both apertures as they can be both used to map the entire
* video memory. -BenH.
*/
- switch (pScrn->bitsPerPixel) {
+ switch (crtc->scrn->bitsPerPixel) {
case 16:
save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 9dd6eb8..ba1159c 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -232,7 +232,7 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
+ CURSOR_SWAPPING_DECL_MMIO
CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset);
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
commit 1496194200adbcb044ec3977367a0908262e389c
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:29:53 2007 -0500
RADEON: driver cleanups, warning fixes
diff --git a/configure.ac b/configure.ac
index b3d46a5..1570e54 100644
--- a/configure.ac
+++ b/configure.ac
@@ -58,7 +58,7 @@ AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri],
AC_ARG_ENABLE(exa,
AC_HELP_STRING([--disable-exa],
- [Disable EXA support [[default enabled]]]),
+ [Disable EXA support [[default=enabled]]]),
[EXA="$enableval"],
[EXA=yes])
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6028aff..ed7d1e9 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -136,8 +136,8 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries)
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"FIFO timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
+ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ (unsigned int)INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"FIFO timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
@@ -168,7 +168,7 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn)
if (i == RADEON_TIMEOUT) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DC flush timeout: %x\n",
- INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
+ (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
}
}
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 6a999af..a1802f8 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -174,8 +174,8 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Idle timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
+ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ (unsigned int)INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Idle timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 6bbd315..ea31a82 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -743,7 +743,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH_BUFFER_CNTL from %x to %x\n",
(unsigned int)info->SavedReg.grph_buffer_cntl,
- INREG(RADEON_GRPH_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
stop_req = mode2->HDisplay * pixel_bytes2 / 16;
@@ -793,7 +793,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH2_BUFFER_CNTL from %x to %x\n",
(unsigned int)info->SavedReg.grph2_buffer_cntl,
- INREG(RADEON_GRPH2_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL));
}
}
commit 44d07c4ccce9acb5bd21a17acb082e91f7225764
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:56:12 2007 -0500
RADEON: typo from last commit
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 95f6b09..6bbd315 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -405,6 +405,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->DACType == DAC_TVDAC) {
info->output_crt2 &= ~(1 << o);
+ tv_dac_change = 1;
if (!info->output_crt2) {
if (info->ChipFamily == CHIP_FAMILY_R200) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
@@ -416,7 +417,6 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
tmp &= ~RADEON_CRTC2_CRT2_ON;
OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- tv_dac_change = 1;
}
}
}
@@ -462,11 +462,11 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
info->output_tv1 &= ~(1 << o);
+ tv_dac_change = 2;
if (!info->output_tv1) {
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp &= ~RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
radeon_output->tv_on = FALSE;
}
}
commit 4da3782239921eb377216d4de4a9cc5bb55e0e8a
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:51:31 2007 -0500
RADEON: add output enable masks
add output enable masks for outputs that drive
more than one connector. Make sure we don't turn off
an output that's driving another connector.
diff --git a/src/radeon.h b/src/radeon.h
index 67315a2..03db360 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -850,6 +850,14 @@ typedef struct {
#endif
RADEONExtTMDSChip ext_tmds_chip;
+ /* output enable masks for outputs shared across connectors */
+ int output_crt1;
+ int output_crt2;
+ int output_dfp1;
+ int output_dfp2;
+ int output_lcd1;
+ int output_tv1;
+
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 9437ef4..95f6b09 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -322,19 +322,28 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
unsigned char * RADEONMMIO = info->MMIO;
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
- int tv_dac_change = 0;
+ int tv_dac_change = 0, o;
radeon_output = output->driver_private;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+
+ for (o = 0; o < xf86_config->num_output; o++) {
+ if (output == xf86_config->output[o]) {
+ break;
+ }
+ }
if (bEnable) {
ErrorF("enable montype: %d\n", radeon_output->MonType);
if (radeon_output->MonType == MT_CRT) {
if (radeon_output->DACType == DAC_PRIMARY) {
+ info->output_crt1 |= (1 << o);
tmp = INREG(RADEON_CRTC_EXT_CNTL);
tmp |= RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
} else if (radeon_output->DACType == DAC_TVDAC) {
+ info->output_crt2 |= (1 << o);
if (info->ChipFamily == CHIP_FAMILY_R200) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
@@ -350,11 +359,13 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
+ info->output_dfp1 |= (1 << o);
tmp = INREG(RADEON_FP_GEN_CNTL);
tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
OUTREG(RADEON_FP_GEN_CNTL, tmp);
save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
} else if (radeon_output->TMDSType == TMDS_EXT) {
+ info->output_dfp2 |= (1 << o);
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp &= ~RADEON_FP2_BLANK_EN;
tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
@@ -363,6 +374,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
}
} else if (radeon_output->MonType == MT_LCD) {
+ info->output_lcd1 |= (1 << o);
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
@@ -372,6 +384,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
} else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
+ info->output_tv1 |= (1 << o);
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp |= RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
@@ -382,70 +395,88 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
ErrorF("disable montype: %d\n", radeon_output->MonType);
if (radeon_output->MonType == MT_CRT) {
if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ info->output_crt1 &= ~(1 << o);
+ if (!info->output_crt1) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ }
} else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ info->output_crt2 &= ~(1 << o);
+ if (!info->output_crt2) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ tv_dac_change = 1;
+ }
}
- tv_dac_change = 1;
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ info->output_dfp1 &= ~(1 << o);
+ if (!info->output_dfp1) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ }
} else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= RADEON_FP2_BLANK_EN;
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ info->output_dfp2 &= ~(1 << o);
+ if (!info->output_dfp2) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= RADEON_FP2_BLANK_EN;
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ }
}
} else if (radeon_output->MonType == MT_LCD) {
- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- if (info->IsMobility || info->IsIGP) {
- /* Asic bug, when turning off LVDS_ON, we have to make sure
- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
- */
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
- }
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- if (info->IsMobility || info->IsIGP) {
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ info->output_lcd1 &= ~(1 << o);
+ if (!info->output_lcd1) {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
}
} else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
- tmp = INREG(RADEON_TV_MASTER_CNTL);
- tmp &= ~RADEON_TV_ON;
- OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
- radeon_output->tv_on = FALSE;
+ info->output_tv1 &= ~(1 << o);
+ if (!info->output_tv1) {
+ tmp = INREG(RADEON_TV_MASTER_CNTL);
+ tmp &= ~RADEON_TV_ON;
+ OUTREG(RADEON_TV_MASTER_CNTL, tmp);
+ tv_dac_change = 2;
+ radeon_output->tv_on = FALSE;
+ }
}
}
if (tv_dac_change) {
if (bEnable)
- info->tv_dac_enable_mask |= tv_dac_change;
+ info->tv_dac_enable_mask |= tv_dac_change;
else
- info->tv_dac_enable_mask &= ~tv_dac_change;
+ info->tv_dac_enable_mask &= ~tv_dac_change;
if (bEnable && info->tv_dac_enable_mask)
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 9e73c08..c60ece8 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -3207,6 +3207,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
}
}
+ /* clear the enable masks */
+ info->output_crt1 = 0;
+ info->output_crt2 = 0;
+ info->output_dfp1 = 0;
+ info->output_dfp2 = 0;
+ info->output_lcd1 = 0;
+ info->output_tv1 = 0;
+
for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
commit 5c5d2d19b2b032a06dd333b4ecc029aac342fb93
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:15:55 2007 -0500
RADEON: whitespace clean-ups
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 999d349..9437ef4 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -163,7 +163,7 @@ void RADEONGetTVDacAdjInfo(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
+
/* Todo: get this setting from BIOS */
radeon_output->tv_dac_adj = default_tvdac_adj[info->ChipFamily];
if (info->IsMobility) { /* some mobility chips may different */
@@ -202,7 +202,7 @@ static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
} else {
CARD32 tv_dac_cntl;
CARD32 fp2_gen_cntl;
-
+
switch(info->ChipFamily)
{
case CHIP_FAMILY_R420:
@@ -259,19 +259,19 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) {
/* primary DAC */
tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
+ tmp &= ~RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
RADEONDacPowerSet(pScrn, FALSE, TRUE);
/* Secondary DAC */
if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
} else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
}
RADEONDacPowerSet(pScrn, FALSE, FALSE);
@@ -327,95 +327,95 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
if (bEnable) {
ErrorF("enable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp |= RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp |= RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp |= RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp |= RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+ }
+ tv_dac_change = 1;
+ }
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp &= ~RADEON_FP2_BLANK_EN;
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
+ }
+ } else if (radeon_output->MonType == MT_LCD) {
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
Reply to: