xserver-xorg-video-ati: Changes to 'upstream-experimental'
Makefile.am | 2
configure.ac | 2
man/radeon.man | 2
src/atividmem.c | 14 --
src/r128_dri.c | 6
src/r128_probe.c | 2
src/radeon.h | 45 +++++--
src/radeon_accel.c | 6
src/radeon_bios.c | 25 +---
src/radeon_commonfuncs.c | 4
src/radeon_crtc.c | 220 +++++++++++++++++++++++++----------
src/radeon_cursor.c | 49 +++++--
src/radeon_display.c | 289 ++++++++++++++++++++++++++---------------------
src/radeon_dri.c | 18 --
src/radeon_driver.c | 43 ++++--
src/radeon_exa.c | 20 ++-
src/radeon_exa_render.c | 93 +++++++++------
src/radeon_output.c | 117 +++++++++++++++----
src/radeon_probe.h | 1
src/radeon_reg.h | 1
20 files changed, 609 insertions(+), 350 deletions(-)
New commits:
commit ce4fa1cedec0cf56b9979dfaa12a8d3a7c643df4
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:34:14 2007 -0500
RADEON: fix fd leak in lid detect code
diff --git a/src/radeon_output.c b/src/radeon_output.c
index c60ece8..6454460 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -699,15 +699,18 @@ RADEONDetectLidStatus(ScrnInfoPtr pScrn)
while (fgets(lidline, sizeof lidline, f)) {
if (!strncmp(lidline, "state:", strlen ("state:"))) {
if (strstr(lidline, "open")) {
+ fclose(f);
ErrorF("proc lid open\n");
return MT_LCD;
}
else if (strstr(lidline, "closed")) {
+ fclose(f);
ErrorF("proc lid closed\n");
return MT_NONE;
}
}
}
+ fclose(f);
}
#endif
commit 20568f66f9a9a60a33bd9a69ccc14a891c656836
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:32:10 2007 -0500
RADEON: more cleanups and warning fixes
diff --git a/src/atividmem.c b/src/atividmem.c
index 8910c73..986ac0f 100644
--- a/src/atividmem.c
+++ b/src/atividmem.c
@@ -103,14 +103,12 @@ ATIUnmapLinear
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pMemory)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMemory, pATI->LinearSize);
#else
- pci_device_unmap_range(pVideo, pATI->pMemory, pATI->LinearSize);
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemory, pATI->LinearSize);
#endif
#if X_BYTE_ORDER != X_LITTLE_ENDIAN
@@ -120,7 +118,7 @@ ATIUnmapLinear
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMemoryLE, pATI->LinearSize);
#else
- pci_device_unmap_range(pVideo, pATI->pMemoryLE, pATI->LinearSize);
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMemoryLE, pATI->LinearSize);
#endif
}
@@ -143,14 +141,12 @@ ATIUnmapMMIO
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pMMIO)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pMMIO, getpagesize());
#else
- pci_device_unmap_range(pVideo, pATI->pMMIO, getpagesize());
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pMMIO, getpagesize());
#endif
}
@@ -169,14 +165,12 @@ ATIUnmapCursor
ATIPtr pATI
)
{
- pciVideoPtr pVideo = pATI->PCIInfo;
-
if (pATI->pCursorPage)
{
#ifndef XSERVER_LIBPCIACCESS
xf86UnMapVidMem(iScreen, pATI->pCursorPage, getpagesize());
#else
- pci_device_unmap_range(pVideo, pATI->pCursorPage, getpagesize());
+ pci_device_unmap_range(pATI->PCIInfo, pATI->pCursorPage, getpagesize());
#endif
}
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 41375da..07857dd 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -145,15 +145,13 @@ RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
static void
RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save)
{
- ScrnInfoPtr pScrn = crtc->scrn;
-
save->surface_cntl = 0;
#if X_BYTE_ORDER == X_BIG_ENDIAN
/* We must set both apertures as they can be both used to map the entire
* video memory. -BenH.
*/
- switch (pScrn->bitsPerPixel) {
+ switch (crtc->scrn->bitsPerPixel) {
case 16:
save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 9dd6eb8..ba1159c 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -232,7 +232,7 @@ radeon_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
ScrnInfoPtr pScrn = crtc->scrn;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
+ CURSOR_SWAPPING_DECL_MMIO
CARD32 *d = (CARD32 *)(pointer)(info->FB + radeon_crtc->cursor_offset + pScrn->fbOffset);
RADEONCTRACE(("RADEONLoadCursorARGB\n"));
commit 1496194200adbcb044ec3977367a0908262e389c
Author: Arkadiusz Miskiewicz <arekm@maven.pl>
Date: Tue Dec 18 15:29:53 2007 -0500
RADEON: driver cleanups, warning fixes
diff --git a/configure.ac b/configure.ac
index b3d46a5..1570e54 100644
--- a/configure.ac
+++ b/configure.ac
@@ -58,7 +58,7 @@ AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri],
AC_ARG_ENABLE(exa,
AC_HELP_STRING([--disable-exa],
- [Disable EXA support [[default enabled]]]),
+ [Disable EXA support [[default=enabled]]]),
[EXA="$enableval"],
[EXA=yes])
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 6028aff..ed7d1e9 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -136,8 +136,8 @@ void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries)
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"FIFO timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
+ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ (unsigned int)INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"FIFO timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
@@ -168,7 +168,7 @@ void RADEONEngineFlush(ScrnInfoPtr pScrn)
if (i == RADEON_TIMEOUT) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"DC flush timeout: %x\n",
- INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
+ (unsigned int)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT));
}
}
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 6a999af..a1802f8 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -174,8 +174,8 @@ void FUNC_NAME(RADEONWaitForIdle)(ScrnInfoPtr pScrn)
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"Idle timed out: %u entries, stat=0x%08x\n",
- INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
- INREG(RADEON_RBBM_STATUS));
+ (unsigned int)INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK,
+ (unsigned int)INREG(RADEON_RBBM_STATUS));
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Idle timed out, resetting engine...\n");
RADEONEngineReset(pScrn);
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 6bbd315..ea31a82 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -743,7 +743,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH_BUFFER_CNTL from %x to %x\n",
(unsigned int)info->SavedReg.grph_buffer_cntl,
- INREG(RADEON_GRPH_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
if (mode2) {
stop_req = mode2->HDisplay * pixel_bytes2 / 16;
@@ -793,7 +793,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
"GRPH2_BUFFER_CNTL from %x to %x\n",
(unsigned int)info->SavedReg.grph2_buffer_cntl,
- INREG(RADEON_GRPH2_BUFFER_CNTL));
+ (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL));
}
}
commit 44d07c4ccce9acb5bd21a17acb082e91f7225764
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:56:12 2007 -0500
RADEON: typo from last commit
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 95f6b09..6bbd315 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -405,6 +405,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->DACType == DAC_TVDAC) {
info->output_crt2 &= ~(1 << o);
+ tv_dac_change = 1;
if (!info->output_crt2) {
if (info->ChipFamily == CHIP_FAMILY_R200) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
@@ -416,7 +417,6 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
tmp &= ~RADEON_CRTC2_CRT2_ON;
OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- tv_dac_change = 1;
}
}
}
@@ -462,11 +462,11 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
info->output_tv1 &= ~(1 << o);
+ tv_dac_change = 2;
if (!info->output_tv1) {
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp &= ~RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
radeon_output->tv_on = FALSE;
}
}
commit 4da3782239921eb377216d4de4a9cc5bb55e0e8a
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:51:31 2007 -0500
RADEON: add output enable masks
add output enable masks for outputs that drive
more than one connector. Make sure we don't turn off
an output that's driving another connector.
diff --git a/src/radeon.h b/src/radeon.h
index 67315a2..03db360 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -850,6 +850,14 @@ typedef struct {
#endif
RADEONExtTMDSChip ext_tmds_chip;
+ /* output enable masks for outputs shared across connectors */
+ int output_crt1;
+ int output_crt2;
+ int output_dfp1;
+ int output_dfp2;
+ int output_lcd1;
+ int output_tv1;
+
Rotation rotation;
void (*PointerMoved)(int, int, int);
CreateScreenResourcesProcPtr CreateScreenResources;
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 9437ef4..95f6b09 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -322,19 +322,28 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
unsigned char * RADEONMMIO = info->MMIO;
unsigned long tmp;
RADEONOutputPrivatePtr radeon_output;
- int tv_dac_change = 0;
+ int tv_dac_change = 0, o;
radeon_output = output->driver_private;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+
+ for (o = 0; o < xf86_config->num_output; o++) {
+ if (output == xf86_config->output[o]) {
+ break;
+ }
+ }
if (bEnable) {
ErrorF("enable montype: %d\n", radeon_output->MonType);
if (radeon_output->MonType == MT_CRT) {
if (radeon_output->DACType == DAC_PRIMARY) {
+ info->output_crt1 |= (1 << o);
tmp = INREG(RADEON_CRTC_EXT_CNTL);
tmp |= RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
} else if (radeon_output->DACType == DAC_TVDAC) {
+ info->output_crt2 |= (1 << o);
if (info->ChipFamily == CHIP_FAMILY_R200) {
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
@@ -350,11 +359,13 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
+ info->output_dfp1 |= (1 << o);
tmp = INREG(RADEON_FP_GEN_CNTL);
tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
OUTREG(RADEON_FP_GEN_CNTL, tmp);
save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
} else if (radeon_output->TMDSType == TMDS_EXT) {
+ info->output_dfp2 |= (1 << o);
tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp &= ~RADEON_FP2_BLANK_EN;
tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
@@ -363,6 +374,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
}
} else if (radeon_output->MonType == MT_LCD) {
+ info->output_lcd1 |= (1 << o);
tmp = INREG(RADEON_LVDS_GEN_CNTL);
tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
@@ -372,6 +384,7 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
} else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
+ info->output_tv1 |= (1 << o);
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp |= RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
@@ -382,70 +395,88 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
ErrorF("disable montype: %d\n", radeon_output->MonType);
if (radeon_output->MonType == MT_CRT) {
if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ info->output_crt1 &= ~(1 << o);
+ if (!info->output_crt1) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ }
} else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ info->output_crt2 &= ~(1 << o);
+ if (!info->output_crt2) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ tv_dac_change = 1;
+ }
}
- tv_dac_change = 1;
}
} else if (radeon_output->MonType == MT_DFP) {
if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ info->output_dfp1 &= ~(1 << o);
+ if (!info->output_dfp1) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ }
} else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= RADEON_FP2_BLANK_EN;
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ info->output_dfp2 &= ~(1 << o);
+ if (!info->output_dfp2) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= RADEON_FP2_BLANK_EN;
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ }
}
} else if (radeon_output->MonType == MT_LCD) {
- unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
- if (info->IsMobility || info->IsIGP) {
- /* Asic bug, when turning off LVDS_ON, we have to make sure
- RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
- */
- OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
- }
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- if (info->IsMobility || info->IsIGP) {
- OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ info->output_lcd1 &= ~(1 << o);
+ if (!info->output_lcd1) {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
}
} else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
- tmp = INREG(RADEON_TV_MASTER_CNTL);
- tmp &= ~RADEON_TV_ON;
- OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
- radeon_output->tv_on = FALSE;
+ info->output_tv1 &= ~(1 << o);
+ if (!info->output_tv1) {
+ tmp = INREG(RADEON_TV_MASTER_CNTL);
+ tmp &= ~RADEON_TV_ON;
+ OUTREG(RADEON_TV_MASTER_CNTL, tmp);
+ tv_dac_change = 2;
+ radeon_output->tv_on = FALSE;
+ }
}
}
if (tv_dac_change) {
if (bEnable)
- info->tv_dac_enable_mask |= tv_dac_change;
+ info->tv_dac_enable_mask |= tv_dac_change;
else
- info->tv_dac_enable_mask &= ~tv_dac_change;
+ info->tv_dac_enable_mask &= ~tv_dac_change;
if (bEnable && info->tv_dac_enable_mask)
RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 9e73c08..c60ece8 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -3207,6 +3207,14 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
}
}
+ /* clear the enable masks */
+ info->output_crt1 = 0;
+ info->output_crt2 = 0;
+ info->output_dfp1 = 0;
+ info->output_dfp2 = 0;
+ info->output_lcd1 = 0;
+ info->output_tv1 = 0;
+
for (i = 0 ; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
if (info->BiosConnector[i].valid) {
RADEONOutputPrivatePtr radeon_output = xnfcalloc(sizeof(RADEONOutputPrivateRec), 1);
commit 5c5d2d19b2b032a06dd333b4ecc029aac342fb93
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:15:55 2007 -0500
RADEON: whitespace clean-ups
diff --git a/src/radeon_display.c b/src/radeon_display.c
index 999d349..9437ef4 100644
--- a/src/radeon_display.c
+++ b/src/radeon_display.c
@@ -163,7 +163,7 @@ void RADEONGetTVDacAdjInfo(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONOutputPrivatePtr radeon_output = output->driver_private;
-
+
/* Todo: get this setting from BIOS */
radeon_output->tv_dac_adj = default_tvdac_adj[info->ChipFamily];
if (info->IsMobility) { /* some mobility chips may different */
@@ -202,7 +202,7 @@ static void RADEONDacPowerSet(ScrnInfoPtr pScrn, Bool IsOn, Bool IsPrimaryDAC)
} else {
CARD32 tv_dac_cntl;
CARD32 fp2_gen_cntl;
-
+
switch(info->ChipFamily)
{
case CHIP_FAMILY_R420:
@@ -259,19 +259,19 @@ void RADEONDisableDisplays(ScrnInfoPtr pScrn) {
/* primary DAC */
tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
+ tmp &= ~RADEON_CRTC_CRT_ON;
OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
RADEONDacPowerSet(pScrn, FALSE, TRUE);
/* Secondary DAC */
if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
} else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
}
RADEONDacPowerSet(pScrn, FALSE, FALSE);
@@ -327,95 +327,95 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
if (bEnable) {
ErrorF("enable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp |= RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp |= RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp |= RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp |= RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+ }
+ tv_dac_change = 1;
+ }
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp &= ~RADEON_FP2_BLANK_EN;
- tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ tmp |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
save->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
+ }
+ } else if (radeon_output->MonType == MT_LCD) {
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ tmp &= ~(RADEON_LVDS_DISPLAY_DIS);
usleep (radeon_output->PanelPwrDly * 1000);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
- } else if (radeon_output->MonType == MT_STV ||
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
+ } else if (radeon_output->MonType == MT_STV ||
radeon_output->MonType == MT_CTV) {
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp |= RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
+ tv_dac_change = 2;
radeon_output->tv_on = TRUE;
}
} else {
ErrorF("disable montype: %d\n", radeon_output->MonType);
- if (radeon_output->MonType == MT_CRT) {
- if (radeon_output->DACType == DAC_PRIMARY) {
- tmp = INREG(RADEON_CRTC_EXT_CNTL);
- tmp &= ~RADEON_CRTC_CRT_ON;
- OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
- save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
- RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
- } else if (radeon_output->DACType == DAC_TVDAC) {
- if (info->ChipFamily == CHIP_FAMILY_R200) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- } else {
- tmp = INREG(RADEON_CRTC2_GEN_CNTL);
- tmp &= ~RADEON_CRTC2_CRT2_ON;
- OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
- save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
- }
- tv_dac_change = 1;
- }
- } else if (radeon_output->MonType == MT_DFP) {
- if (radeon_output->TMDSType == TMDS_INT) {
- tmp = INREG(RADEON_FP_GEN_CNTL);
- tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- OUTREG(RADEON_FP_GEN_CNTL, tmp);
- save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
- } else if (radeon_output->TMDSType == TMDS_EXT) {
- tmp = INREG(RADEON_FP2_GEN_CNTL);
+ if (radeon_output->MonType == MT_CRT) {
+ if (radeon_output->DACType == DAC_PRIMARY) {
+ tmp = INREG(RADEON_CRTC_EXT_CNTL);
+ tmp &= ~RADEON_CRTC_CRT_ON;
+ OUTREG(RADEON_CRTC_EXT_CNTL, tmp);
+ save->crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+ RADEONDacPowerSet(pScrn, bEnable, (radeon_output->DACType == DAC_PRIMARY));
+ } else if (radeon_output->DACType == DAC_TVDAC) {
+ if (info->ChipFamily == CHIP_FAMILY_R200) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ } else {
+ tmp = INREG(RADEON_CRTC2_GEN_CNTL);
+ tmp &= ~RADEON_CRTC2_CRT2_ON;
+ OUTREG(RADEON_CRTC2_GEN_CNTL, tmp);
+ save->crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ }
+ tv_dac_change = 1;
+ }
+ } else if (radeon_output->MonType == MT_DFP) {
+ if (radeon_output->TMDSType == TMDS_INT) {
+ tmp = INREG(RADEON_FP_GEN_CNTL);
+ tmp &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ OUTREG(RADEON_FP_GEN_CNTL, tmp);
+ save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+ } else if (radeon_output->TMDSType == TMDS_EXT) {
+ tmp = INREG(RADEON_FP2_GEN_CNTL);
tmp |= RADEON_FP2_BLANK_EN;
- tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- OUTREG(RADEON_FP2_GEN_CNTL, tmp);
- save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
- save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
- }
- } else if (radeon_output->MonType == MT_LCD) {
+ tmp &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ OUTREG(RADEON_FP2_GEN_CNTL, tmp);
+ save->fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+ save->fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+ }
+ } else if (radeon_output->MonType == MT_LCD) {
unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
if (info->IsMobility || info->IsIGP) {
/* Asic bug, when turning off LVDS_ON, we have to make sure
@@ -423,20 +423,20 @@ void RADEONEnableDisplay(xf86OutputPtr output, BOOL bEnable)
*/
OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
}
- tmp = INREG(RADEON_LVDS_GEN_CNTL);
- tmp |= RADEON_LVDS_DISPLAY_DIS;
- tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
- OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
- save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
- save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ tmp = INREG(RADEON_LVDS_GEN_CNTL);
+ tmp |= RADEON_LVDS_DISPLAY_DIS;
+ tmp &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
+ OUTREG(RADEON_LVDS_GEN_CNTL, tmp);
+ save->lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN);
if (info->IsMobility || info->IsIGP) {
OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
}
- } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
+ } else if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) {
tmp = INREG(RADEON_TV_MASTER_CNTL);
tmp &= ~RADEON_TV_ON;
OUTREG(RADEON_TV_MASTER_CNTL, tmp);
- tv_dac_change = 2;
+ tv_dac_change = 2;
radeon_output->tv_on = FALSE;
}
}
@@ -487,13 +487,13 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
int stop_req, max_stop_req;
float read_return_rate, time_disp1_drop_priority;
- /*
- * Set display0/1 priority up on r3/4xx in the memory controller for
- * high res modes if the user specifies HIGH for displaypriority
+ /*
+ * Set display0/1 priority up on r3/4xx in the memory controller for
+ * high res modes if the user specifies HIGH for displaypriority
* option.
*/
if ((info->DispPriority == 2) && IS_R300_VARIANT) {
- CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
+ CARD32 mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
if (pRADEONEnt->pCrtc[1]->enabled) {
mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */
} else {
@@ -522,14 +522,14 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
peak_disp_bw += (pix_clk2 * pixel_bytes2);
if (peak_disp_bw >= mem_bw * min_mem_eff) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"You may not have enough display bandwidth for current mode\n"
"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
- }
+ }
/* CRTC1
Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
+ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
*/
stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
@@ -540,7 +540,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
max_stop_req = 0x7c;
if (stop_req > max_stop_req)
stop_req = max_stop_req;
-
+
/* Get values from the EXT_MEM_CNTL register...converting its contents. */
temp = INREG(RADEON_MEM_TIMING_CNTL);
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
@@ -552,8 +552,8 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
}
-
- /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
+
+ /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
data = (temp & (7<<20)) >> 20;
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */
@@ -625,7 +625,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
}
mc_latency_sclk = sclk_delay / sclk_eff;
-
+
if (info->IsDDR) {
if (info->RamWidth == 32) {
k1 = 40;
@@ -667,7 +667,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
/*
Find the critical point of the display buffer.
*/
- critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
+ critical_point= (CARD32)(disp_drain_rate * disp_latency + 0.5);
/* ???? */
/*
@@ -682,7 +682,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
The critical point should never be above max_stop_req-4. Setting
GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
*/
- if (max_stop_req - critical_point < 4) critical_point = 0;
+ if (max_stop_req - critical_point < 4) critical_point = 0;
if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
@@ -733,7 +733,7 @@ void RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_b
RADEON_GRPH_CRITICAL_AT_SOF |
RADEON_GRPH_STOP_CNTL);
- if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
(info->ChipFamily == CHIP_FAMILY_RS200))
critical_point2 = 0;
else {
@@ -810,7 +810,7 @@ void RADEONBlank(ScrnInfoPtr pScrn)
for (c = 0; c < xf86_config->num_crtc; c++) {
crtc = xf86_config->crtc[c];
- for (o = 0; o < xf86_config->num_output; o++) {
+ for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
@@ -833,7 +833,7 @@ void RADEONUnblank(ScrnInfoPtr pScrn)
if(!crtc->enabled)
continue;
crtc->funcs->dpms(crtc, DPMSModeOn);
- for (o = 0; o < xf86_config->num_output; o++) {
+ for (o = 0; o < xf86_config->num_output; o++) {
output = xf86_config->output[o];
if (output->crtc != crtc)
continue;
commit 9f1d8220315c8894a17f2cc328025dc682b0c6e0
Author: Alex Deucher <alex@t41p.hsd1.va.comcast.net>
Date: Mon Dec 17 18:04:05 2007 -0500
RADEON: more PLL fixes
- reduce the calculation accuracy
- certain LVDS panels seem to only like certain ref_divs
- add pll flags to handle special cases
- adjust the pll limits on legacy cards
diff --git a/src/radeon.h b/src/radeon.h
index 960266e..67315a2 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -366,6 +366,10 @@ typedef struct {
} RADEONSaveRec, *RADEONSavePtr;
+#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
+#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
+#define RADEON_PLL_USE_REF_DIV (1 << 2)
+
typedef struct {
CARD16 reference_freq;
CARD16 reference_div;
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index ebb8c52..41375da 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -606,7 +606,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save,
}
-static CARD32 RADEONDiv64(CARD64 n, CARD32 d)
+static int RADEONDiv(int n, int d)
{
return (n + (d / 2)) / d;
}
@@ -617,12 +617,15 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 *chosen_dot_clock_freq,
CARD32 *chosen_feedback_div,
CARD32 *chosen_reference_div,
- CARD32 *chosen_post_div)
+ CARD32 *chosen_post_div,
+ int flags)
{
int post_divs[] = {1, 2, 4, 8, 3, 6, 12, 0};
int i;
+ CARD32 min_ref_div = pll->min_ref_div;
+ CARD32 max_ref_div = pll->max_ref_div;
CARD32 best_vco = pll->best_vco;
CARD32 best_post_div = 1;
CARD32 best_ref_div = 1;
@@ -631,38 +634,46 @@ RADEONComputePLL(RADEONPLLPtr pll,
CARD32 best_error = 0xffffffff;
CARD32 best_vco_diff = 1;
+ freq = freq / 10;
+
ErrorF("freq: %lu\n", freq);
+ if (flags & RADEON_PLL_USE_REF_DIV)
+ min_ref_div = max_ref_div = pll->reference_div;
+
for (i = 0; post_divs[i]; i++) {
int post_div = post_divs[i];
CARD32 ref_div;
- CARD32 vco = (freq / 10000) * post_div;
+ CARD32 vco = freq * post_div;
+
+ if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+ continue;
if (vco < pll->min_pll_freq || vco > pll->max_pll_freq)
continue;
- for (ref_div = pll->min_ref_div; ref_div <= pll->max_ref_div; ++ref_div) {
+ for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
CARD32 feedback_div, current_freq, error, vco_diff;
CARD32 pll_in = pll->reference_freq / ref_div;
if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
continue;
- feedback_div = RADEONDiv64((CARD64)freq * ref_div * post_div,
- pll->reference_freq * 10000);
+ feedback_div = RADEONDiv(freq * ref_div * post_div,
+ pll->reference_freq);
if (feedback_div < pll->min_feedback_div || feedback_div > pll->max_feedback_div)
continue;
- current_freq = RADEONDiv64((CARD64)pll->reference_freq * 10000 * feedback_div,
- ref_div * post_div);
+ current_freq = RADEONDiv(pll->reference_freq * feedback_div,
+ ref_div * post_div);
error = abs(current_freq - freq);
vco_diff = abs(vco - best_vco);
if ((best_vco == 0 && error < best_error) ||
(best_vco != 0 &&
- (error < best_error - 100 ||
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