xserver-xorg-video-i810: Changes to 'upstream-experimental'
configure.ac | 2
src/common.h | 1
src/i830.h | 1
src/i830_debug.c | 13 ++----
src/i830_display.c | 103 +++++++++++++++++++++++++++++----------------------
src/i830_dri.c | 10 ++++
src/i830_i2c.c | 1
src/i830_lvds.c | 8 ---
src/i830_memory.c | 2
src/i830_sdvo.c | 84 ++++++++++++++++++++++++++++++++++++-----
src/i830_sdvo_regs.h | 8 +++
11 files changed, 163 insertions(+), 70 deletions(-)
New commits:
commit 9fbef2de9edbbed9c2f6a80c4074b9b245547c45
Author: Eric Anholt <eric@anholt.net>
Date: Wed Mar 14 12:34:34 2007 -0700
Bump to 1.9.92 for RC2.
diff --git a/configure.ac b/configure.ac
index 52cc07b..451179d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@ # Process this file with autoconf to pro
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 1.9.91,
+ 1.9.92,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
commit 555b801a75cafa082808bc9bb683e700fc97d79a
Author: Michel Dänzer <michel@tungstengraphics.com>
Date: Wed Mar 14 11:41:50 2007 +0100
Make sure the legacy texture area is there when needed.
This currently only matters when the DRM memory manager is not available and
Option "Legacy3D" "off" is specified, but that hasn't always been the case and
might change again in the future.
diff --git a/src/i830.h b/src/i830.h
index dc8041c..d4be403 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -591,6 +591,7 @@ void i830_free_3d_memory(ScrnInfoPtr pSc
void i830_free_memory(ScrnInfoPtr pScrn, i830_memory *mem);
extern long I830CheckAvailableMemory(ScrnInfoPtr pScrn);
Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn);
+Bool i830_allocate_texture_memory(ScrnInfoPtr pScrn);
Bool i830_allocate_3d_memory(ScrnInfoPtr pScrn);
extern Bool I830IsPrimary(ScrnInfoPtr pScrn);
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 8fae4b7..b24c839 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -702,6 +702,16 @@ #define REQ_MIN 1
i830_free_memory(pScrn, pI830->memory_manager);
pI830->memory_manager = NULL;
+
+ if (!(pI830->mmModeFlags & I830_KERNEL_TEX)) {
+ pI830->mmModeFlags |= I830_KERNEL_TEX;
+
+ if (!i830_allocate_texture_memory(pScrn)) {
+ I830DRICloseScreen(pScreen);
+ drmFreeVersion(version);
+ return FALSE;
+ }
+ }
}
}
#ifdef DAMAGE
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 0742d8c..a20e743 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -1156,7 +1156,7 @@ i830_allocate_depthbuffer(ScrnInfoPtr pS
return TRUE;
}
-static Bool
+Bool
i830_allocate_texture_memory(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
commit 66fdb08c83d353fbe4e917900c54b555c869eb80
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 17:07:10 2007 -0700
Refine the i855 LVDS clock code. In particular, p2 is always 14.
This gets correct clocks detected on most harware. The SSC is always assumed
to be 66Mhz, which may not be true, but we'll fix that when we find example
hardware.
diff --git a/src/i830_debug.c b/src/i830_debug.c
index dccaa7e..7fd9441 100644
--- a/src/i830_debug.c
+++ b/src/i830_debug.c
@@ -187,25 +187,24 @@ DEBUGSTRING(i830_debug_dpll)
} else {
Bool is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
- if (val & PLL_P2_DIVIDE_BY_4)
- p2 = 4;
- else
- p2 = 2;
-
if (is_lvds) {
mode = "LVDS";
- /* Map the bit number set from (1, 6) to (-1, 4). */
p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
DPLL_FPA01_P1_POST_DIV_SHIFT);
+ p2 = 14;
} else {
mode = "DAC/serial";
if (val & PLL_P1_DIVIDE_BY_TWO) {
p1 = 2;
} else {
- /* Map the number in the field to (1, 31) */
+ /* Map the number in the field to (3, 33) */
p1 = ((val & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
}
+ if (val & PLL_P2_DIVIDE_BY_4)
+ p2 = 4;
+ else
+ p2 = 2;
}
}
diff --git a/src/i830_display.c b/src/i830_display.c
index a5d8df8..6e64961 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -85,15 +85,14 @@ #define I8XX_M2_MIN 6
#define I8XX_M2_MAX 16
#define I8XX_P_MIN 4
#define I8XX_P_MAX 128
-/* LVDS p1 value can go from 1 to 6, while DAC goes from 2 to 33. These
- * values below get 2 added in the clock calculations.
- */
-#define I8XX_P1_MIN 0
-#define I8XX_P1_MAX 31
-#define I8XX_P1_LVDS_MIN -1
-#define I8XX_P1_LVDS_MAX 4
-#define I8XX_P2_SLOW 1 /* this is a bit shift amount */
-#define I8XX_P2_FAST 0 /* this is a bit shift amount */
+#define I8XX_P1_MIN 2
+#define I8XX_P1_MAX 33
+#define I8XX_P1_LVDS_MIN 1
+#define I8XX_P1_LVDS_MAX 6
+#define I8XX_P2_SLOW 4
+#define I8XX_P2_FAST 2
+#define I8XX_P2_LVDS_SLOW 14
+#define I8XX_P2_LVDS_FAST 14 /* No fast option */
#define I8XX_P2_SLOW_LIMIT 165000
#define I9XX_DOT_MIN 20000
@@ -149,7 +148,7 @@ static const intel_limit_t intel_limits[
.p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
.p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
.p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
- .p2_slow = I8XX_P2_FAST, .p2_fast = I8XX_P2_FAST },
+ .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
},
{ /* INTEL_LIMIT_I9XX_SDVO_DAC */
.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
@@ -206,7 +205,7 @@ static const intel_limit_t *intel_limit
static void i8xx_clock(int refclk, intel_clock_t *clock)
{
clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
- clock->p = (clock->p1 + 2) << (clock->p2 + 1);
+ clock->p = clock->p1 * clock->p2;
clock->vco = refclk * clock->m / (clock->n + 2);
clock->dot = clock->vco / clock->p;
}
@@ -797,15 +796,15 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, Dis
dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
} else {
if (is_lvds) {
- /* map (-1 to 4) to ((1 << 0) to (1 << 5)). */
- dpll |= (1 << (clock.p1 + 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
} else {
- if (clock.p1 == 0)
+ if (clock.p1 == 2)
dpll |= PLL_P1_DIVIDE_BY_TWO;
else
- dpll |= clock.p1 << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ if (clock.p2 == 4)
+ dpll |= PLL_P2_DIVIDE_BY_4;
}
- dpll |= clock.p2 << 23;
}
if (is_tv)
@@ -1255,26 +1254,28 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, x
Bool is_lvds = (pipe == 1) && (INREG(LVDS) & LVDS_PORT_EN);
if (is_lvds) {
- /* Map the bit number set from (1, 6) to (-1, 4). */
clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT) - 2;
- clock.p2 = 0;
+ DPLL_FPA01_P1_POST_DIV_SHIFT);
+ clock.p2 = 14;
+
+ if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
+ i8xx_clock(66000, &clock); /* XXX: might not be 66MHz */
+ else
+ i8xx_clock(48000, &clock);
} else {
if (dpll & PLL_P1_DIVIDE_BY_TWO) {
- clock.p1 = 0;
+ clock.p1 = 2;
} else {
- /* Map the number in the field to (1, 31) */
clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
- DPLL_FPA01_P1_POST_DIV_SHIFT);
+ DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
}
if (dpll & PLL_P2_DIVIDE_BY_4)
- clock.p2 = 1;
+ clock.p2 = 4;
else
- clock.p2 = 0;
- }
+ clock.p2 = 2;
- /* XXX: Deal with other refclocks */
- i8xx_clock(48000, &clock);
+ i8xx_clock(48000, &clock);
+ }
}
/* XXX: It would be nice to validate the clocks, but we can't reuse
commit 44708bdd9ebfef0328302c9a964b80deb46e57c6
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 16:55:38 2007 -0700
Get SDVO DPMS working on the Mac Mini by writing SDVOB and SDVOC together.
Also, add code for setting the encoder power state like the BIOS does, but this
doesn't appear to work. We do much more than the BIOS does in powering things
down, so perhaps that's interfering somehow.
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index cd0b115..fb6a7c8 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -79,6 +79,25 @@ struct i830_sdvo_priv {
/** @} */
};
+/**
+ * Writes the SDVOB or SDVOC with the given value, but always writes both
+ * SDVOB and SDVOC to work around apparent hardware issues (according to
+ * comments in the BIOS).
+ */
+static void i830_sdvo_write_sdvox(xf86OutputPtr output, CARD32 val)
+{
+ ScrnInfoPtr pScrn = output->scrn;
+ I830OutputPrivatePtr intel_output = output->driver_private;
+ struct i830_sdvo_priv *dev_priv = intel_output->dev_priv;
+ I830Ptr pI830 = I830PTR(pScrn);
+
+ if (dev_priv->output_device == SDVOC)
+ OUTREG(SDVOB, INREG(SDVOB));
+ OUTREG(dev_priv->output_device, val);
+ if (dev_priv->output_device == SDVOB)
+ OUTREG(SDVOC, INREG(SDVOC));
+}
+
/** Read a single byte from the given address on the SDVO device. */
static Bool i830_sdvo_read_byte(xf86OutputPtr output, int addr,
unsigned char *ch)
@@ -163,6 +182,9 @@ const static struct _sdvo_cmd_name {
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
+ SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
+ SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODER_POWER_STATE),
+ SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_RESOLUTION_SUPPORT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
};
@@ -346,6 +368,34 @@ i830_sdvo_set_active_outputs(xf86OutputP
return (status == SDVO_CMD_STATUS_SUCCESS);
}
+static Bool
+i830_sdvo_set_encoder_power_state(xf86OutputPtr output, int mode)
+{
+ CARD8 status;
+ CARD8 state;
+
+ switch (mode) {
+ case DPMSModeOn:
+ state = SDVO_ENCODER_STATE_ON;
+ break;
+ case DPMSModeStandby:
+ state = SDVO_ENCODER_STATE_STANDBY;
+ break;
+ case DPMSModeSuspend:
+ state = SDVO_ENCODER_STATE_SUSPEND;
+ break;
+ case DPMSModeOff:
+ state = SDVO_ENCODER_STATE_OFF;
+ break;
+ }
+
+ i830_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
+ sizeof(state));
+ status = i830_sdvo_read_response(output, NULL, 0);
+
+ return (status == SDVO_CMD_STATUS_SUCCESS);
+}
+
/**
* Returns the pixel clock range limits of the current target input in kHz.
*/
@@ -669,7 +719,7 @@ #endif
sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
}
- OUTREG(dev_priv->output_device, sdvox);
+ i830_sdvo_write_sdvox(output, sdvox);
}
static void
@@ -683,9 +733,16 @@ i830_sdvo_dpms(xf86OutputPtr output, int
if (mode != DPMSModeOn) {
i830_sdvo_set_active_outputs(output, 0);
- temp = INREG(dev_priv->output_device);
- if ((temp & SDVO_ENABLE) != 0)
- OUTREG(dev_priv->output_device, temp & ~SDVO_ENABLE);
+ if (0)
+ i830_sdvo_set_encoder_power_state(output, mode);
+
+ if (mode == DPMSModeOff) {
+ temp = INREG(dev_priv->output_device);
+ if ((temp & SDVO_ENABLE) != 0) {
+ i830_sdvo_write_sdvox(output, temp & ~SDVO_ENABLE);
+ POSTING_READ(dev_priv->output_device);
+ }
+ }
} else {
Bool input1, input2;
int i;
@@ -694,14 +751,15 @@ i830_sdvo_dpms(xf86OutputPtr output, int
temp = INREG(dev_priv->output_device);
if ((temp & SDVO_ENABLE) == 0)
{
- OUTREG(dev_priv->output_device, temp | SDVO_ENABLE);
+ i830_sdvo_write_sdvox(output, temp | SDVO_ENABLE);
POSTING_READ(dev_priv->output_device);
#if 0
- /* Do it again! If we remove this below register write, or the exact
- * same one 2 lines up, the mac mini SDVO output doesn't turn on.
+ /* Do it again! If we remove this below register write, or the
+ * exact same one 2 lines up, the mac mini SDVO output doesn't
+ * turn on.
*/
- OUTREG(dev_priv->output_device,
- INREG(dev_priv->output_device) | SDVO_ENABLE);
+ i830_sdvo_write_sdvox(output, INREG(dev_priv->output_device) |
+ SDVO_ENABLE);
POSTING_READ(dev_priv->output_device);
#endif
}
@@ -717,6 +775,8 @@ #endif
SDVO_NAME(dev_priv));
}
+ if (0)
+ i830_sdvo_set_encoder_power_state(output, mode);
i830_sdvo_set_active_outputs(output, dev_priv->active_outputs);
}
}
@@ -764,7 +824,6 @@ i830_sdvo_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_sdvo_priv *dev_priv = intel_output->dev_priv;
- I830Ptr pI830 = I830PTR(pScrn);
int o;
int i;
Bool input1, input2;
@@ -794,7 +853,7 @@ i830_sdvo_restore(xf86OutputPtr output)
i830_sdvo_set_clock_rate_mult(output, dev_priv->save_sdvo_mult);
- OUTREG(dev_priv->output_device, dev_priv->save_SDVOX);
+ i830_sdvo_write_sdvox(output, dev_priv->save_SDVOX);
if (dev_priv->save_SDVOX & SDVO_ENABLE)
{
diff --git a/src/i830_sdvo_regs.h b/src/i830_sdvo_regs.h
index 59b2aa8..437ff50 100644
--- a/src/i830_sdvo_regs.h
+++ b/src/i830_sdvo_regs.h
@@ -307,6 +307,14 @@ #define SDVO_CMD_GET_TV_FORMAT 0x28
#define SDVO_CMD_SET_TV_FORMAT 0x29
+#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
+#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b
+#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
+# define SDVO_ENCODER_STATE_ON (1 << 0)
+# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
+# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
+# define SDVO_ENCODER_STATE_OFF (1 << 3)
+
#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93
#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
commit 5135b3a79f9c30ebce78c84c49846bba83607fed
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 10:21:06 2007 -0700
Use a POSTING_READ(reg) macro instead of using the (void)INREG(reg) pattern.
diff --git a/src/common.h b/src/common.h
index f596eb8..a634895 100644
--- a/src/common.h
+++ b/src/common.h
@@ -233,6 +233,7 @@ #define BEGIN_LP_RING(n) \
#define INREG8(addr) *(volatile CARD8 *)(RecPtr->MMIOBase + (addr))
#define INREG16(addr) *(volatile CARD16 *)(RecPtr->MMIOBase + (addr))
#define INREG(addr) *(volatile CARD32 *)(RecPtr->MMIOBase + (addr))
+#define POSTING_READ(addr) (void)INREG(addr)
#define OUTREG8(addr, val) do { \
*(volatile CARD8 *)(RecPtr->MMIOBase + (addr)) = (val); \
diff --git a/src/i830_display.c b/src/i830_display.c
index e5390b3..a5d8df8 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -383,12 +383,12 @@ i830PipeSetBase(xf86CrtcPtr crtc, int x,
if (IS_I965G(pI830)) {
OUTREG(dspbase, Offset);
- (void) INREG(dspbase);
+ POSTING_READ(dspbase);
OUTREG(dspsurf, Start);
- (void) INREG(dspsurf);
+ POSTING_READ(dspsurf);
} else {
OUTREG(dspbase, Start + Offset);
- (void) INREG(dspbase);
+ POSTING_READ(dspbase);
}
#ifdef XF86DRI
@@ -447,15 +447,15 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
if ((temp & DPLL_VCO_ENABLE) == 0)
{
OUTREG(dpll_reg, temp);
- (void)INREG(dpll_reg);
+ POSTING_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
- (void)INREG(dpll_reg);
+ POSTING_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
- (void)INREG(dpll_reg);
+ POSTING_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
}
@@ -493,7 +493,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
OUTREG(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
OUTREG(dspbase_reg, INREG(dspbase_reg));
- (void)INREG(dspbase_reg);
+ POSTING_READ(dspbase_reg);
}
if (!IS_I9XX(pI830)) {
@@ -505,7 +505,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
temp = INREG(pipeconf_reg);
if ((temp & PIPEACONF_ENABLE) != 0) {
OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
- (void)INREG(pipeconf_reg);
+ POSTING_READ(pipeconf_reg);
}
/* Wait for vblank for the disable to take effect. */
@@ -514,7 +514,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
temp = INREG(dpll_reg);
if ((temp & DPLL_VCO_ENABLE) != 0) {
OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
- (void)INREG(dpll_reg);
+ POSTING_READ(dpll_reg);
}
/* Wait for the clocks to turn off. */
@@ -876,7 +876,7 @@ #endif
{
OUTREG(fp_reg, fp);
OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
- (void)INREG(dpll_reg);
+ POSTING_READ(dpll_reg);
usleep(150);
}
@@ -887,12 +887,12 @@ #endif
* things on.
*/
OUTREG(LVDS, INREG(LVDS) | LVDS_PORT_EN | LVDS_PIPEB_SELECT);
- (void)INREG(LVDS);
+ POSTING_READ(LVDS);
}
OUTREG(fp_reg, fp);
OUTREG(dpll_reg, dpll);
- (void)INREG(dpll_reg);
+ POSTING_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
@@ -904,7 +904,7 @@ #endif
/* write it again -- the BIOS does, after all */
OUTREG(dpll_reg, dpll);
}
- (void)INREG(dpll_reg);
+ POSTING_READ(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
@@ -928,7 +928,7 @@ #endif
OUTREG(dsppos_reg, 0);
OUTREG(pipesrc_reg, ((mode->HDisplay - 1) << 16) | (mode->VDisplay - 1));
OUTREG(pipeconf_reg, pipeconf);
- (void)INREG(pipeconf_reg);
+ POSTING_READ(pipeconf_reg);
i830WaitForVblank(pScrn);
OUTREG(dspcntr_reg, dspcntr);
diff --git a/src/i830_i2c.c b/src/i830_i2c.c
index 7fac63c..319e8da 100644
--- a/src/i830_i2c.c
+++ b/src/i830_i2c.c
@@ -336,7 +336,7 @@ #endif
clock_bits = GPIO_CLOCK_DIR_OUT|GPIO_CLOCK_DIR_MASK|GPIO_CLOCK_VAL_MASK;
OUTREG(b->DriverPrivate.uval, reserved | data_bits | clock_bits);
- (void)INREG(b->DriverPrivate.uval);
+ POSTING_READ(b->DriverPrivate.uval);
}
#endif
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index 4c543db..cd0b115 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -695,14 +695,14 @@ i830_sdvo_dpms(xf86OutputPtr output, int
if ((temp & SDVO_ENABLE) == 0)
{
OUTREG(dev_priv->output_device, temp | SDVO_ENABLE);
- (void)INREG(dev_priv->output_device);
+ POSTING_READ(dev_priv->output_device);
#if 0
/* Do it again! If we remove this below register write, or the exact
* same one 2 lines up, the mac mini SDVO output doesn't turn on.
*/
OUTREG(dev_priv->output_device,
INREG(dev_priv->output_device) | SDVO_ENABLE);
- (void)INREG(dev_priv->output_device);
+ POSTING_READ(dev_priv->output_device);
#endif
}
for (i = 0; i < 2; i++)
commit 578da7ca705c5a58c0bd397b0831e2f95140f8ae
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 10:11:29 2007 -0700
Add PCI write posting protection to i2c putbits.
diff --git a/src/i830_i2c.c b/src/i830_i2c.c
index 450f9de..7fac63c 100644
--- a/src/i830_i2c.c
+++ b/src/i830_i2c.c
@@ -336,6 +336,7 @@ #endif
clock_bits = GPIO_CLOCK_DIR_OUT|GPIO_CLOCK_DIR_MASK|GPIO_CLOCK_VAL_MASK;
OUTREG(b->DriverPrivate.uval, reserved | data_bits | clock_bits);
+ (void)INREG(b->DriverPrivate.uval);
}
#endif
commit cf33abe43bd95c9437fad8e6201a24084ff96cb8
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 10:08:57 2007 -0700
Add write posting protection for the SDVO DPMS-on path.
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index a3db517..4c543db 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -695,12 +695,14 @@ i830_sdvo_dpms(xf86OutputPtr output, int
if ((temp & SDVO_ENABLE) == 0)
{
OUTREG(dev_priv->output_device, temp | SDVO_ENABLE);
+ (void)INREG(dev_priv->output_device);
#if 0
/* Do it again! If we remove this below register write, or the exact
* same one 2 lines up, the mac mini SDVO output doesn't turn on.
*/
OUTREG(dev_priv->output_device,
INREG(dev_priv->output_device) | SDVO_ENABLE);
+ (void)INREG(dev_priv->output_device);
#endif
}
for (i = 0; i < 2; i++)
commit 9d30f0007203157e6b82fa0ffc57324490eb2ca0
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 10:04:06 2007 -0700
Replace #if 0ed LVDS register setting with updated comment.
diff --git a/src/i830_lvds.c b/src/i830_lvds.c
index f554b38..adfbe4f 100644
--- a/src/i830_lvds.c
+++ b/src/i830_lvds.c
@@ -225,13 +225,9 @@ i830_lvds_mode_set(xf86OutputPtr output,
I830Ptr pI830 = I830PTR(pScrn);
CARD32 pfit_control;
-#if 0
- /* The LVDS pin pair needs to be on before the DPLLs are enabled.
- * This is an exception to the general rule that mode_set doesn't turn
- * things on.
+ /* The LVDS pin pair will already have been turned on in the
+ * i830_crtc_mode_set since it has a large impact on the DPLL settings.
*/
- OUTREG(LVDS, INREG(LVDS) | LVDS_PORT_EN | LVDS_PIPEB_SELECT);
-#endif
/* Enable automatic panel scaling so that non-native modes fill the
* screen. Should be enabled before the pipe is enabled, according to
commit 9c17c6e9c63563cad5edff837519a73fe0afe313
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 09:55:49 2007 -0700
Add write posting protections to relevant register writes in the mode-set path.
diff --git a/src/i830_display.c b/src/i830_display.c
index d230f74..e5390b3 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -447,12 +447,15 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
if ((temp & DPLL_VCO_ENABLE) == 0)
{
OUTREG(dpll_reg, temp);
+ (void)INREG(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
+ (void)INREG(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
+ (void)INREG(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
}
@@ -490,6 +493,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
OUTREG(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
/* Flush the plane changes */
OUTREG(dspbase_reg, INREG(dspbase_reg));
+ (void)INREG(dspbase_reg);
}
if (!IS_I9XX(pI830)) {
@@ -499,15 +503,19 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mod
/* Next, disable display pipes */
temp = INREG(pipeconf_reg);
- if ((temp & PIPEACONF_ENABLE) != 0)
+ if ((temp & PIPEACONF_ENABLE) != 0) {
OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
+ (void)INREG(pipeconf_reg);
+ }
/* Wait for vblank for the disable to take effect. */
i830WaitForVblank(pScrn);
temp = INREG(dpll_reg);
- if ((temp & DPLL_VCO_ENABLE) != 0)
+ if ((temp & DPLL_VCO_ENABLE) != 0) {
OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
+ (void)INREG(dpll_reg);
+ }
/* Wait for the clocks to turn off. */
usleep(150);
@@ -856,15 +864,6 @@ #if 1
pipeconf |= PIPEACONF_ENABLE;
dpll |= DPLL_VCO_ENABLE;
#endif
-
- if (is_lvds)
- {
- /* The LVDS pin pair needs to be on before the DPLLs are enabled.
- * This is an exception to the general rule that mode_set doesn't turn
- * things on.
- */
- OUTREG(LVDS, INREG(LVDS) | LVDS_PORT_EN | LVDS_PIPEB_SELECT);
- }
/* Disable the panel fitter if it was on our pipe */
if (i830_panel_fitter_pipe (pI830) == pipe)
@@ -877,10 +876,23 @@ #endif
{
OUTREG(fp_reg, fp);
OUTREG(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+ (void)INREG(dpll_reg);
usleep(150);
}
+
+ if (is_lvds)
+ {
+ /* The LVDS pin pair needs to be on before the DPLLs are enabled.
+ * This is an exception to the general rule that mode_set doesn't turn
+ * things on.
+ */
+ OUTREG(LVDS, INREG(LVDS) | LVDS_PORT_EN | LVDS_PIPEB_SELECT);
+ (void)INREG(LVDS);
+ }
+
OUTREG(fp_reg, fp);
OUTREG(dpll_reg, dpll);
+ (void)INREG(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
@@ -889,9 +901,10 @@ #endif
OUTREG(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
} else {
- /* write it again -- the BIOS does, after all */
- OUTREG(dpll_reg, dpll);
+ /* write it again -- the BIOS does, after all */
+ OUTREG(dpll_reg, dpll);
}
+ (void)INREG(dpll_reg);
/* Wait for the clocks to stabilize. */
usleep(150);
@@ -915,8 +928,9 @@ #endif
OUTREG(dsppos_reg, 0);
OUTREG(pipesrc_reg, ((mode->HDisplay - 1) << 16) | (mode->VDisplay - 1));
OUTREG(pipeconf_reg, pipeconf);
+ (void)INREG(pipeconf_reg);
i830WaitForVblank(pScrn);
-
+
OUTREG(dspcntr_reg, dspcntr);
/* Flush the plane changes */
i830PipeSetBase(crtc, x, y);
commit 2824ec7ccbf44ba413a6133f735f4a548c73b3cd
Author: Eric Anholt <eric@anholt.net>
Date: Tue Mar 13 09:53:35 2007 -0700
Fix uninitialized string use in SDVO non-TMDS case.
diff --git a/src/i830_sdvo.c b/src/i830_sdvo.c
index b7cf843..a3db517 100644
--- a/src/i830_sdvo.c
+++ b/src/i830_sdvo.c
@@ -1205,6 +1205,7 @@ i830_sdvo_init(ScrnInfoPtr pScrn, int ou
"%s: No active TMDS outputs (0x%02x%02x)\n",
SDVO_NAME(dev_priv),
bytes[0], bytes[1]);
+ name_prefix="Unknown";
}
strcpy (name, name_prefix);
strcat (name, name_suffix);
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