X Strike Force X.Org X11 SVN commit: r208 - in trunk/debian: . patches
Author: branden
Date: 2005-06-14 15:04:50 -0500 (Tue, 14 Jun 2005)
New Revision: 208
Removed:
trunk/debian/patches/024a_radeon_benh_fixes.diff
Modified:
trunk/debian/TODO
trunk/debian/changelog
trunk/debian/patches/0000_backport_from_upstream.diff
Log:
Grab patches from upstream CVS HEAD:
- Add radeon(4x) manpage updates documenting VGAAccess, ReverseDDC, and
LVDSProbePLL options. (Benjamin Herrenschmidt)
<URL: https://bugs.freedesktop.org/show_bug.cgi?id=2064 >.
- Add VGAAccess option to r128 driver, based on Benjamin Herrenscmidts's
radeon patch. r128 should now work on PowerPCs without "UseFBDev". To
use this on PowerPC, make sure you set "UseFBDev" to "false".
(Alex Deucher)
<URL: https://bugs.freedesktop.org/show_bug.cgi?id=2089 >.
Move upstream patches in #024a to #0000.
Add TODO item for first experimental release milestone.
NOTE: This commit breaks patch #024b; see the added TODO item.
Modified: trunk/debian/TODO
===================================================================
--- trunk/debian/TODO 2005-06-14 19:46:39 UTC (rev 207)
+++ trunk/debian/TODO 2005-06-14 20:04:50 UTC (rev 208)
@@ -7,6 +7,9 @@
xorg-x11 6.8.2-0pre1v1 (experimental)
-------------------------------------
+* Forward-port patch #024b (patch #024 from Debian xfree86 SVN trunk), which now
+ does not apply cleanly
+
* Document non-freeness of rman (PolyglotMan) in debian/copyright. [branden]
* Trash patch #999 (disable x11perf), revert changes to MANIFESTs and
Modified: trunk/debian/changelog
===================================================================
--- trunk/debian/changelog 2005-06-14 19:46:39 UTC (rev 207)
+++ trunk/debian/changelog 2005-06-14 20:04:50 UTC (rev 208)
@@ -159,8 +159,18 @@
* Update paths to files containg sourceless firmware in debian/copyright.
- -- Branden Robinson <branden@debian.org> Mon, 13 Jun 2005 17:10:37 -0500
+ * Grab patches from upstream CVS HEAD:
+ - Add radeon(4x) manpage updates documenting VGAAccess, ReverseDDC, and
+ LVDSProbePLL options. (Benjamin Herrenschmidt)
+ <URL: https://bugs.freedesktop.org/show_bug.cgi?id=2064 >.
+ - Add VGAAccess option to r128 driver, based on Benjamin Herrenscmidts's
+ radeon patch. r128 should now work on PowerPCs without "UseFBDev". To
+ use this on PowerPC, make sure you set "UseFBDev" to "false".
+ (Alex Deucher)
+ <URL: https://bugs.freedesktop.org/show_bug.cgi?id=2089 >.
+ -- Branden Robinson <branden@debian.org> Tue, 14 Jun 2005 14:52:14 -0500
+
xfree86 (4.3.0.dfsg.1-14) unstable; urgency=high
Urgency set to high due to fix for security flaw (see below).
Modified: trunk/debian/patches/0000_backport_from_upstream.diff
===================================================================
--- trunk/debian/patches/0000_backport_from_upstream.diff 2005-06-14 19:46:39 UTC (rev 207)
+++ trunk/debian/patches/0000_backport_from_upstream.diff 2005-06-14 20:04:50 UTC (rev 208)
@@ -42,6 +42,30 @@
Rename XFree86CustomVersion to XorgCustomVersion in the Debian
Maintainer section.
+2004-12-17 Alex Deucher <agd5f@yahoo.com>
+
+ * programs/Xserver/hw/xfree86/drivers/ati/r128.h:
+ * programs/Xserver/hw/xfree86/drivers/ati/r128.man:
+ * programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c:
+ - Add VGAAccess option to r128 driver. Based on Benh's radeon patch.
+ r128 should now work on ppcs without usefbdev. To use this on ppc
+ make sure you set "usefbdev" to false. (bug 2089)
+
+ * programs/Xserver/hw/xfree86/drivers/ati/radeon.h:
+ * programs/Xserver/hw/xfree86/drivers/ati/radeon.man:
+ * programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c:
+ (RADEONEngineRestore):
+ * programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c:
+ (RADEONProbePLLParameters), (RADEONGetPanelInfoFromReg),
+ (RADEONGetLVDSInfo), (RADEONGetPanelInfo), (RADEONGetClockInfo),
+ (RADEONQueryConnectedMonitors), (RADEONUpdatePanelSize),
+ (RADEONDDCModes), (RADEONValidateDDCModes), (RADEONPreInitModes),
+ (RADEONPreInit), (RADEONSave), (RADEONRestore),
+ (RADEONInitDispBandwidth), (RADEONInitCrtc2Registers),
+ (RADEONInitPLLRegisters), (RADEONInitPLL2Registers), (RADEONInit),
+ (RADEONFreeScreen):
+ - Apply Benjamin Herrenschmidt's radeon patches (bug 2064)
+
2005-01-24 Adam Jackson <ajax@freedesktop.org>
* programs/Xserver/hw/xfree86/i2c/xf86i2c.c:
@@ -88,15 +112,806 @@
* config/cf/linux.cf:
Fix typo that I introduced on 2005-03-06.
+Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c
+===================================================================
+--- xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c (revision 140)
++++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128_driver.c (working copy)
+@@ -137,7 +137,8 @@
+ OPTION_PROG_FP_REGS,
+ OPTION_FBDEV,
+ OPTION_VIDEO_KEY,
+- OPTION_SHOW_CACHE
++ OPTION_SHOW_CACHE,
++ OPTION_VGA_ACCESS
+ } R128Opts;
+
+ static const OptionInfoRec R128Options[] = {
+@@ -164,6 +165,7 @@
+ { OPTION_FBDEV, "UseFBDev", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
+ { OPTION_SHOW_CACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
++ { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE },
+ { -1, NULL, OPTV_NONE, {0}, FALSE }
+ };
+
+@@ -1873,13 +1875,6 @@
+ return TRUE;
+ }
+
+- if (!xf86LoadSubModule(pScrn, "vgahw")) return FALSE;
+- xf86LoaderReqSymLists(vgahwSymbols, NULL);
+- if (!vgaHWGetHWRec(pScrn)) {
+- R128FreeRec(pScrn);
+- return FALSE;
+- }
+-
+ info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index);
+ info->PciTag = pciTag(info->PciInfo->bus,
+ info->PciInfo->device,
+@@ -1906,6 +1901,33 @@
+ memcpy(info->Options, R128Options, sizeof(R128Options));
+ xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
+
++ /* By default, don't do VGA IOs on ppc */
++#ifdef __powerpc__
++ info->VGAAccess = FALSE;
++#else
++ info->VGAAccess = TRUE;
++#endif
++
++ xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess);
++ if (info->VGAAccess) {
++ if (!xf86LoadSubModule(pScrn, "vgahw"))
++ info->VGAAccess = FALSE;
++ else {
++ xf86LoaderReqSymLists(vgahwSymbols, NULL);
++ if (!vgaHWGetHWRec(pScrn))
++ info->VGAAccess = FALSE;
++ }
++ if (!info->VGAAccess)
++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed,"
++ " trying to run without it\n");
++ } else
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE,"
++ " VGA module load skipped\n");
++ if (info->VGAAccess)
++ vgaHWGetIOBase(VGAHWPTR(pScrn));
++
++
++
+ if (!R128PreInitWeight(pScrn)) goto fail;
+
+ if(xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, &(info->videoKey))) {
+@@ -1989,7 +2011,8 @@
+ if (pInt10)
+ xf86FreeInt10(pInt10);
+
+- vgaHWFreeHWRec(pScrn);
++ if (info->VGAAccess)
++ vgaHWFreeHWRec(pScrn);
+ R128FreeRec(pScrn);
+ return FALSE;
+ }
+@@ -2802,17 +2825,31 @@
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+ R128SavePtr save = &info->SavedReg;
+- vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ R128TRACE(("R128Save\n"));
+ if (info->FBDev) {
+ fbdevHWSave(pScrn);
+ return;
+ }
+- vgaHWUnlock(hwp);
+- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); /* save mode, fonts, cmap */
+- vgaHWLock(hwp);
+
++ if (info->VGAAccess) {
++ vgaHWPtr hwp = VGAHWPTR(pScrn);
++
++ vgaHWUnlock(hwp);
++#if defined(__powerpc__)
++ /* temporary hack to prevent crashing on PowerMacs when trying to
++ * read VGA fonts and colormap, will find a better solution
++ * in the future. TODO: Check if there's actually some VGA stuff
++ * setup in the card at all !!
++ */
++ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
++#else
++ /* Save mode * & fonts & cmap */
++ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS);
++#endif
++ vgaHWLock(hwp);
++ }
++
+ R128SaveMode(pScrn, save);
+
+ save->dp_datatype = INREG(R128_DP_DATATYPE);
+@@ -2828,7 +2865,6 @@
+ R128InfoPtr info = R128PTR(pScrn);
+ unsigned char *R128MMIO = info->MMIO;
+ R128SavePtr restore = &info->SavedReg;
+- vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ R128TRACE(("R128Restore\n"));
+ if (info->FBDev) {
+@@ -2844,9 +2880,19 @@
+ OUTREG(R128_DP_DATATYPE, restore->dp_datatype);
+
+ R128RestoreMode(pScrn, restore);
+- vgaHWUnlock(hwp);
+- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
+- vgaHWLock(hwp);
++ if (info->VGAAccess) {
++ vgaHWPtr hwp = VGAHWPTR(pScrn);
++ vgaHWUnlock(hwp);
++#if defined(__powerpc__)
++ /* Temporary hack to prevent crashing on PowerMacs when trying to
++ * write VGA fonts, will find a better solution in the future
++ */
++ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
++#else
++ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
++#endif
++ vgaHWLock(hwp);
++ }
+
+ R128WaitForVerticalSync(pScrn);
+ R128Unblank(pScrn);
+@@ -3579,9 +3625,10 @@
+ void R128FreeScreen(int scrnIndex, int flags)
+ {
+ ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
++ R128InfoPtr info = R128PTR(pScrn);
+
+ R128TRACE(("R128FreeScreen\n"));
+- if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
++ if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
+ vgaHWFreeHWRec(pScrn);
+ R128FreeRec(pScrn);
+ }
Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c
===================================================================
-RCS file: /cvs/xorg/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v
-retrieving revision 1.21
-retrieving revision 1.22
-diff -u -r1.21 -r1.22
---- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 3 Oct 2004 00:01:14 -0000 1.21
-+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 11 Oct 2004 09:58:04 -0000 1.22
-@@ -6482,6 +6482,7 @@
+--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c (revision 140)
++++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c (working copy)
+@@ -165,6 +165,9 @@
+ #endif
+ OPTION_SHOWCACHE,
+ OPTION_DYNAMIC_CLOCKS
++ OPTION_VGA_ACCESS,
++ OPTION_REVERSE_DDC,
++ OPTION_LVDS_PROBE_PLL
+ } RADEONOpts;
+
+ static const OptionInfoRec RADEONOptions[] = {
+@@ -209,6 +212,9 @@
+ #endif
+ { OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
+ { OPTION_DYNAMIC_CLOCKS, "DynamicClocks", OPTV_BOOLEAN, {0}, FALSE },
++ { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE },
++ { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE },
++ { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE },
+ { -1, NULL, OPTV_NONE, {0}, FALSE }
+ };
+
+@@ -1184,41 +1190,59 @@
+ return(bConnected ? MT_CRT : MT_NONE);
+ }
+
+-#if defined(__powerpc__)
+ static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
+ {
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ RADEONPLLPtr pll = &info->pll;
+ unsigned char *RADEONMMIO = info->MMIO;
+ unsigned char ppll_div_sel;
+- unsigned Nx, M;
++ unsigned mpll_fb_div, spll_fb_div, M;
+ unsigned xclk, tmp, ref_div;
+ int hTotal, vTotal, num, denom, m, n;
+- float hz, vclk, xtal;
++ float hz, prev_xtal, vclk, xtal, mpll, spll;
+ long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs;
+- int i;
++ long to1_secs, to1_usecs, to2_secs, to2_usecs;
++ unsigned int f1, f2, f3;
++ int i, tries = 0;
+
+- for(i=0; i<1000000; i++)
+- if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
++ prev_xtal = 0;
++ again:
++ xtal = 0;
++ if (++tries > 10)
++ goto failed;
++
++ xf86getsecs(&to1_secs, &to1_usecs);
++ f1 = INREG(RADEON_CRTC_CRNT_FRAME);
++ for (;;) {
++ f2 = INREG(RADEON_CRTC_CRNT_FRAME);
++ if (f1 != f2)
+ break;
+-
++ xf86getsecs(&to2_secs, &to2_usecs);
++ if ((to2_secs - to1_secs) > 1) {
++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n");
++ goto failed;
++ }
++ }
+ xf86getsecs(&start_secs, &start_usecs);
+-
+- for(i=0; i<1000000; i++)
+- if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
++ for(;;) {
++ f3 = INREG(RADEON_CRTC_CRNT_FRAME);
++ if (f3 != f2)
+ break;
+-
+- for(i=0; i<1000000; i++)
+- if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
+- break;
+-
++ xf86getsecs(&to2_secs, &to2_usecs);
++ if ((to2_secs - start_secs) > 1)
++ goto failed;
++ }
+ xf86getsecs(&stop_secs, &stop_usecs);
+
++ if ((stop_secs - start_secs) != 0)
++ goto again;
+ total_usecs = abs(stop_usecs - start_usecs);
+- hz = 1000000/total_usecs;
++ if (total_usecs == 0)
++ goto again;
++ hz = 1000000.0/(float)total_usecs;
+
+- hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
+- vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
++ hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8;
++ vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1);
+ vclk = (float)(hTotal * (float)(vTotal * hz));
+
+ switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) {
+@@ -1280,23 +1304,94 @@
+ else if ((xtal > 29400000) && (xtal < 29600000))
+ xtal = 2950;
+ else
+- return FALSE;
++ goto again;
++ failed:
++ if (xtal == 0) {
++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! "
++ "Using default 27Mhz\n");
++ xtal = 2700;
++ } else {
++ if (prev_xtal == 0) {
++ prev_xtal = xtal;
++ tries = 0;
++ goto again;
++ } else if (prev_xtal != xtal) {
++ prev_xtal = 0;
++ goto again;
++ }
++ }
+
+ tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV);
+ ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff;
+
+- Nx = (tmp & 0xff00) >> 8;
++ /* Some sanity check based on the BIOS code .... */
++ if (ref_div < 2) {
++ CARD32 tmp;
++ tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV);
++ if (IS_R300_VARIANT || (info->ChipFamily == CHIP_FAMILY_RS300))
++ ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >>
++ R300_PPLL_REF_DIV_ACC_SHIFT;
++ else
++ ref_div = tmp & RADEON_PPLL_REF_DIV_MASK;
++ if (ref_div < 2)
++ ref_div = 12;
++ }
++
++ /* Calculate "base" xclk straight from MPLL, though that isn't
++ * really useful (hopefully)
++ */
++ mpll_fb_div = (tmp & 0xff00) >> 8;
++ spll_fb_div = (tmp & 0xff0000) >> 16;
+ M = (tmp & 0xff);
+- xclk = RADEONDiv((2 * Nx * xtal), (2 * M));
++ xclk = RADEONDiv((2 * mpll_fb_div * xtal), (2 * M));
+
++ /*
++ * Calculate MCLK based on MCLK-A and SCLK
++ *
++ * NOTE: It is not clear at this point wether we should put in sclk and
++ * mclk the raw SPLL and MPLL output values, or the divided values according
++ * to the source selection iN MCLK_CNTL and SCLK_CNTL. I'm putting the divided
++ * values for now, waiting for a definitive answer from ATI
++ */
++ mpll = ((float)mpll_fb_div * (float)(xtal / 100.0)) / (float)M;
++ spll = ((float)spll_fb_div * (float)(xtal / 100.0)) / (float)M;
++
++ tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7;
++ switch(tmp) {
++ case 1: info->mclk = mpll; break;
++ case 2: info->mclk = mpll / 2.0; break;
++ case 3: info->mclk = mpll / 4.0; break;
++ case 4: info->mclk = mpll / 8.0; break;
++ case 7: info->mclk = spll; break;
++ default:
++ info->mclk = 200.00;
++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source"
++ " setting %d, can't probe MCLK value !\n", tmp);
++ }
++
++ tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7;
++ switch(tmp) {
++ case 1: info->sclk = spll; break;
++ case 2: info->sclk = spll / 2.0; break;
++ case 3: info->sclk = spll / 4.0; break;
++ case 4: info->sclk = spll / 8.0; break;
++ case 7: info->sclk = mpll;
++ default:
++ info->sclk = 200.00;
++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source"
++ " setting %d, can't probe SCLK value !\n", tmp);
++ }
++
+ /* we're done, hopefully these are sane values */
+ pll->reference_div = ref_div;
+ pll->xclk = xclk;
+ pll->reference_freq = xtal;
+
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, "
++ "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk);
++
+ return TRUE;
+ }
+-#endif
+
+ static void RADEONGetPanelInfoFromReg (ScrnInfoPtr pScrn)
+ {
+@@ -1321,7 +1416,25 @@
+ info->PanelXRes = 640;
+ info->PanelYRes = 480;
+ }
+-
++
++ if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) {
++ CARD32 ppll_div_sel, ppll_val;
++
++ OUTREG(RADEON_CLOCK_CNTL_INDEX, 1);
++ ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_DATA + 1) & 0x3;
++ ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel);
++ if ((ppll_val & 0x000707ff) == 0x1bb)
++ goto noprobe;
++ info->FeedbackDivider = ppll_val & 0x7ff;
++ info->PostDivider = (ppll_val >> 16) & 0x7;
++ info->RefDivider = info->pll.reference_div;
++ info->UseBiosDividers = TRUE;
++
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
++ "Existing panel PLL dividers will be used.\n");
++ }
++ noprobe:
++
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "Panel size %dx%d is derived, this may not be correct.\n"
+ "If not, use PanelSize option to overwrite this setting\n",
+@@ -1335,17 +1448,24 @@
+ if (!RADEONGetLVDSInfoFromBIOS(pScrn))
+ RADEONGetPanelInfoFromReg(pScrn);
+
++ /* The panel size we collected from BIOS may not be the
++ * maximum size supported by the panel. If not, we update
++ * it now. These will be used if no matching mode can be
++ * found from EDID data.
++ */
++ RADEONUpdatePanelSize(pScrn);
++
++ /* No timing information for the native mode,
++ * use whatever specified in the Modeline.
++ * If no Modeline specified, we'll just pick
++ * the VESA mode at 60Hz refresh rate which
++ * is likely to be the best for a flat panel.
++ */
+ if (info->DotClock == 0) {
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+ DisplayModePtr tmp_mode = NULL;
+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
+ "No valid timing info from BIOS.\n");
+- /* No timing information for the native mode,
+- use whatever specified in the Modeline.
+- If no Modeline specified, we'll just pick
+- the VESA mode at 60Hz refresh rate which
+- is likely to be the best for a flat panel.
+- */
+ tmp_mode = pScrn->monitor->Modes;
+ while(tmp_mode) {
+ if ((tmp_mode->HDisplay == info->PanelXRes) &&
+@@ -1416,6 +1536,8 @@
+ RADEONGetTMDSInfo(pScrn);
+ if (!pScrn->monitor->DDC)
+ RADEONGetHardCodedEDIDFromBIOS(pScrn);
++ else if (!info->IsSecondary)
++ RADEONUpdatePanelSize(pScrn);
+ }
+ }
+ }
+@@ -1448,17 +1570,24 @@
+ xf86DrvMsg (pScrn->scrnIndex, X_WARNING,
+ "Video BIOS not detected, using default clock settings!\n");
+
+-#if defined(__powerpc__)
+- if (RADEONProbePLLParameters(pScrn)) return;
+-#endif
++ /* Default min/max PLL values */
++ if (info->ChipFamily == CHIP_FAMILY_R420) {
++ pll->min_pll_freq = 20000;
++ pll->max_pll_freq = 50000;
++ } else {
++ pll->min_pll_freq = 12500;
++ pll->max_pll_freq = 35000;
++ }
++
++ if (RADEONProbePLLParameters(pScrn))
++ return;
++
+ if (info->IsIGP)
+ pll->reference_freq = 1432;
+ else
+ pll->reference_freq = 2700;
+
+ pll->reference_div = 12;
+- pll->min_pll_freq = 12500;
+- pll->max_pll_freq = 35000;
+ pll->xclk = 10300;
+
+ info->sclk = 200.00;
+@@ -1610,6 +1739,14 @@
+ pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY;
+ pRADEONEnt->PortInfo[1].TMDSType = TMDS_EXT;
+ pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_CRT;
++
++ /* Some cards have the DDC lines swapped and we have no way to
++ * detect it yet (Mac cards)
++ */
++ if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
++ pRADEONEnt->PortInfo[0].DDCType = DDC_VGA;
++ pRADEONEnt->PortInfo[1].DDCType = DDC_DVI;
++ }
+ }
+
+ /* always make TMDS_INT port first*/
+@@ -2599,14 +2736,35 @@
+ xf86MonPtr ddc = pScrn->monitor->DDC;
+ DisplayModePtr p;
+
++ if (info->UseBiosDividers && info->DotClock != 0)
++ return;
++
+ /* Go thru detailed timing table first */
+ for (j = 0; j < 4; j++) {
+ if (ddc->det_mon[j].type == 0) {
+ struct detailed_timings *d_timings =
+ &ddc->det_mon[j].section.d_timings;
++ int match = 0;
++
++ /* If we didn't get a panel clock or guessed one, try to match the
++ * mode with the panel size. We do that because we _need_ a panel
++ * clock, or ValidateFPModes will fail, even when UseBiosDividers
++ * is set.
++ */
++ if (info->DotClock == 0 &&
++ info->PanelXRes == d_timings->h_active &&
++ info->PanelYRes == d_timings->v_active)
++ match = 1;
++
++ /* If we don't have a BIOS provided panel data with fixed dividers,
++ * check for a larger panel size
++ */
+ if (info->PanelXRes <= d_timings->h_active &&
+- info->PanelYRes <= d_timings->v_active) {
++ info->PanelYRes <= d_timings->v_active &&
++ !info->UseBiosDividers)
++ match = 1;
+
++ if (match) {
+ if (info->DotClock) continue; /* Timings already inited */
+
+ info->PanelXRes = d_timings->h_active;
+@@ -2618,10 +2776,24 @@
+ info->VOverPlus = d_timings->v_sync_off;
+ info->VSyncWidth = d_timings->v_sync_width;
+ info->VBlank = d_timings->v_blanking;
++ info->Flags = (d_timings->interlaced ? V_INTERLACE : 0);
++ if (d_timings->sync == 3) {
++ switch (d_timings->misc) {
++ case 0: info->Flags |= V_NHSYNC | V_NVSYNC; break;
++ case 1: info->Flags |= V_PHSYNC | V_NVSYNC; break;
++ case 2: info->Flags |= V_NHSYNC | V_PVSYNC; break;
++ case 3: info->Flags |= V_PHSYNC | V_PVSYNC; break;
++ }
++ }
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC detailed: %dx%d\n",
++ info->PanelXRes, info->PanelYRes);
+ }
+ }
+ }
+
++ if (info->UseBiosDividers && info->DotClock != 0)
++ return;
++
+ /* Search thru standard VESA modes from EDID */
+ for (j = 0; j < 8; j++) {
+ if ((info->PanelXRes < ddc->timings2[j].hsize) &&
+@@ -2643,26 +2815,14 @@
+ info->VOverPlus = p->VSyncStart - p->VDisplay;
+ info->VSyncWidth = p->VSyncEnd - p->VSyncStart;
+ info->DotClock = p->Clock;
+- info->Flags =
+- (ddc->det_mon[j].section.d_timings.interlaced
+- ? V_INTERLACE
+- : 0);
+- if (ddc->det_mon[j].section.d_timings.sync == 3) {
+- switch (ddc->det_mon[j].section.d_timings.misc) {
+- case 0: info->Flags |= V_NHSYNC | V_NVSYNC; break;
+- case 1: info->Flags |= V_PHSYNC | V_NVSYNC; break;
+- case 2: info->Flags |= V_NHSYNC | V_PVSYNC; break;
+- case 3: info->Flags |= V_PHSYNC | V_PVSYNC; break;
+- }
+- }
++ info->Flags = p->Flags;
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC VESA/EDID: %dx%d\n",
++ info->PanelXRes, info->PanelYRes);
+ }
+ }
+ }
+ }
+ }
+-
+- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel size found from DDC: %dx%d\n",
+- info->PanelXRes, info->PanelYRes);
+ }
+
+ /* This function will sort all modes according to their resolution.
+@@ -2783,6 +2943,8 @@
+
+ /* Search thru standard VESA modes from EDID */
+ for (j = 0; j < 8; j++) {
++ if (ddc->timings2[j].hsize == 0 || ddc->timings2[j].vsize == 0)
++ continue;
+ for (p = pScrn->monitor->Modes; p && p->next; p = p->next->next) {
+ /* Ignore all double scan modes */
+ if ((ddc->timings2[j].hsize == p->HDisplay) &&
+@@ -2872,19 +3034,10 @@
+ pScrn->virtualX = pScrn1->display->virtualX;
+ pScrn->virtualY = pScrn1->display->virtualY;
+
+- if (pScrn->monitor->DDC && !info->UseBiosDividers) {
++ if (pScrn->monitor->DDC) {
+ int maxVirtX = pScrn->virtualX;
+ int maxVirtY = pScrn->virtualY;
+
+- if ((DisplayType != MT_CRT) && (!info->IsSecondary) && (!crtc2)) {
+- /* The panel size we collected from BIOS may not be the
+- * maximum size supported by the panel. If not, we update
+- * it now. These will be used if no matching mode can be
+- * found from EDID data.
+- */
+- RADEONUpdatePanelSize(pScrn);
+- }
+-
+ /* Collect all of the DDC modes */
+ first = last = ddcModes = RADEONDDCModes(pScrn);
+
+@@ -3576,7 +3729,8 @@
+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
+ "Invalid PanelSize value: %s\n", s);
+ }
+- }
++ } else
++ RADEONGetPanelInfo(pScrn);
+ }
+
+ if (pScrn->monitor->DDC) {
+@@ -4143,15 +4297,7 @@
+ return TRUE;
+ }
+
+- if (!xf86LoadSubModule(pScrn, "vgahw")) return FALSE;
+- xf86LoaderReqSymLists(vgahwSymbols, NULL);
+- if (!vgaHWGetHWRec(pScrn)) {
+- RADEONFreeRec(pScrn);
+- goto fail2;
+- }
+
+- vgaHWGetIOBase(VGAHWPTR(pScrn));
+-
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "PCI bus %d card %d func %d\n",
+ info->PciInfo->bus,
+@@ -4179,6 +4325,32 @@
+ memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
+ xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
+
++ /* By default, don't do VGA IOs on ppc */
++#ifdef __powerpc__
++ info->VGAAccess = FALSE;
++#else
++ info->VGAAccess = TRUE;
++#endif
++
++ xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess);
++ if (info->VGAAccess) {
++ if (!xf86LoadSubModule(pScrn, "vgahw"))
++ info->VGAAccess = FALSE;
++ else {
++ xf86LoaderReqSymLists(vgahwSymbols, NULL);
++ if (!vgaHWGetHWRec(pScrn))
++ info->VGAAccess = FALSE;
++ }
++ if (!info->VGAAccess)
++ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed,"
++ " trying to run without it\n");
++ } else
++ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE,"
++ " VGA module load skipped\n");
++ if (info->VGAAccess)
++ vgaHWGetIOBase(VGAHWPTR(pScrn));
++
++
+ if (!RADEONPreInitWeight(pScrn))
+ goto fail;
+
+@@ -4237,7 +4409,6 @@
+ RADEONGetBIOSInfo(pScrn, pInt10);
+ if (!RADEONQueryConnectedMonitors(pScrn)) goto fail;
+ RADEONGetClockInfo(pScrn);
+- RADEONGetPanelInfo(pScrn);
+
+ /* collect MergedFB options */
+ /* only parse mergedfb options on the primary head.
+@@ -4293,7 +4464,8 @@
+ if (pInt10)
+ xf86FreeInt10(pInt10);
+
+- vgaHWFreeHWRec(pScrn);
++ if (info->VGAAccess)
++ vgaHWFreeHWRec(pScrn);
+
+ fail2:
+ if(info->MMIO) RADEONUnmapMMIO(pScrn);
+@@ -5731,7 +5903,6 @@
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ RADEONSavePtr save = &info->SavedReg;
+- vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ RADEONTRACE(("RADEONSave\n"));
+ if (info->FBDev) {
+@@ -5740,19 +5911,23 @@
+ }
+
+ if (!info->IsSecondary) {
+- vgaHWUnlock(hwp);
++ if (info->VGAAccess) {
++ vgaHWPtr hwp = VGAHWPTR(pScrn);
++
++ vgaHWUnlock(hwp);
+ #if defined(__powerpc__)
+- /* temporary hack to prevent crashing on PowerMacs when trying to
+- * read VGA fonts and colormap, will find a better solution
+- * in the future
+- */
+- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
++ /* temporary hack to prevent crashing on PowerMacs when trying to
++ * read VGA fonts and colormap, will find a better solution
++ * in the future. TODO: Check if there's actually some VGA stuff
++ * setup in the card at all !!
++ */
++ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
+ #else
+- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS); /* Save mode
+- * & fonts & cmap
+- */
++ /* Save mode * & fonts & cmap */
++ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS);
+ #endif
+- vgaHWLock(hwp);
++ vgaHWLock(hwp);
++ }
+ save->dp_datatype = INREG(RADEON_DP_DATATYPE);
+ save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
+ save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
+@@ -5768,7 +5943,6 @@
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
+ RADEONSavePtr restore = &info->SavedReg;
+- vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ RADEONTRACE(("RADEONRestore\n"));
+
+@@ -5810,27 +5984,36 @@
+ usleep(100000);
+ #endif
+
+- if (!info->IsSecondary) {
+- vgaHWUnlock(hwp);
++ if (info->VGAAccess) {
++ vgaHWPtr hwp = VGAHWPTR(pScrn);
++ if (!info->IsSecondary) {
++ vgaHWUnlock(hwp);
+ #if defined(__powerpc__)
+- /* Temporary hack to prevent crashing on PowerMacs when trying to
+- * write VGA fonts, will find a better solution in the future
+- */
+- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
++ /* Temporary hack to prevent crashing on PowerMacs when trying to
++ * write VGA fonts, will find a better solution in the future
++ */
++ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
+ #else
+- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
++ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
+ #endif
+- vgaHWLock(hwp);
+- } else {
+- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+- ScrnInfoPtr pScrn0;
+- vgaHWPtr hwp0;
++ vgaHWLock(hwp);
++ } else {
++ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
++ ScrnInfoPtr pScrn0 = pRADEONEnt->pPrimaryScrn;
++ RADEONInfoPtr info0 = RADEONPTR(pScrn0);
++ vgaHWPtr hwp0;
+
+- pScrn0 = pRADEONEnt->pPrimaryScrn;
+- hwp0 = VGAHWPTR(pScrn0);
+- vgaHWUnlock(hwp0);
+- vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
+- vgaHWLock(hwp0);
++ if (info0->VGAAccess) {
++ hwp0 = VGAHWPTR(pScrn0);
++ vgaHWUnlock(hwp0);
++#if defined(__powerpc__)
++ vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE);
++#else
++ vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
++#endif
++ vgaHWLock(hwp0);
++ }
++ }
+ }
+ RADEONUnblank(pScrn);
+
+@@ -5978,7 +6161,7 @@
+ */
+ temp = INREG(RADEON_MEM_CNTL);
+ data = (R300_MEM_NUM_CHANNELS_MASK & temp);
+- if (data == 2) {
++ if (data == 1) {
+ if (R300_MEM_USE_CD_CH_ONLY & temp) {
+ temp = INREG(R300_MC_IND_INDEX);
+ temp &= ~R300_MC_IND_ADDR_MASK;
+@@ -6459,8 +6642,13 @@
+ ? RADEON_CRTC2_V_SYNC_POL
+ : 0));
+
++ /* We must make sure Tiling is disabled. It seem all other fancy
++ * options in there can be safely disabled too
++ */
+ save->crtc2_offset = 0;
+- save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
++ save->crtc2_offset_cntl = 0;
++
++
+ /* this should be right */
+ if (info->MergedFB) {
+ save->crtc2_pitch = (((info->CRT2pScrn->displayWidth * pScrn->bitsPerPixel) +
+@@ -6482,6 +6670,7 @@
save->fp2_h_sync_strt_wid = save->crtc2_h_sync_strt_wid;
save->fp2_v_sync_strt_wid = save->crtc2_v_sync_strt_wid;
save->fp2_gen_cntl = info->SavedReg.fp2_gen_cntl | RADEON_FP2_ON;
@@ -104,6 +919,230 @@
if (info->ChipFamily == CHIP_FAMILY_R200 ||
IS_R300_VARIANT) {
+@@ -6502,6 +6691,23 @@
+
+ }
+
++ /* We must set SURFACE_CNTL properly on the second screen too */
++ save->surface_cntl = 0;
++#if X_BYTE_ORDER == X_BIG_ENDIAN
++ /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */
++ switch (pScrn->bitsPerPixel) {
++ case 16:
++ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
++ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
++ break;
++
++ case 32:
++ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
++ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
++ break;
++ }
++#endif
++
+ RADEONTRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n",
+ save->crtc2_pitch, pScrn->virtualX,
+ info->CurrentLayout.displayWidth));
+@@ -6727,8 +6933,8 @@
+ }
+
+ /* Define PLL registers for requested video mode */
+-static void RADEONInitPLLRegisters(RADEONSavePtr save, RADEONPLLPtr pll,
+- double dot_clock)
++static void RADEONInitPLLRegisters(RADEONInfoPtr info, RADEONSavePtr save,
++ RADEONPLLPtr pll, double dot_clock)
+ {
+ unsigned long freq = dot_clock * 100;
+
+@@ -6752,6 +6958,13 @@
+ { 0, 0 }
+ };
+
++ if (info->UseBiosDividers) {
++ save->ppll_ref_div = info->RefDivider;
++ save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
++ save->htotal_cntl = 0;
++ return;
++ }
++
+ if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
+ if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
+
+@@ -6786,7 +6999,7 @@
+
+ /* Define PLL2 registers for requested video mode */
+ static void RADEONInitPLL2Registers(RADEONSavePtr save, RADEONPLLPtr pll,
+- double dot_clock)
++ double dot_clock, int no_odd_postdiv)
+ {
+ unsigned long freq = dot_clock * 100;
+
+@@ -6813,6 +7026,11 @@
+ if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
+
+ for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
++ /* Odd post divider value don't work properly on the second digital
++ * output
++ */
++ if (no_odd_postdiv && (post_div->divider & 1))
++ continue;
+ save->pll_output_freq_2 = post_div->divider * freq;
+ if (save->pll_output_freq_2 >= pll->min_pll_freq
+ && save->pll_output_freq_2 <= pll->max_pll_freq) break;
+@@ -6913,7 +7131,7 @@
+ if (info->IsSecondary) {
+ if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))
+ return FALSE;
+- RADEONInitPLL2Registers(save, &info->pll, dot_clock);
++ RADEONInitPLL2Registers(save, &info->pll, dot_clock, info->DisplayType != MT_CRT);
+ } else if (info->MergedFB) {
+ RADEONInitCommonRegisters(save, info);
+ if (!RADEONInitCrtcRegisters(pScrn, save,
+@@ -6921,7 +7139,7 @@
+ return FALSE;
+ dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0;
+ if (dot_clock) {
+- RADEONInitPLLRegisters(save, &info->pll, dot_clock);
++ RADEONInitPLLRegisters(info, save, &info->pll, dot_clock);
+ } else {
+ save->ppll_ref_div = info->SavedReg.ppll_ref_div;
+ save->ppll_div_3 = info->SavedReg.ppll_div_3;
+@@ -6930,19 +7148,13 @@
+ RADEONInitCrtc2Registers(pScrn, save,
+ ((RADEONMergedDisplayModePtr)mode->Private)->CRT2, info);
+ dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT2)->Clock / 1000.0;
+- RADEONInitPLL2Registers(save, &info->pll, dot_clock);
++ RADEONInitPLL2Registers(save, &info->pll, dot_clock, info->MergeType != MT_CRT);
+ } else {
+ if (!RADEONInitCrtcRegisters(pScrn, save, mode, info))
+ return FALSE;
+ dot_clock = mode->Clock/1000.0;
+ if (dot_clock) {
+- if (info->UseBiosDividers) {
+- save->ppll_ref_div = info->RefDivider;
+- save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
+- save->htotal_cntl = 0;
+- }
+- else
+- RADEONInitPLLRegisters(save, &info->pll, dot_clock);
++ RADEONInitPLLRegisters(info, save, &info->pll, dot_clock);
+ } else {
+ save->ppll_ref_div = info->SavedReg.ppll_ref_div;
+ save->ppll_div_3 = info->SavedReg.ppll_div_3;
+@@ -7349,7 +7561,7 @@
+ }
+ }
+
+- if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
++ if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
+ vgaHWFreeHWRec(pScrn);
+ RADEONFreeRec(pScrn);
+ }
+Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man
+===================================================================
+--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man (revision 140)
++++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man (working copy)
+@@ -494,6 +494,34 @@
+ with this enabled. The default is
+ .B off.
+ .TP
++.BI "Option \*qVGAAccess\*q \*q" boolean \*q
++Tell the driver if it can do legacy VGA IOs to the card. This is
++necessary for properly resuming consoles when in VGA text mode, but
++shouldn't be if the console is using radeonfb or some other graphic
++mode driver. Some platforms like PowerPC have issues with those, and they aren't
++necessary unless you have a real text mode in console. The default is
++.B off
++on PowerPC and
++.B on
++on other architectures.
++.TP
++.BI "Option \*qReverseDDC\*q \*q" boolean \*q
++When BIOS connector informations aren't available, use this option to
++reverse the mapping of the 2 main DDC ports. Use this if the X serve
++obviously detects the wrong display for each connector. This is
++typically needed on the Radeon 9600 cards bundled with Apple G5s. The
++default is
++.B off.
++.TP
++.BI "Option \*qLVDSProbePLL\*q \*q" boolean \*q
++When BIOS panel informations aren't available (like on PowerBooks), it
++may still be necessary to use the firmware provided PLL values for the
++panel or flickering will happen. This option will force probing of
++the current value programmed in the chip when X is launched in that
++case. This is only useful for LVDS panels (laptop internal panels).
++The default is
++.B on.
++.TP
+
+ .SH SEE ALSO
+ __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
+Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h
+===================================================================
+--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h (revision 140)
++++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h (working copy)
+@@ -596,6 +596,9 @@
+
+ /* special handlings for DELL triple-head server */
+ Bool IsDellServer;
++
++ Bool VGAAccess;
++
+ } RADEONInfoRec, *RADEONInfoPtr;
+
+
+Index: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c
+===================================================================
+--- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c (revision 140)
++++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c (working copy)
+@@ -291,10 +291,8 @@
+ OUTREGP(RADEON_DP_DATATYPE, 0, ~RADEON_HOST_BIG_ENDIAN_EN);
+ #endif
+
+- /* Restore SURFACE_CNTL - only the first head contains valid data -ReneR */
+- if (!info->IsSecondary) {
+- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+- }
++ /* Restore SURFACE_CNTL */
++ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
+
+ RADEONWaitForFifo(pScrn, 1);
+ OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
+Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man
+===================================================================
+--- xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man (revision 140)
++++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128.man (working copy)
+@@ -123,6 +123,17 @@
+ .BI "Option \*qShowCache\*q \*q" boolean \*q
+ Enable or disable viewing offscreen cache memory. A
+ development debug option. Default: off.
++.TP
++.BI "Option \*qVGAAccess\*q \*q" boolean \*q
++Tell the driver if it can do legacy VGA IOs to the card. This is
++necessary for properly resuming consoles when in VGA text mode, but
++shouldn't be if the console is using radeonfb or some other graphic
++mode driver. Some platforms like PowerPC have issues with those, and they aren't
++necessary unless you have a real text mode in console. The default is
++.B off
++on PowerPC and
++.B on
++on other architectures.
+
+ .SH "SEE ALSO"
+ __xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
+Index: xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h
+===================================================================
+--- xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h (revision 140)
++++ xc/programs/Xserver/hw/xfree86/drivers/ati/r128.h (working copy)
+@@ -401,6 +401,8 @@
+ I2CBusPtr pI2CBus;
+ CARD32 DDCReg;
+
++ Bool VGAAccess;
++
+ } R128InfoRec, *R128InfoPtr;
+
+ #define R128WaitForFifo(pScrn, entries) \
Index: xc/programs/Xserver/hw/dmx/config/Imakefile
===================================================================
RCS file: /cvs/xorg/xc/programs/Xserver/hw/dmx/config/Imakefile,v
Deleted: trunk/debian/patches/024a_radeon_benh_fixes.diff
===================================================================
--- trunk/debian/patches/024a_radeon_benh_fixes.diff 2005-06-14 19:46:39 UTC (rev 207)
+++ trunk/debian/patches/024a_radeon_benh_fixes.diff 2005-06-14 20:04:50 UTC (rev 208)
@@ -1,797 +0,0 @@
-$Id$
-
-diff -urN xc/programs/Xserver/hw/xfree86/drivers/ati.orig/radeon.h xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h
---- xc/programs/Xserver/hw/xfree86/drivers/ati.orig/radeon.h 2005-03-28 22:38:44.127214368 +1000
-+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h 2005-03-28 22:41:06.849517280 +1000
-@@ -593,6 +593,7 @@
- Bool AtLeastOneNonClone;
- int MergedFBXDPI, MergedFBYDPI;
- Bool NoVirtual;
-+ Bool VGAAccess;
-
- /* special handlings for DELL triple-head server */
- Bool IsDellServer;
-diff -urN xc/programs/Xserver/hw/xfree86/drivers/ati.orig/radeon_accel.c xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c
---- xc/programs/Xserver/hw/xfree86/drivers/ati.orig/radeon_accel.c 2005-03-28 22:38:44.127214368 +1000
-+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c 2005-03-28 22:41:06.850517128 +1000
-@@ -291,10 +291,8 @@
- OUTREGP(RADEON_DP_DATATYPE, 0, ~RADEON_HOST_BIG_ENDIAN_EN);
- #endif
-
-- /* Restore SURFACE_CNTL - only the first head contains valid data -ReneR */
-- if (!info->IsSecondary) {
-- OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
-- }
-+ /* Restore SURFACE_CNTL */
-+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg.surface_cntl);
-
- RADEONWaitForFifo(pScrn, 1);
- OUTREG(RADEON_DEFAULT_SC_BOTTOM_RIGHT, (RADEON_DEFAULT_SC_RIGHT_MAX
-diff -urN xc/programs/Xserver/hw/xfree86/drivers/ati.orig/radeon_driver.c xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c
---- xc/programs/Xserver/hw/xfree86/drivers/ati.orig/radeon_driver.c 2005-03-28 22:38:44.133213456 +1000
-+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 2005-03-28 22:41:06.872513784 +1000
-@@ -118,6 +118,7 @@
- static void RADEONGetMergedFBOptions(ScrnInfoPtr pScrn);
- static int RADEONValidateMergeModes(ScrnInfoPtr pScrn);
- static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode);
-+static void RADEONUpdatePanelSize(ScrnInfoPtr pScrn);
-
- /* psuedo xinerama support */
-
-@@ -164,7 +165,10 @@
- OPTION_SUBPIXEL_ORDER,
- #endif
- OPTION_SHOWCACHE,
-- OPTION_DYNAMIC_CLOCKS
-+ OPTION_DYNAMIC_CLOCKS,
-+ OPTION_VGA_ACCESS,
-+ OPTION_LVDS_PROBE_PLL,
-+ OPTION_REVERSE_DDC,
- } RADEONOpts;
-
- static const OptionInfoRec RADEONOptions[] = {
-@@ -209,6 +213,9 @@
- #endif
- { OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE },
- { OPTION_DYNAMIC_CLOCKS, "DynamicClocks", OPTV_BOOLEAN, {0}, FALSE },
-+ { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE },
-+ { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE },
-+ { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE },
- { -1, NULL, OPTV_NONE, {0}, FALSE }
- };
-
-@@ -1184,41 +1191,55 @@
- return(bConnected ? MT_CRT : MT_NONE);
- }
-
--#if defined(__powerpc__)
- static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn)
- {
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONPLLPtr pll = &info->pll;
- unsigned char *RADEONMMIO = info->MMIO;
- unsigned char ppll_div_sel;
-- unsigned Nx, M;
-+ unsigned mpll_fb_div, spll_fb_div, M;
- unsigned xclk, tmp, ref_div;
- int hTotal, vTotal, num, denom, m, n;
-- float hz, vclk, xtal;
-+ float hz, prev_xtal, vclk, xtal, mpll, spll;
- long start_secs, start_usecs, stop_secs, stop_usecs, total_usecs;
-- int i;
--
-- for(i=0; i<1000000; i++)
-- if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
-+ long to1_secs, to1_usecs, to2_secs, to2_usecs;
-+ unsigned int f1, f2, f3;
-+ int i, tries = 0;
-+
-+ prev_xtal = 0;
-+ again:
-+ xtal = 0;
-+ if (++tries > 10)
-+ goto failed;
-+
-+ xf86getsecs(&to1_secs, &to2_usecs);
-+ f1 = INREG(RADEON_CRTC_CRNT_FRAME);
-+ for (;;) {
-+ f2 = INREG(RADEON_CRTC_CRNT_FRAME);
-+ if (f1 != f2)
- break;
--
-+ xf86getsecs(&to2_secs, &to2_usecs);
-+ if ((to2_secs - to1_secs) > 1) {
-+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n");
-+ goto failed;
-+ }
-+ }
- xf86getsecs(&start_secs, &start_usecs);
--
-- for(i=0; i<1000000; i++)
-- if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
-+ for(;;) {
-+ f3 = INREG(RADEON_CRTC_CRNT_FRAME);
-+ if (f3 != f2)
- break;
--
-- for(i=0; i<1000000; i++)
-- if (((INREG(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
-- break;
--
-+ xf86getsecs(&to2_secs, &to2_usecs);
-+ if ((to2_secs - start_secs) > 1)
-+ goto failed;
-+ }
- xf86getsecs(&stop_secs, &stop_usecs);
-
- total_usecs = abs(stop_usecs - start_usecs);
- hz = 1000000/total_usecs;
-
-- hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
-- vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
-+ hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8;
-+ vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1);
- vclk = (float)(hTotal * (float)(vTotal * hz));
-
- switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) {
-@@ -1280,23 +1301,80 @@
- else if ((xtal > 29400000) && (xtal < 29600000))
- xtal = 2950;
- else
-- return FALSE;
-+ goto again;
-+ failed:
-+ if (xtal == 0) {
-+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! Using default 27Mhz\n");
-+ xtal = 2700;
-+ } else {
-+ if (prev_xtal == 0) {
-+ prev_xtal = xtal;
-+ tries = 0;
-+ goto again;
-+ } else if (prev_xtal != xtal) {
-+ prev_xtal = 0;
-+ goto again;
-+ }
-+ }
-
- tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV);
- ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff;
-
-- Nx = (tmp & 0xff00) >> 8;
-+ /* Calculate "base" xclk straight from MPLL, though that isn't
-+ * really useful (hopefully)
-+ */
-+ mpll_fb_div = (tmp & 0xff00) >> 8;
-+ spll_fb_div = (tmp & 0xff0000) >> 16;
- M = (tmp & 0xff);
-- xclk = RADEONDiv((2 * Nx * xtal), (2 * M));
-+ xclk = RADEONDiv((2 * mpll_fb_div * xtal), (2 * M));
-+
-+ /*
-+ * Calculate MCLK based on MCLK-A and SCLK
-+ *
-+ * NOTE: It is not clear at this point wether we should put in sclk and
-+ * mclk the raw SPLL and MPLL output values, or the divided values according
-+ * to the source selection iN MCLK_CNTL and SCLK_CNTL. I'm putting the divided
-+ * values for now, waiting for a definitive answer from ATI
-+ */
-+ mpll = ((float)mpll_fb_div * (float)(xtal / 100.0)) / (float)M;
-+ spll = ((float)spll_fb_div * (float)(xtal / 100.0)) / (float)M;
-+
-+ tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7;
-+ switch(tmp) {
-+ case 1: info->mclk = mpll; break;
-+ case 2: info->mclk = mpll / 2.0; break;
-+ case 3: info->mclk = mpll / 4.0; break;
-+ case 4: info->mclk = mpll / 8.0; break;
-+ case 7: info->mclk = spll; break;
-+ default:
-+ info->mclk = 200.00;
-+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source"
-+ " setting %d, can't probe MCLK value !\n", tmp);
-+ }
-+
-+ tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7;
-+ switch(tmp) {
-+ case 1: info->sclk = spll; break;
-+ case 2: info->sclk = spll / 2.0; break;
-+ case 3: info->sclk = spll / 4.0; break;
-+ case 4: info->sclk = spll / 8.0; break;
-+ case 7: info->sclk = mpll;
-+ default:
-+ info->sclk = 200.00;
-+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source"
-+ " setting %d, can't probe SCLK value !\n", tmp);
-+ }
-
- /* we're done, hopefully these are sane values */
- pll->reference_div = ref_div;
- pll->xclk = xclk;
- pll->reference_freq = xtal;
-
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, "
-+ "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk);
-+
- return TRUE;
- }
--#endif
-
- static void RADEONGetPanelInfoFromReg (ScrnInfoPtr pScrn)
- {
-@@ -1321,6 +1399,24 @@
- info->PanelXRes = 640;
- info->PanelYRes = 480;
- }
-+
-+ if (xf86ReturnOptValBool(info->Options, OPTION_LVDS_PROBE_PLL, TRUE)) {
-+ CARD32 ppll_div_sel, ppll_val;
-+
-+ OUTREG(RADEON_CLOCK_CNTL_INDEX, 1);
-+ ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_DATA + 1) & 0x3;
-+ ppll_val = INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel);
-+ if ((ppll_val & 0x000707ff) == 0x1bb)
-+ goto noprobe;
-+ info->FeedbackDivider = ppll_val & 0x7ff;
-+ info->PostDivider = (ppll_val >> 16) & 0x7;
-+ info->RefDivider = info->pll.reference_div;
-+ info->UseBiosDividers = TRUE;
-+
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
-+ "Existing panel PLL dividers will be used.\n");
-+ }
-+ noprobe:
-
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "Panel size %dx%d is derived, this may not be correct.\n"
-@@ -1335,17 +1431,24 @@
- if (!RADEONGetLVDSInfoFromBIOS(pScrn))
- RADEONGetPanelInfoFromReg(pScrn);
-
-+ /* The panel size we collected from BIOS may not be the
-+ * maximum size supported by the panel. If not, we update
-+ * it now. These will be used if no matching mode can be
-+ * found from EDID data.
-+ */
-+ RADEONUpdatePanelSize(pScrn);
-+
-+ /* No timing information for the native mode,
-+ * use whatever specified in the Modeline.
-+ * If no Modeline specified, we'll just pick
-+ * the VESA mode at 60Hz refresh rate which
-+ * is likely to be the best for a flat panel.
-+ */
- if (info->DotClock == 0) {
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
- DisplayModePtr tmp_mode = NULL;
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
- "No valid timing info from BIOS.\n");
-- /* No timing information for the native mode,
-- use whatever specified in the Modeline.
-- If no Modeline specified, we'll just pick
-- the VESA mode at 60Hz refresh rate which
-- is likely to be the best for a flat panel.
-- */
- tmp_mode = pScrn->monitor->Modes;
- while(tmp_mode) {
- if ((tmp_mode->HDisplay == info->PanelXRes) &&
-@@ -1416,6 +1519,8 @@
- RADEONGetTMDSInfo(pScrn);
- if (!pScrn->monitor->DDC)
- RADEONGetHardCodedEDIDFromBIOS(pScrn);
-+ else if (!info->IsSecondary)
-+ RADEONUpdatePanelSize(pScrn);
- }
- }
- }
-@@ -1448,17 +1553,24 @@
- xf86DrvMsg (pScrn->scrnIndex, X_WARNING,
- "Video BIOS not detected, using default clock settings!\n");
-
--#if defined(__powerpc__)
-- if (RADEONProbePLLParameters(pScrn)) return;
--#endif
-+ /* First, setup default PLL min/max */
-+ if (info->ChipFamily >= CHIP_FAMILY_R420) {
-+ pll->min_pll_freq = 20000;
-+ pll->max_pll_freq = 50000;
-+ } else {
-+ pll->min_pll_freq = 12500;
-+ pll->max_pll_freq = 35000;
-+ }
-+ /* Try to probe the values from chip registers */
-+ if (RADEONProbePLLParameters(pScrn))
-+ return;
-+
- if (info->IsIGP)
- pll->reference_freq = 1432;
- else
- pll->reference_freq = 2700;
-
- pll->reference_div = 12;
-- pll->min_pll_freq = 12500;
-- pll->max_pll_freq = 35000;
- pll->xclk = 10300;
-
- info->sclk = 200.00;
-@@ -1610,6 +1722,14 @@
- pRADEONEnt->PortInfo[1].DACType = DAC_PRIMARY;
- pRADEONEnt->PortInfo[1].TMDSType = TMDS_EXT;
- pRADEONEnt->PortInfo[1].ConnectorType = CONNECTOR_CRT;
-+
-+ /* Some cards have the DDC lines swapped and we have no way to
-+ * detect it yet (Mac cards)
-+ */
-+ if (xf86ReturnOptValBool(info->Options, OPTION_REVERSE_DDC, FALSE)) {
-+ pRADEONEnt->PortInfo[0].DDCType = DDC_VGA;
-+ pRADEONEnt->PortInfo[1].DDCType = DDC_DVI;
-+ }
- }
-
- /* always make TMDS_INT port first*/
-@@ -2662,9 +2782,28 @@
- if (ddc->det_mon[j].type == 0) {
- struct detailed_timings *d_timings =
- &ddc->det_mon[j].section.d_timings;
-- if (info->PanelXRes <= d_timings->h_active &&
-- info->PanelYRes <= d_timings->v_active) {
-
-+ int match = 0;
-+
-+ /* If we didn't get a panel clock or guessed one, try to match the
-+ * mode with the panel size. We do that because we _need_ a panel
-+ * clock, or ValidateFPModes will fail, even when UseBiosDividers
-+ * is set.
-+ */
-+ if (info->DotClock == 0 &&
-+ info->PanelXRes == d_timings->h_active &&
-+ info->PanelYRes == d_timings->v_active)
-+ match = 1;
-+
-+ /* If we don't have a BIOS provided panel data with fixed dividers,
-+ * check for a larger panel size
-+ */
-+ if (info->PanelXRes < d_timings->h_active &&
-+ info->PanelYRes < d_timings->v_active &&
-+ !info->UseBiosDividers)
-+ match = 1;
-+
-+ if (match) {
- if (info->DotClock) continue; /* Timings already inited */
-
- info->PanelXRes = d_timings->h_active;
-@@ -2676,10 +2815,24 @@
- info->VOverPlus = d_timings->v_sync_off;
- info->VSyncWidth = d_timings->v_sync_width;
- info->VBlank = d_timings->v_blanking;
-+ info->Flags = (d_timings->interlaced ? V_INTERLACE : 0);
-+ if (d_timings->sync == 3) {
-+ switch (d_timings->misc) {
-+ case 0: info->Flags |= V_NHSYNC | V_NVSYNC; break;
-+ case 1: info->Flags |= V_PHSYNC | V_NVSYNC; break;
-+ case 2: info->Flags |= V_NHSYNC | V_PVSYNC; break;
-+ case 3: info->Flags |= V_PHSYNC | V_PVSYNC; break;
-+ }
-+ }
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC detailed: %dx%d\n",
-+ info->PanelXRes, info->PanelYRes);
- }
- }
- }
-
-+ if (info->UseBiosDividers && info->DotClock != 0)
-+ return;
-+
- /* Search thru standard VESA modes from EDID */
- for (j = 0; j < 8; j++) {
- if ((info->PanelXRes < ddc->timings2[j].hsize) &&
-@@ -2701,28 +2854,16 @@
- info->VOverPlus = p->VSyncStart - p->VDisplay;
- info->VSyncWidth = p->VSyncEnd - p->VSyncStart;
- info->DotClock = p->Clock;
-- info->Flags =
-- (ddc->det_mon[j].section.d_timings.interlaced
-- ? V_INTERLACE
-- : 0);
-- if (ddc->det_mon[j].section.d_timings.sync == 3) {
-- switch (ddc->det_mon[j].section.d_timings.misc) {
-- case 0: info->Flags |= V_NHSYNC | V_NVSYNC; break;
-- case 1: info->Flags |= V_PHSYNC | V_NVSYNC; break;
-- case 2: info->Flags |= V_NHSYNC | V_PVSYNC; break;
-- case 3: info->Flags |= V_PHSYNC | V_PVSYNC; break;
-- }
-- }
-+ info->Flags = p->Flags;
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel infos found from DDC VESA/EDID: %dx%d\n",
-+ info->PanelXRes, info->PanelYRes);
- }
- }
- }
- }
- }
--
-- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Panel size found from DDC: %dx%d\n",
-- info->PanelXRes, info->PanelYRes);
--}
--
-+ }
-+
- /* This function will sort all modes according to their resolution.
- * Highest resolution first.
- */
-@@ -2841,6 +2982,8 @@
-
- /* Search thru standard VESA modes from EDID */
- for (j = 0; j < 8; j++) {
-+ if (ddc->timings2[j].hsize == 0 || ddc->timings2[j].vsize == 0)
-+ continue;
- for (p = pScrn->monitor->Modes; p && p->next; p = p->next->next) {
- /* Ignore all double scan modes */
- if ((ddc->timings2[j].hsize == p->HDisplay) &&
-@@ -2930,19 +3073,10 @@
- pScrn->virtualX = pScrn1->display->virtualX;
- pScrn->virtualY = pScrn1->display->virtualY;
-
-- if (pScrn->monitor->DDC && !info->UseBiosDividers) {
-+ if (pScrn->monitor->DDC) {
- int maxVirtX = pScrn->virtualX;
- int maxVirtY = pScrn->virtualY;
-
-- if ((DisplayType != MT_CRT) && (!info->IsSecondary) && (!crtc2)) {
-- /* The panel size we collected from BIOS may not be the
-- * maximum size supported by the panel. If not, we update
-- * it now. These will be used if no matching mode can be
-- * found from EDID data.
-- */
-- RADEONUpdatePanelSize(pScrn);
-- }
--
- /* Collect all of the DDC modes */
- first = last = ddcModes = RADEONDDCModes(pScrn);
-
-@@ -3634,7 +3768,8 @@
- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "Invalid PanelSize value: %s\n", s);
- }
-- }
-+ } else
-+ RADEONGetPanelInfo(pScrn);
- }
-
- if (pScrn->monitor->DDC) {
-@@ -4201,15 +4336,6 @@
- return TRUE;
- }
-
-- if (!xf86LoadSubModule(pScrn, "vgahw")) return FALSE;
-- xf86LoaderReqSymLists(vgahwSymbols, NULL);
-- if (!vgaHWGetHWRec(pScrn)) {
-- RADEONFreeRec(pScrn);
-- goto fail2;
-- }
--
-- vgaHWGetIOBase(VGAHWPTR(pScrn));
--
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "PCI bus %d card %d func %d\n",
- info->PciInfo->bus,
-@@ -4237,6 +4363,32 @@
- memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions));
- xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options);
-
-+ /* By default, don't do VGA IOs on ppc */
-+#ifdef __powerpc__
-+ info->VGAAccess = FALSE;
-+#else
-+ info->VGAAccess = TRUE;
-+#endif
-+
-+ xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess);
-+ if (info->VGAAccess) {
-+ if (!xf86LoadSubModule(pScrn, "vgahw"))
-+ info->VGAAccess = FALSE;
-+ else {
-+ xf86LoaderReqSymLists(vgahwSymbols, NULL);
-+ if (!vgaHWGetHWRec(pScrn))
-+ info->VGAAccess = FALSE;
-+ }
-+ if (!info->VGAAccess)
-+ xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed,"
-+ " trying to run without it\n");
-+ } else
-+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE,"
-+ " VGA module load skipped\n");
-+ if (info->VGAAccess)
-+ vgaHWGetIOBase(VGAHWPTR(pScrn));
-+
-+
- if (!RADEONPreInitWeight(pScrn))
- goto fail;
-
-@@ -4295,7 +4447,6 @@
- RADEONGetBIOSInfo(pScrn, pInt10);
- if (!RADEONQueryConnectedMonitors(pScrn)) goto fail;
- RADEONGetClockInfo(pScrn);
-- RADEONGetPanelInfo(pScrn);
-
- /* collect MergedFB options */
- /* only parse mergedfb options on the primary head.
-@@ -4351,7 +4502,8 @@
- if (pInt10)
- xf86FreeInt10(pInt10);
-
-- vgaHWFreeHWRec(pScrn);
-+ if (info->VGAAccess)
-+ vgaHWFreeHWRec(pScrn);
-
- fail2:
- if(info->MMIO) RADEONUnmapMMIO(pScrn);
-@@ -5745,10 +5897,6 @@
- unsigned char *RADEONMMIO = info->MMIO;
- int i;
-
--#ifdef ENABLE_FLAT_PANEL
-- /* Select palette 0 (main CRTC) if using FP-enabled chip */
-- /* if (info->Port1 == MT_DFP) PAL_SELECT(1); */
--#endif
- PAL_SELECT(1);
- INPAL_START(0);
- for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT();
-@@ -5789,7 +5937,6 @@
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr save = &info->SavedReg;
-- vgaHWPtr hwp = VGAHWPTR(pScrn);
-
- RADEONTRACE(("RADEONSave\n"));
- if (info->FBDev) {
-@@ -5798,19 +5945,23 @@
- }
-
- if (!info->IsSecondary) {
-- vgaHWUnlock(hwp);
-+ if (info->VGAAccess) {
-+ vgaHWPtr hwp = VGAHWPTR(pScrn);
-+
-+ vgaHWUnlock(hwp);
- #if defined(__powerpc__)
-- /* temporary hack to prevent crashing on PowerMacs when trying to
-- * read VGA fonts and colormap, will find a better solution
-- * in the future
-- */
-- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
-+ /* temporary hack to prevent crashing on PowerMacs when trying to
-+ * read VGA fonts and colormap, will find a better solution
-+ * in the future. TODO: Check if there's actually some VGA stuff
-+ * setup in the card at all !!
-+ */
-+ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */
- #else
-- vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS); /* Save mode
-- * & fonts & cmap
-- */
-+ /* Save mode * & fonts & cmap */
-+ vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS);
- #endif
-- vgaHWLock(hwp);
-+ vgaHWLock(hwp);
-+ }
- save->dp_datatype = INREG(RADEON_DP_DATATYPE);
- save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
- save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
-@@ -5826,7 +5977,6 @@
- RADEONInfoPtr info = RADEONPTR(pScrn);
- unsigned char *RADEONMMIO = info->MMIO;
- RADEONSavePtr restore = &info->SavedReg;
-- vgaHWPtr hwp = VGAHWPTR(pScrn);
-
- RADEONTRACE(("RADEONRestore\n"));
-
-@@ -5868,27 +6018,36 @@
- usleep(100000);
- #endif
-
-- if (!info->IsSecondary) {
-- vgaHWUnlock(hwp);
-+ if (info->VGAAccess) {
-+ vgaHWPtr hwp = VGAHWPTR(pScrn);
-+ if (!info->IsSecondary) {
-+ vgaHWUnlock(hwp);
- #if defined(__powerpc__)
-- /* Temporary hack to prevent crashing on PowerMacs when trying to
-- * write VGA fonts, will find a better solution in the future
-- */
-- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
-+ /* Temporary hack to prevent crashing on PowerMacs when trying to
-+ * write VGA fonts, will find a better solution in the future
-+ */
-+ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE );
- #else
-- vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
-+ vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
- #endif
-- vgaHWLock(hwp);
-- } else {
-- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-- ScrnInfoPtr pScrn0;
-- vgaHWPtr hwp0;
--
-- pScrn0 = pRADEONEnt->pPrimaryScrn;
-- hwp0 = VGAHWPTR(pScrn0);
-- vgaHWUnlock(hwp0);
-- vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
-- vgaHWLock(hwp0);
-+ vgaHWLock(hwp);
-+ } else {
-+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-+ ScrnInfoPtr pScrn0 = pRADEONEnt->pPrimaryScrn;
-+ RADEONInfoPtr info0 = RADEONPTR(pScrn0);
-+ vgaHWPtr hwp0;
-+
-+ if (info0->VGAAccess) {
-+ hwp0 = VGAHWPTR(pScrn0);
-+ vgaHWUnlock(hwp0);
-+#if defined(__powerpc__)
-+ vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE);
-+#else
-+ vgaHWRestore(pScrn0, &hwp0->SavedReg, VGA_SR_MODE | VGA_SR_FONTS );
-+#endif
-+ vgaHWLock(hwp0);
-+ }
-+ }
- }
- RADEONUnblank(pScrn);
-
-@@ -6036,7 +6195,7 @@
- */
- temp = INREG(RADEON_MEM_CNTL);
- data = (R300_MEM_NUM_CHANNELS_MASK & temp);
-- if (data == 2) {
-+ if (data == 1) {
- if (R300_MEM_USE_CD_CH_ONLY & temp) {
- temp = INREG(R300_MC_IND_INDEX);
- temp &= ~R300_MC_IND_ADDR_MASK;
-@@ -6517,8 +6676,13 @@
- ? RADEON_CRTC2_V_SYNC_POL
- : 0));
-
-+ /* We must make sure Tiling is disabled. It seem all other fancy
-+ * options in there can be safely disabled too
-+ */
- save->crtc2_offset = 0;
-- save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
-+ save->crtc2_offset_cntl = 0;
-+
-+
- /* this should be right */
- if (info->MergedFB) {
- save->crtc2_pitch = (((info->CRT2pScrn->displayWidth * pScrn->bitsPerPixel) +
-@@ -6560,6 +6724,23 @@
-
- }
-
-+ /* We must set SURFACE_CNTL properly on the second screen too */
-+ save->surface_cntl = 0;
-+#if X_BYTE_ORDER == X_BIG_ENDIAN
-+ /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */
-+ switch (pScrn->bitsPerPixel) {
-+ case 16:
-+ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
-+ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
-+ break;
-+
-+ case 32:
-+ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
-+ save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
-+ break;
-+ }
-+#endif
-+
- RADEONTRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n",
- save->crtc2_pitch, pScrn->virtualX,
- info->CurrentLayout.displayWidth));
-@@ -6785,8 +6966,8 @@
- }
-
- /* Define PLL registers for requested video mode */
--static void RADEONInitPLLRegisters(RADEONSavePtr save, RADEONPLLPtr pll,
-- double dot_clock)
-+static void RADEONInitPLLRegisters(RADEONInfoPtr info, RADEONSavePtr save,
-+ RADEONPLLPtr pll, double dot_clock)
- {
- unsigned long freq = dot_clock * 100;
-
-@@ -6810,6 +6991,13 @@
- { 0, 0 }
- };
-
-+ if (info->UseBiosDividers) {
-+ save->ppll_ref_div = info->RefDivider;
-+ save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
-+ save->htotal_cntl = 0;
-+ return;
-+ }
-+
- if (freq > pll->max_pll_freq) freq = pll->max_pll_freq;
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
-
-@@ -6844,7 +7032,7 @@
-
- /* Define PLL2 registers for requested video mode */
- static void RADEONInitPLL2Registers(RADEONSavePtr save, RADEONPLLPtr pll,
-- double dot_clock)
-+ double dot_clock, int no_odd_postdiv)
- {
- unsigned long freq = dot_clock * 100;
-
-@@ -6861,7 +7049,7 @@
- { 2, 1 }, /* VCLK_SRC/2 */
- { 4, 2 }, /* VCLK_SRC/4 */
- { 8, 3 }, /* VCLK_SRC/8 */
-- { 3, 4 }, /* VCLK_SRC/3 */
-+ { 3, 4 }, /* VCLK_SRC/3 */
- { 6, 6 }, /* VCLK_SRC/6 */
- { 12, 7 }, /* VCLK_SRC/12 */
- { 0, 0 }
-@@ -6871,6 +7059,11 @@
- if (freq * 12 < pll->min_pll_freq) freq = pll->min_pll_freq / 12;
-
- for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
-+ /* Odd post divider value don't work properly on the second digital
-+ * output
-+ */
-+ if (no_odd_postdiv && (post_div->divider & 1))
-+ continue;
- save->pll_output_freq_2 = post_div->divider * freq;
- if (save->pll_output_freq_2 >= pll->min_pll_freq
- && save->pll_output_freq_2 <= pll->max_pll_freq) break;
-@@ -6971,7 +7164,7 @@
- if (info->IsSecondary) {
- if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))
- return FALSE;
-- RADEONInitPLL2Registers(save, &info->pll, dot_clock);
-+ RADEONInitPLL2Registers(save, &info->pll, dot_clock, info->DisplayType != MT_CRT);
- } else if (info->MergedFB) {
- RADEONInitCommonRegisters(save, info);
- if (!RADEONInitCrtcRegisters(pScrn, save,
-@@ -6979,7 +7172,7 @@
- return FALSE;
- dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0;
- if (dot_clock) {
-- RADEONInitPLLRegisters(save, &info->pll, dot_clock);
-+ RADEONInitPLLRegisters(info, save, &info->pll, dot_clock);
- } else {
- save->ppll_ref_div = info->SavedReg.ppll_ref_div;
- save->ppll_div_3 = info->SavedReg.ppll_div_3;
-@@ -6988,19 +7181,14 @@
- RADEONInitCrtc2Registers(pScrn, save,
- ((RADEONMergedDisplayModePtr)mode->Private)->CRT2, info);
- dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT2)->Clock / 1000.0;
-- RADEONInitPLL2Registers(save, &info->pll, dot_clock);
-+ RADEONInitPLL2Registers(save, &info->pll, dot_clock,
-+ info->MergeType != MT_CRT);
- } else {
- if (!RADEONInitCrtcRegisters(pScrn, save, mode, info))
- return FALSE;
- dot_clock = mode->Clock/1000.0;
- if (dot_clock) {
-- if (info->UseBiosDividers) {
-- save->ppll_ref_div = info->RefDivider;
-- save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16);
-- save->htotal_cntl = 0;
-- }
-- else
-- RADEONInitPLLRegisters(save, &info->pll, dot_clock);
-+ RADEONInitPLLRegisters(info, save, &info->pll, dot_clock);
- } else {
- save->ppll_ref_div = info->SavedReg.ppll_ref_div;
- save->ppll_div_3 = info->SavedReg.ppll_div_3;
-@@ -7406,7 +7594,7 @@
- }
- }
-
-- if (xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
-+ if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
- vgaHWFreeHWRec(pScrn);
- RADEONFreeRec(pScrn);
- }
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