Bug#324765: O: vbpp - Verilog preprocessor
I no longer use the vbs and vbpp packages myself. They need a new
maintainer. Both packges are in good condition, having no bugs.
vbs -- Verilog Behavioral Simulation
Verilog is a Hardware Description Language used mostly for digital
circuit design and simulation. This program is a simple
implementation of a Verilog simulator. VBS tries to implement all of
the Verilog behavioral constructs that are synthesizable, but still
allow complex test vectors for simulation.
vbpp -- Verilog preprocessor
VBPP is a Verilog preprocessor. It has support for most Verilog
preprocessing directives and additional directives such as:
1. Statement generator ('generate' command in VHDL).
2. Expression evaluation.
3. Mathematical functions: log2, ceil, floor, round, abs, etc.
4. Conditionals: if, switch, etc.