Re: Identifying CPU and current OS
On 9/29/25 9:44 AM, Michael Stone wrote:
On Mon, Sep 29, 2025 at 05:26:54AM -0500, Richard Owlett wrote:
Underlying my question was the assumption that when a processor was
referred to as 32 or 64 bit, it was a reference to the width of the
data bus.
Not really, which is why this was a weird/misleading/confusing question.
A "bus" is the physical connection between components in a computer. The
(basically obsolete) phrase "data bus" referred to the physical
connection between the processor and external components. In early
computing the term "N bit computer" conflated a number of concepts
because the systems people were talking about shared a lot of
characteristics. But even at the time it was a bit of a fuzzy term
without clear utility. It might mean a system that used an 8 bit byte
and was byte-addressable, it might mean an 8 bit data bus, it might mean
an 8 bit register size, it might mean 8 bit integer size, etc. Different
architectures used different combinations of these "8 bit" concepts so
there was never a completely clear and logical mapping between the
phrase "8 bit computer" and an actual implementation.
Can't really disagree ;}
My formal computer background is a single undergrad programming course
in '61. I haven't been in a computer environment for over 30 years.
May an octogenarian have some leeway < Chuckle ;>
A very interesting post.
I won't be able to carefully read it until at least this evening.
Thank you for your time.
Are you of my era?
In practical terms "8 bit computer" was shorthand for "computers that
can address 64kB of memory" (a value which was the product of an 8 bit
byte and a 16 bit address bus). Note that the "8 bit" there doesn't have
anything to do with the width of the data bus *or* the address bus. A
clear practical example of this is a comparison of the 8086 and the
8088. Both are byte addressable, both have a 20 bit address bus (so 1MB
rather than 64kB), but the 8086 has a 16 bit data bus and the 8088 has
an 8 bit data bus. Neither of these is generally considered to be an "8
bit computer". The same sort of difference reappeared in the 80386SX,
which was a version of the 80386 with a 16 bit data bus; it was
considered a "32 bit computer", just one with less memory bandwidth.
In more technical terms, "8 bit computer" can more closely map to the
size of an accumulator register in the CPU. That is, in an integer is
implemented as an 8 bit value, such that when you add 1 to 256 it wraps
around to 0. Similarly a "16 bit computer" has a 16 bit integer that
wraps around at 65536. The thing is that this isn't a characteristic
that really matters to users: 8 bit computers were obviously able to
work with numbers larger than 256. It's also another fuzzy concept
because some (but not all) "8 bit" processors could combine registers
and (for example) multiply two 8 bit integers into a 16 bit value.
People using the term "8 bit computer" were not generally talking about
what kind of machine code was used for various arithmetic operations,
which is why in practice the term more reflected the memory limitations
of common implementations.
Looking back to the 8088 in particular and that era of computers
generally, it was common for peripherals to attach to an expansion card
bus that was an extension of the CPU data bus. An 8 bit PC bus (ISA)
card was connected to the 8 bit CPU data bus and operated at the speed
of the CPU. If IBM had gone with an 8086 instead of an 8088 there likely
would have been a 16 bit card bus rather than an 8 bit card bus--which
is exactly what was implemented when the PC/AT was released with a 80286
processor which (like the 8086) had a 16 bit data bus. This was a
user-visible difference, because if both the 8 bit card and the 16 bit
card are operating at the same clock speed, the 16 bit card can transfer
twice as much data per clock (will be twice as fast) as the 8 bit card.
RAM was connected via the same data bus, and performance similarly
reflected how much data could be transferred per clock. (So memory
bandwith in the XT would have been doubled if IBM had gone with the 8086
vs the 8088.) In PC terms the last generation of peripheral bus that
worked like this was the VL bus--this was a 32 bit bus that ran at CPU
clock speed, and it didn't last very long. Even by that time the ISA bus
had been decoupled from the CPU clock because peripheral cards could not
run reliably as CPU clocks increased to 16 or 20MHz instead of the 4
or 8MHz the card expected. The ISA bus was thus
locked at a specific clock speed (typically 8MHz, but there was
variance) and CPU access to the bus was intermediated by a seperate
controller. MCA, EISA, and PCI were all specified independently from the
CPU (VL bus was the oddball even when it was released). As peripherals
were abstracted more from the CPU, a parallel change was that memory was
no longer accessed over the same bus as other peripherals because the
coupling between memory and CPU needed to be faster and more direct than
that between the CPU and other peripherals. The term "data bus" no
longer has any meaning as your expansion cards are connected to a bus
controller via a PCI(e) protocol that operates entirely independently of
the CPU internals while your memory is connected via a completely
different controller tightly integrated with the CPU. What's more,
many modern buses are serial rather than parallel--meaning that the old
concept of "bus width" is irrelevant.
Back to the original question, "what is the width of the data bus of a
modern CPU?" The answer is "none". There's a bus internal to the
processor package which connects CPUs, memory controllers, PCIe
controllers, other controllers such as SATA, etc. It serializes data
transfers, meaning that a logical transfer is broken down into smaller
packets; the length and width of the packets varies across the system
depending on the physical and electrical limitations of a given physical
link. There are multiple PCIe controllers, which in turn include
multiple (serialized) PCIe channels. A PCIe logical link can attain
different bandwidths depending on the physical clock rate of a given
PCIe channel and the number of channels between the controller and the
peripheral. There are multiple memory buses, and memory bandwidth is
determined by the clock speed of the memory, the width of each memory
bus, and the number of memory buses implemented.
In the end, what is the "64" in amd64? It indicates that the CPU
supports instructions which operate on 64 bit general purpose registers.
It also indicates that the CPU instructions are limited to a memory
address length of no more than 64 bits. (I.e., a cpu might implement 36,
40, 48, 52, 57, etc., bits depending upon the intended use of the
processor.)
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