eliminating implicit rules in makefiles

[hendrik@topoi.pooq.com]

How can I disab;e *all* the default rules in my Makefiles?

When I say
	make frith
I don't want it do respond with
	cc frith.c -o frith
even if there is a frith.c file, because that just doesn't work.  Frith needs a lot
more source files to be compiled.  I'd want it to say
	no rule to make frith
or something like it.

Now frith is a machine-dependent file, so I specify something like
	cc -o $(ARCH)/frith frith.c foo.c and so on
which works when I say
	make i686/frith
or
	make x86_64/frith

That's fine.  But even if I say
	frith: $(ARCH)/frith
without any statements to actually make frith,  I have trouble.
Sometimes after I
	make frith
it responds with
	cc -o i686/drith frith.c foo.c and so on
correctly, but then apparently as an afterthough, noticing that frith hasn't ben made yet, 
follows up with
	cc -o frith frith.c

based (presumably) on some build-in implicit rule.

How can I get rid of all these implicit rules, so I only get the ones I speify explicitly?

-- hendrik