Re: Install Fails on T5240

Tony,

Thanks for all the info! I really appreciate it!

On Wed, Sep 3, 2025 at 2:46 PM Tony Rodriguez <unixpro1970@gmail.com> wrote:

Fixed a typo: should be.

--> set /SP/services/http secureredirect=disabled

On 9/2/25 8:58 PM, Tony Rodriguez wrote:

Hi Jeremy,

Update: I was incorrect regarding the dimms they should be 1.8v. Note: The "Samsung M395T5160QZ4-CE66 0819" part number dimms work on my t5140 and t5120.

Pulled my t5140 and t5120 from storage, they are very similar to your t5240. Experienced the same memory related issues, forgot about installing all matching dimms when I put these server away years ago.

Had a mixture of 16 ("Samsung M395T5160QZ4-CE66 0819" and "Samsung M395T5160QZ4-CE66 0816"). Both systems didn't like that. Even though each dimm is 4GB and the part numbers seem similar, the difference with the revision "0819" vs "0816" caused a problem. As such, I filled all 16 dimm slots with only "Samsung M395T5160QZ4-CE66 0819" and memory related errors stopped.

A) Regarding Memory Errors:

use ILOM CLI:

-> show faulty

For example: "show faulty" output shows dimm location /SYS/MB/CMP0/BR0/CH0/D0 as bad. To fix it:

--> set /SYS/MB/CMP0/BR0/CH0/D0 clear_fault_action=true

--> set /SYS/MB/CMP0/BR0/CH0/D0 component_state=Enabled

#you must do this for all devices/components listed within the show faulty output.

--> reset /SP

Yep. I've been doing this when the system does show a faulted component.

Here is what show faulty reports:

None of these seem to be able to be cleared by CLI. Restarting the ILOM clears these until I try to start the host. Sometimes the host starts, sometimes it doesn't. When the host starts it will pass all the verbose diagnostics. When it doesn't it usually just says unsupported memory configuration.

B) Regarding not being able to connect to ilom from a modern web browser with https:

* Will assume you already have ethernet mgmt port configured via ilom.

--> show /SP/network

Note: Disable https and enable http via ilom cli.

-->set /SP/services/http servicestate=enabled

--> set /SP/services/http secureredirect=disabled
--> set /SP/services/https servicestate=disabled

*Please share if you have a better way. Haven't had any luck with newer web browsers connecting to ILOM via https (on older servers like this).

I haven't had an issue connecting to the ILOM. I disabled https via CLI early on.

C) Regarding being unable to connect to the t5140 ethernet mgmt port via ssh. add HostKeyAlgorithms=+ssh-rsa to your ssh.

For example:

ssh root@192.168.21.138

Unable to negotiate with 192.168.18 port 22: no matching host key type found. Their offer: ssh-rsa,ssh-dss

$ ssh -o HostKeyAlgorithms=+ssh-rsa root@192.168.1.18 (use ip of your t5240 management port).

Yep. I've been doing this as well. I'm familiar with this with other older systems as well.

D) Recommend you populate either 8 or 16 dimms according to the following diagram. Otherwise, "show faulty" may generate warnings/errors regarding degraded memory performance.

The following is helpful:

For T5140/T5240:

https://docs.oracle.com/cd/E19712-01/E21412-01/z40002fb1399759.html#z40002fb1400813

For T5120:

https://docs.oracle.com/cd/E19839-01/E21875-01/z40012191414552.html

Thanks for these links.

I have 8 x 4GB FB DIMMS and 8 x 8GB GB DIMMS. These match the specs that were in the docs.

E) Also recommend installing latest Oracle ilom/firmware for your t5240 server. (SysFW 7.4.11 based on ILOM 3.0 147310-15)

https://www.oracle.com/servers/technologies/firmware/release-history-jsp.html#T5240

Unfortunately, I don't have access to download firmware from Oracle. However I do seem to be on the latest firmware:

Sun System Firmware 7.4.11 2017/05/04 15:31

Regards,

Tony

Here is a console log from a successful boot. When this happens the server works fine. But I have to power cycle it several times to get there. Since this last log I haven't been able to get it to successfully boot though.

2025-09-01 02:02:42.620 0:0:0>POST 4.33.6.h 2017/05/04 14:33
2025-09-01 02:02:42.710 0:0:0>
2025-09-01 02:02:42.770 0:0:0>Copyright (c) 2017, Oracle and/or its affiliates. All rights reserved.
2025-09-01 02:02:42.944 0:0:0>vbsc_input_location 000000ff.f0e04388
2025-09-01 02:02:43.041 0:0:0>POST enabling CMP 0 threads: ffffffff.ffffffff
2025-09-01 02:02:43.158 0:0:0>POST enabling CMP 1 threads: ffffffff.ffffffff
2025-09-01 02:02:43.277 0:0:0>VBSC mode is: 00000000.00000001
2025-09-01 02:02:43.370 0:0:0>VBSC level is: 00000000.00000001
2025-09-01 02:02:43.462 0:0:0>VBSC selecting Normal mode, MAX Testing.
2025-09-01 02:02:43.565 0:0:0>VBSC setting verbosity level 3
2025-09-01 02:02:43.653 0:0:0> Victoria Falls, Version 1.3
2025-09-01 02:02:43.740 0:0:0> Serial Number: 3fc9e900.e5823165
2025-09-01 02:02:44.833 0:0:0> CMP 1582 Mhz
2025-09-01 02:02:45.911 0:0:0>Sys 166 MHz, CPU 1582 MHz, Mem 332 MHz
2025-09-01 02:02:46.012 0:0:0>CMP 1582 MHz
2025-09-01 02:02:46.097 0:0:0>Start CMP 1...
2025-09-01 02:02:46.168 1:0:0>NODE 1 present
2025-09-01 02:02:46.233 1:0:0> Victoria Falls, Version 1.3
2025-09-01 02:02:46.319 1:0:0> Serial Number: 4fd1e300.e5823cce
2025-09-01 02:02:47.411 1:0:0> CMP 1582 Mhz
2025-09-01 02:02:47.475 1:0:0>Slave set io stack aid 64
2025-09-01 02:02:47.615 0:0:0>Do 8 meg scrub
2025-09-01 02:02:53.691 0:0:0>End 8 meg scrub
2025-09-01 02:02:53.774 0:0:0>Test Memory.....
2025-09-01 02:02:53.853 0:0:0>Begin: Probe and Setup Memory
2025-09-01 02:02:53.944 0:0:0>INFO: 16384MB at Memory Branch 0
2025-09-01 02:02:54.037 0:0:0>INFO: 16384MB at Memory Branch 1
2025-09-01 02:02:54.131 0:0:0>
2025-09-01 02:02:54.187 0:0:0>End : Probe and Setup Memory
2025-09-01 02:02:54.281 0:0:0>Setup POST Mailbox .....
2025-09-01 02:02:54.372 0:0:0>Begin: Test Mailbox region
2025-09-01 02:02:54.455 0:0:0>..
2025-09-01 02:03:21.433 0:0:0>End : Test Mailbox region
2025-09-01 02:03:21.524 0:0:0>Begin: Set Mailbox
2025-09-01 02:03:27.480 0:0:0>Master CPU Tests Basic.....
2025-09-01 02:03:27.733 0:0:0>CPU =: 0
2025-09-01 02:03:28.100 0:0:0>Begin: DMMU Registers Access
2025-09-01 02:03:28.492 0:0:0>End : DMMU Registers Access
2025-09-01 02:03:28.652 0:0:0>Begin: IMMU Registers Access
2025-09-01 02:03:29.035 0:0:0>End : IMMU Registers Access
2025-09-01 02:03:29.196 0:0:0>Begin: Common MMU regs
2025-09-01 02:03:29.851 0:0:0>End : Common MMU regs
2025-09-01 02:03:30.200 0:0:0>Init MMU.....
2025-09-01 02:03:36.623 0:0:0>Sys 166 MHz, CPU 1582 MHz, Mem 332 MHz
2025-09-01 02:03:36.790 0:0:0>CMP 1582 MHz
2025-09-01 02:03:36.927 0:0:0>Begin: Setup Final DMMU Entries
2025-09-01 02:03:37.268 0:0:0>End : Setup Final DMMU Entries
2025-09-01 02:03:38.003 0:0:0>Copy POST to memory..
2025-09-01 02:03:47.853 0:0:0>Verifying checksum on copied image.
2025-09-01 02:03:48.012 0:0:0>The Memory's CHECKSUM value is e5c9.
2025-09-01 02:03:48.174 0:0:0>The Memory's Content Size value is bcea2.
2025-09-01 02:03:59.632 0:0:0>Success... Checksum on Memory Validated.
2025-09-01 02:03:59.795 0:0:0>Executing out of memory..
2025-09-01 02:04:00.011 1:0:0>INFO: 16384MB at Memory Branch 0
2025-09-01 02:04:00.093 1:0:0>INFO: 16384MB at Memory Branch 1
2025-09-01 02:04:00.176 1:0:0>
2025-09-01 02:04:00.365 0:0:0>CPU =: 0 64
2025-09-01 02:04:00.660 1:0:0>Begin: Setup L2 Cache
2025-09-01 02:04:00.668 1:0:0>End : Setup L2 Cache
2025-09-01 02:04:00.675 0:0:0>L2 Tests.....
2025-09-01 02:04:00.681 1:0:0>Begin: L2 Cache UA Array Test
2025-09-01 02:04:00.688 0:0:0>Begin: Setup L2 Cache
2025-09-01 02:04:00.696 0:0:0>End : Setup L2 Cache
2025-09-01 02:04:00.703 0:0:0>Begin: L2 Cache UA Array Test
2025-09-01 02:04:00.708 1:0:0>End : L2 Cache UA Array Test
2025-09-01 02:04:00.767 1:0:0>Begin: L2 Cache VD Array Test
2025-09-01 02:04:00.773 0:0:0>End : L2 Cache UA Array Test
2025-09-01 02:04:00.828 0:0:0>Begin: L2 Cache VD Array Test
2025-09-01 02:04:00.886 1:0:0>End : L2 Cache VD Array Test
2025-09-01 02:04:00.893 0:0:0>End : L2 Cache VD Array Test
2025-09-01 02:04:00.897 1:0:0>Begin: L2 Cache Tags Test
2025-09-01 02:04:00.903 0:0:0>Begin: L2 Cache Tags Test
2025-09-01 02:04:01.019 0:0:0>End : L2 Cache Tags Test
2025-09-01 02:04:01.024 1:0:0>End : L2 Cache Tags Test
2025-09-01 02:04:01.030 0:0:0>Begin: Scrub and Setup L2 Cache
2025-09-01 02:04:01.036 1:0:0>Begin: Scrub and Setup L2 Cache
2025-09-01 02:04:01.044 0:0:0>L2 Scrub VD & UA
2025-09-01 02:04:01.048 1:0:0>L2 Scrub VD & UA
2025-09-01 02:04:01.053 0:0:0>L2 Scrub Tags
2025-09-01 02:04:01.057 1:0:0>L2 Scrub Tags
2025-09-01 02:04:01.168 0:0:0>End : Scrub and Setup L2 Cache
2025-09-01 02:04:01.174 1:0:0>End : Scrub and Setup L2 Cache
2025-09-01 02:04:01.333 1:0:0>Begin: Wake Core Threads
2025-09-01 02:04:01.510 1:0:0>End : Wake Core Threads
2025-09-01 02:04:03.073 0:0:0>CPU =: 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
2025-09-01 02:04:04.017 0:1:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.124 0:2:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.130 0:3:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.136 0:4:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.141 0:5:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.148 0:6:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.153 0:7:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.159 1:0:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.166 1:1:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.172 1:2:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.180 1:3:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.186 1:4:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.193 1:5:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.199 1:6:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.206 1:7:0>Begin: DMMU Registers Access
2025-09-01 02:04:04.259 0:1:0>End : DMMU Registers Access
2025-09-01 02:04:04.265 0:2:0>End : DMMU Registers Access
2025-09-01 02:04:04.271 0:3:0>End : DMMU Registers Access
2025-09-01 02:04:04.276 0:4:0>End : DMMU Registers Access
2025-09-01 02:04:04.282 0:5:0>End : DMMU Registers Access
2025-09-01 02:04:04.288 0:6:0>End : DMMU Registers Access
2025-09-01 02:04:04.293 0:7:0>End : DMMU Registers Access
2025-09-01 02:04:04.299 1:0:0>End : DMMU Registers Access
2025-09-01 02:04:04.307 1:1:0>End : DMMU Registers Access
2025-09-01 02:04:04.313 1:2:0>End : DMMU Registers Access
2025-09-01 02:04:04.319 1:3:0>End : DMMU Registers Access
2025-09-01 02:04:04.326 1:4:0>End : DMMU Registers Access
2025-09-01 02:04:04.332 1:5:0>End : DMMU Registers Access
2025-09-01 02:04:04.339 1:6:0>End : DMMU Registers Access
2025-09-01 02:04:04.347 1:7:0>End : DMMU Registers Access
2025-09-01 02:04:04.354 0:1:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.360 0:2:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.366 0:3:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.372 0:4:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.377 0:5:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.383 0:6:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.388 0:7:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.394 1:0:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.401 1:1:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.407 1:2:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.414 1:3:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.421 1:4:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.428 1:5:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.434 1:6:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.442 1:7:0>Begin: IMMU Registers Access
2025-09-01 02:04:04.497 0:1:0>End : IMMU Registers Access
2025-09-01 02:04:04.504 0:2:0>End : IMMU Registers Access
2025-09-01 02:04:04.509 0:3:0>End : IMMU Registers Access
2025-09-01 02:04:04.515 0:4:0>End : IMMU Registers Access
2025-09-01 02:04:04.522 0:5:0>End : IMMU Registers Access
2025-09-01 02:04:04.527 0:6:0>End : IMMU Registers Access
2025-09-01 02:04:04.533 0:7:0>End : IMMU Registers Access
2025-09-01 02:04:04.538 1:0:0>End : IMMU Registers Access
2025-09-01 02:04:04.544 1:1:0>End : IMMU Registers Access
2025-09-01 02:04:04.552 1:2:0>End : IMMU Registers Access
2025-09-01 02:04:04.559 1:3:0>End : IMMU Registers Access
2025-09-01 02:04:04.565 1:4:0>End : IMMU Registers Access
2025-09-01 02:04:04.572 1:5:0>End : IMMU Registers Access
2025-09-01 02:04:04.578 1:6:0>End : IMMU Registers Access
2025-09-01 02:04:04.584 1:7:0>End : IMMU Registers Access
2025-09-01 02:04:04.592 0:1:0>Begin: Common MMU regs
2025-09-01 02:04:04.597 0:2:0>Begin: Common MMU regs
2025-09-01 02:04:04.602 0:3:0>Begin: Common MMU regs
2025-09-01 02:04:04.607 0:4:0>Begin: Common MMU regs
2025-09-01 02:04:04.613 0:5:0>Begin: Common MMU regs
2025-09-01 02:04:04.618 0:6:0>Begin: Common MMU regs
2025-09-01 02:04:04.623 0:7:0>Begin: Common MMU regs
2025-09-01 02:04:04.628 1:0:0>Begin: Common MMU regs
2025-09-01 02:04:04.634 1:1:0>Begin: Common MMU regs
2025-09-01 02:04:04.640 1:2:0>Begin: Common MMU regs
2025-09-01 02:04:04.646 1:3:0>Begin: Common MMU regs
2025-09-01 02:04:04.652 1:4:0>Begin: Common MMU regs
2025-09-01 02:04:04.658 1:5:0>Begin: Common MMU regs
2025-09-01 02:04:04.664 1:6:0>Begin: Common MMU regs
2025-09-01 02:04:04.671 1:7:0>Begin: Common MMU regs
2025-09-01 02:04:04.702 0:1:0>End : Common MMU regs
2025-09-01 02:04:04.707 0:2:0>End : Common MMU regs
2025-09-01 02:04:04.737 0:3:0>End : Common MMU regs
2025-09-01 02:04:04.742 0:4:0>End : Common MMU regs
2025-09-01 02:04:04.747 0:5:0>End : Common MMU regs
2025-09-01 02:04:04.752 0:6:0>End : Common MMU regs
2025-09-01 02:04:04.758 0:7:0>End : Common MMU regs
2025-09-01 02:04:04.764 1:0:0>End : Common MMU regs
2025-09-01 02:04:04.770 1:1:0>End : Common MMU regs
2025-09-01 02:04:04.776 1:2:0>End : Common MMU regs
2025-09-01 02:04:04.782 1:3:0>End : Common MMU regs
2025-09-01 02:04:04.788 1:4:0>End : Common MMU regs
2025-09-01 02:04:04.794 1:5:0>End : Common MMU regs
2025-09-01 02:04:04.801 1:6:0>End : Common MMU regs
2025-09-01 02:04:04.806 1:7:0>End : Common MMU regs
2025-09-01 02:04:06.049 0:0:0>Extended CPU Tests.....
2025-09-01 02:04:06.080 0:1:0>Begin: D-Cache RAM
2025-09-01 02:04:06.109 0:2:0>Begin: D-Cache RAM
2025-09-01 02:04:06.114 0:3:0>Begin: D-Cache RAM
2025-09-01 02:04:06.119 0:4:0>Begin: D-Cache RAM
2025-09-01 02:04:06.125 0:5:0>Begin: D-Cache RAM
2025-09-01 02:04:06.130 0:6:0>Begin: D-Cache RAM
2025-09-01 02:04:06.135 0:7:0>Begin: D-Cache RAM
2025-09-01 02:04:06.140 1:0:0>Begin: D-Cache RAM
2025-09-01 02:04:06.146 1:1:0>Begin: D-Cache RAM
2025-09-01 02:04:06.152 1:2:0>Begin: D-Cache RAM
2025-09-01 02:04:06.158 1:3:0>Begin: D-Cache RAM
2025-09-01 02:04:06.163 1:4:0>Begin: D-Cache RAM
2025-09-01 02:04:06.170 1:5:0>Begin: D-Cache RAM
2025-09-01 02:04:06.175 1:6:0>Begin: D-Cache RAM
2025-09-01 02:04:06.181 1:7:0>Begin: D-Cache RAM
2025-09-01 02:04:06.214 0:1:0>End : D-Cache RAM
2025-09-01 02:04:06.220 0:0:0>Begin: D-Cache RAM
2025-09-01 02:04:06.226 0:1:0>Begin: D-Cache Tags
2025-09-01 02:04:06.305 0:1:0>End : D-Cache Tags
2025-09-01 02:04:06.310 0:2:0>End : D-Cache RAM
2025-09-01 02:04:06.315 0:3:0>End : D-Cache RAM
2025-09-01 02:04:06.321 0:4:0>End : D-Cache RAM
2025-09-01 02:04:06.335 0:1:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.340 0:2:0>Begin: D-Cache Tags
2025-09-01 02:04:06.345 0:3:0>Begin: D-Cache Tags
2025-09-01 02:04:06.350 0:4:0>Begin: D-Cache Tags
2025-09-01 02:04:06.354 0:5:0>End : D-Cache RAM
2025-09-01 02:04:06.360 0:6:0>End : D-Cache RAM
2025-09-01 02:04:06.365 0:7:0>End : D-Cache RAM
2025-09-01 02:04:06.370 1:0:0>End : D-Cache RAM
2025-09-01 02:04:06.379 0:0:0>End : D-Cache RAM
2025-09-01 02:04:06.391 0:5:0>Begin: D-Cache Tags
2025-09-01 02:04:06.396 0:6:0>Begin: D-Cache Tags
2025-09-01 02:04:06.401 0:7:0>Begin: D-Cache Tags
2025-09-01 02:04:06.407 1:0:0>Begin: D-Cache Tags
2025-09-01 02:04:06.413 1:1:0>End : D-Cache RAM
2025-09-01 02:04:06.419 1:2:0>End : D-Cache RAM
2025-09-01 02:04:06.432 0:0:0>Begin: D-Cache Tags
2025-09-01 02:04:06.447 1:1:0>Begin: D-Cache Tags
2025-09-01 02:04:06.453 1:2:0>Begin: D-Cache Tags
2025-09-01 02:04:06.460 1:3:0>End : D-Cache RAM
2025-09-01 02:04:06.465 1:4:0>End : D-Cache RAM
2025-09-01 02:04:06.472 1:5:0>End : D-Cache RAM
2025-09-01 02:04:06.479 1:6:0>End : D-Cache RAM
2025-09-01 02:04:06.485 1:7:0>End : D-Cache RAM
2025-09-01 02:04:06.492 0:2:0>End : D-Cache Tags
2025-09-01 02:04:06.498 0:3:0>End : D-Cache Tags
2025-09-01 02:04:06.503 0:4:0>End : D-Cache Tags
2025-09-01 02:04:06.517 1:3:0>Begin: D-Cache Tags
2025-09-01 02:04:06.523 1:4:0>Begin: D-Cache Tags
2025-09-01 02:04:06.529 1:5:0>Begin: D-Cache Tags
2025-09-01 02:04:06.536 1:6:0>Begin: D-Cache Tags
2025-09-01 02:04:06.541 1:7:0>Begin: D-Cache Tags
2025-09-01 02:04:06.550 0:2:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.555 0:3:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.560 0:4:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.565 0:5:0>End : D-Cache Tags
2025-09-01 02:04:06.571 0:6:0>End : D-Cache Tags
2025-09-01 02:04:06.576 0:7:0>End : D-Cache Tags
2025-09-01 02:04:06.581 1:0:0>End : D-Cache Tags
2025-09-01 02:04:06.600 0:0:0>End : D-Cache Tags
2025-09-01 02:04:06.605 0:1:0>End : I-Cache RAM Test
2025-09-01 02:04:06.615 0:5:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.620 0:6:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.625 0:7:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.631 1:0:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.638 1:1:0>End : D-Cache Tags
2025-09-01 02:04:06.644 1:2:0>End : D-Cache Tags
2025-09-01 02:04:06.659 0:0:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.664 0:1:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:06.676 1:1:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.683 1:2:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.689 1:3:0>End : D-Cache Tags
2025-09-01 02:04:06.695 1:4:0>End : D-Cache Tags
2025-09-01 02:04:06.700 1:5:0>End : D-Cache Tags
2025-09-01 02:04:06.707 1:6:0>End : D-Cache Tags
2025-09-01 02:04:06.712 1:7:0>End : D-Cache Tags
2025-09-01 02:04:06.724 1:3:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.731 1:4:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.738 1:5:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.744 1:6:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.750 1:7:0>Begin: I-Cache RAM Test
2025-09-01 02:04:06.767 0:1:0>End : I-Cache Tag RAM
2025-09-01 02:04:06.991 0:2:0>End : I-Cache RAM Test
2025-09-01 02:04:06.997 0:3:0>End : I-Cache RAM Test
2025-09-01 02:04:07.002 0:4:0>End : I-Cache RAM Test
2025-09-01 02:04:07.010 0:2:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.015 0:3:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.021 0:4:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.095 0:0:0>End : I-Cache RAM Test
2025-09-01 02:04:07.100 0:2:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.105 0:3:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.110 0:4:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.115 0:5:0>End : I-Cache RAM Test
2025-09-01 02:04:07.120 0:6:0>End : I-Cache RAM Test
2025-09-01 02:04:07.126 0:7:0>End : I-Cache RAM Test
2025-09-01 02:04:07.131 0:0:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.140 0:5:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.145 0:6:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.151 0:7:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.233 0:0:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.238 0:5:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.243 0:6:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.248 0:7:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.253 1:0:0>End : I-Cache RAM Test
2025-09-01 02:04:07.266 1:0:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.354 1:0:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.361 1:1:0>End : I-Cache RAM Test
2025-09-01 02:04:07.367 1:2:0>End : I-Cache RAM Test
2025-09-01 02:04:07.373 1:3:0>End : I-Cache RAM Test
2025-09-01 02:04:07.379 1:4:0>End : I-Cache RAM Test
2025-09-01 02:04:07.385 1:5:0>End : I-Cache RAM Test
2025-09-01 02:04:07.391 1:6:0>End : I-Cache RAM Test
2025-09-01 02:04:07.397 1:7:0>End : I-Cache RAM Test
2025-09-01 02:04:07.405 1:1:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.411 1:2:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.417 1:3:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.423 1:4:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.428 1:5:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.435 1:6:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.441 1:7:0>Begin: I-Cache Tag RAM
2025-09-01 02:04:07.528 1:1:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.534 1:2:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.540 1:3:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.546 1:4:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.552 1:5:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.559 1:6:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.565 1:7:0>End : I-Cache Tag RAM
2025-09-01 02:04:07.769 1:0:0>Begin: CMP Cache Ram Test
2025-09-01 02:04:07.900 0:0:0>Begin: CMP Cache Ram Test
2025-09-01 02:04:09.899 0:0:0>End : CMP Cache Ram Test
2025-09-01 02:04:09.955 0:0:0>Begin: Enable CMP Cache
2025-09-01 02:04:10.062 0:0:0>Selected mode = 0
2025-09-01 02:04:10.116 0:0:0>L2 Scrub Data
2025-09-01 02:04:10.376 1:0:0>End : CMP Cache Ram Test
2025-09-01 02:04:10.433 1:0:0>Begin: Enable CMP Cache
2025-09-01 02:04:10.542 1:0:0>Selected mode = 0
2025-09-01 02:04:10.597 0:0:0>L2 Enable
2025-09-01 02:04:10.601 1:0:0>L2 Scrub Data
2025-09-01 02:04:10.656 0:0:0>End : Enable CMP Cache
2025-09-01 02:04:11.377 1:0:0>L2 Enable
2025-09-01 02:04:11.482 1:0:0>End : Enable CMP Cache
2025-09-01 02:04:11.638 1:0:0>Begin: Wake All Slave Threads
2025-09-01 02:04:11.881 1:0:0>End : Wake All Slave Threads
2025-09-01 02:04:23.918 0:0:0>CPU =: 0-127
2025-09-01 02:04:24.074 0:0:0>Test slave strand registers...
2025-09-01 02:04:35.106 0:0:0>Scrub Memory.....
2025-09-01 02:04:35.159 0:0:0>Begin: Scrub Memory
2025-09-01 02:04:35.285 0:0:0>Scrub 00000000.10000000->00000010.00000000
2025-09-01 02:04:40.667 0:0:0>End : Scrub Memory
2025-09-01 02:04:41.127 0:0:0>Functional CPU Tests.....
2025-09-01 02:04:41.239 0:0:0>Extended Memory Tests.....
2025-09-01 02:04:41.295 0:0:0>Begin: Print Mem Config
2025-09-01 02:04:41.300 0:0:0>Caches : Icache is ON, Dcache is ON.
2025-09-01 02:04:41.304 0:0:0> Total Memory = 00000000.00000000 -> 00000010.00000000
2025-09-01 02:04:41.309 0:0:0>End : Print Mem Config
2025-09-01 02:04:41.362 0:0:0>Begin: Block Mem Test
2025-09-01 02:04:41.488 0:0:0>Block Mem Test 00000000.10000000->00000010.00000000
2025-09-01 02:04:42.565 0:0:0>........
2025-09-01 02:05:48.383 0:0:0>Testing Gaps..
2025-09-01 02:05:48.437 0:0:0>........
2025-09-01 02:05:56.988 0:0:0>........
2025-09-01 02:06:05.452 0:0:0>........
2025-09-01 02:06:15.094 0:0:0>End : Block Mem Test
2025-09-01 02:06:15.149 0:0:0>Cross Node Memory Test
2025-09-01 02:06:15.204 0:0:0>Target cmp for 0 = 1 MS 00000008.00000000 ME 00000008.40000000
2025-09-01 02:06:15.314 0:0:0>Target cmp for 1 = 0 MS 00000000.10000000 ME 00000000.50000000
2025-09-01 02:06:16.348 0:0:0>........
2025-09-01 02:06:26.762 0:0:0>SPU CWQ Tests...
2025-09-01 02:06:27.350 0:0:0>MAU Tests...
2025-09-01 02:06:28.061 0:1:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.135 0:2:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.188 0:3:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.237 0:4:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.285 0:5:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.338 0:6:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.383 0:7:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.438 1:0:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.485 1:1:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.533 1:2:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.582 1:3:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.632 1:4:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.688 1:5:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.737 1:6:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:28.788 1:7:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:29.388 0:0:0>Begin: FPU Registers and Data Path
2025-09-01 02:06:29.827 0:1:0>End : FPU Registers and Data Path
2025-09-01 02:06:29.865 0:2:0>End : FPU Registers and Data Path
2025-09-01 02:06:29.908 0:3:0>End : FPU Registers and Data Path
2025-09-01 02:06:29.951 0:4:0>End : FPU Registers and Data Path
2025-09-01 02:06:29.997 0:5:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.045 0:6:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.088 0:7:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.136 1:0:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.181 1:1:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.221 1:2:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.261 1:3:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.303 1:4:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.345 1:5:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.390 1:6:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.430 1:7:0>End : FPU Registers and Data Path
2025-09-01 02:06:30.503 0:1:0>Begin: FPU Move Registers
2025-09-01 02:06:30.555 0:2:0>Begin: FPU Move Registers
2025-09-01 02:06:30.605 0:3:0>Begin: FPU Move Registers
2025-09-01 02:06:30.650 0:4:0>Begin: FPU Move Registers
2025-09-01 02:06:30.697 0:5:0>Begin: FPU Move Registers
2025-09-01 02:06:30.730 0:6:0>Begin: FPU Move Registers
2025-09-01 02:06:30.763 0:7:0>Begin: FPU Move Registers
2025-09-01 02:06:30.810 1:0:0>Begin: FPU Move Registers
2025-09-01 02:06:30.853 1:1:0>Begin: FPU Move Registers
2025-09-01 02:06:30.889 1:2:0>Begin: FPU Move Registers
2025-09-01 02:06:30.923 1:3:0>Begin: FPU Move Registers
2025-09-01 02:06:30.957 1:4:0>Begin: FPU Move Registers
2025-09-01 02:06:30.990 1:5:0>Begin: FPU Move Registers
2025-09-01 02:06:31.025 1:6:0>Begin: FPU Move Registers
2025-09-01 02:06:31.058 1:7:0>Begin: FPU Move Registers
2025-09-01 02:06:31.092 0:0:0>End : FPU Registers and Data Path
2025-09-01 02:06:31.624 0:0:0>Begin: FPU Move Registers
2025-09-01 02:06:34.967 0:1:0>End : FPU Move Registers
2025-09-01 02:06:35.028 0:2:0>End : FPU Move Registers
2025-09-01 02:06:35.091 0:3:0>End : FPU Move Registers
2025-09-01 02:06:35.148 0:4:0>End : FPU Move Registers
2025-09-01 02:06:35.211 0:5:0>End : FPU Move Registers
2025-09-01 02:06:35.277 0:6:0>End : FPU Move Registers
2025-09-01 02:06:35.338 0:7:0>End : FPU Move Registers
2025-09-01 02:06:35.397 1:0:0>End : FPU Move Registers
2025-09-01 02:06:35.438 1:1:0>End : FPU Move Registers
2025-09-01 02:06:35.479 1:2:0>End : FPU Move Registers
2025-09-01 02:06:35.517 1:3:0>End : FPU Move Registers
2025-09-01 02:06:35.557 1:4:0>End : FPU Move Registers
2025-09-01 02:06:35.595 1:5:0>End : FPU Move Registers
2025-09-01 02:06:35.635 1:6:0>End : FPU Move Registers
2025-09-01 02:06:35.674 1:7:0>End : FPU Move Registers
2025-09-01 02:06:35.762 0:1:0>Begin: FSR Read/Write
2025-09-01 02:06:35.982 0:2:0>Begin: FSR Read/Write
2025-09-01 02:06:36.326 0:3:0>Begin: FSR Read/Write
2025-09-01 02:06:36.769 0:4:0>Begin: FSR Read/Write
2025-09-01 02:06:37.296 0:5:0>Begin: FSR Read/Write
2025-09-01 02:06:37.897 0:6:0>Begin: FSR Read/Write
2025-09-01 02:06:38.575 0:7:0>Begin: FSR Read/Write
2025-09-01 02:06:39.315 1:0:0>Begin: FSR Read/Write
2025-09-01 02:06:39.441 1:1:0>Begin: FSR Read/Write
2025-09-01 02:06:39.701 1:2:0>Begin: FSR Read/Write
2025-09-01 02:06:40.085 1:3:0>Begin: FSR Read/Write
2025-09-01 02:06:40.571 1:4:0>Begin: FSR Read/Write
2025-09-01 02:06:41.148 1:5:0>Begin: FSR Read/Write
2025-09-01 02:06:41.805 1:6:0>Begin: FSR Read/Write
2025-09-01 02:06:42.541 1:7:0>Begin: FSR Read/Write
2025-09-01 02:06:43.337 0:0:0>End : FPU Move Registers
2025-09-01 02:06:46.057 0:0:0>Begin: FSR Read/Write
2025-09-01 02:06:47.655 0:1:0>End : FSR Read/Write
2025-09-01 02:06:47.661 0:2:0>End : FSR Read/Write
2025-09-01 02:06:47.666 0:3:0>End : FSR Read/Write
2025-09-01 02:06:47.671 0:4:0>End : FSR Read/Write
2025-09-01 02:06:47.675 0:5:0>End : FSR Read/Write
2025-09-01 02:06:47.679 0:6:0>End : FSR Read/Write
2025-09-01 02:06:47.684 0:7:0>End : FSR Read/Write
2025-09-01 02:06:47.689 1:0:0>End : FSR Read/Write
2025-09-01 02:06:47.802 1:1:0>End : FSR Read/Write
2025-09-01 02:06:47.910 1:2:0>End : FSR Read/Write
2025-09-01 02:06:48.016 1:3:0>End : FSR Read/Write
2025-09-01 02:06:48.311 1:4:0>End : FSR Read/Write
2025-09-01 02:06:48.519 1:5:0>End : FSR Read/Write
2025-09-01 02:06:48.638 1:6:0>End : FSR Read/Write
2025-09-01 02:06:48.700 1:7:0>End : FSR Read/Write
2025-09-01 02:06:48.717 0:1:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.721 0:2:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.726 0:3:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.730 0:4:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.735 0:5:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.739 0:6:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.744 0:7:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.749 1:0:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.754 1:1:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.759 1:2:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.764 1:3:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.768 1:4:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.773 1:5:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.778 1:6:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.783 1:7:0>Begin: FPU Branch Instructions
2025-09-01 02:06:48.789 0:0:0>End : FSR Read/Write
2025-09-01 02:06:48.830 0:0:0>Begin: FPU Branch Instructions
2025-09-01 02:06:49.004 0:0:0>End : FPU Branch Instructions
2025-09-01 02:06:49.065 0:1:0>End : FPU Branch Instructions
2025-09-01 02:06:49.070 0:2:0>End : FPU Branch Instructions
2025-09-01 02:06:49.075 0:3:0>End : FPU Branch Instructions
2025-09-01 02:06:49.080 0:4:0>End : FPU Branch Instructions
2025-09-01 02:06:49.085 0:5:0>End : FPU Branch Instructions
2025-09-01 02:06:49.093 0:6:0>End : FPU Branch Instructions
2025-09-01 02:06:49.097 0:7:0>End : FPU Branch Instructions
2025-09-01 02:06:49.101 1:0:0>End : FPU Branch Instructions
2025-09-01 02:06:49.106 1:1:0>End : FPU Branch Instructions
2025-09-01 02:06:49.112 1:2:0>End : FPU Branch Instructions
2025-09-01 02:06:49.116 1:3:0>End : FPU Branch Instructions
2025-09-01 02:06:49.121 1:4:0>End : FPU Branch Instructions
2025-09-01 02:06:49.125 1:5:0>End : FPU Branch Instructions
2025-09-01 02:06:49.130 1:6:0>End : FPU Branch Instructions
2025-09-01 02:06:49.135 1:7:0>End : FPU Branch Instructions
2025-09-01 02:06:49.140 0:0:0>Begin: FPU Functional Test
2025-09-01 02:06:49.144 0:1:0>Begin: FPU Functional Test
2025-09-01 02:06:49.148 0:2:0>Begin: FPU Functional Test
2025-09-01 02:06:49.152 0:3:0>Begin: FPU Functional Test
2025-09-01 02:06:49.157 0:4:0>Begin: FPU Functional Test
2025-09-01 02:06:49.161 0:5:0>Begin: FPU Functional Test
2025-09-01 02:06:49.164 0:6:0>Begin: FPU Functional Test
2025-09-01 02:06:49.169 0:7:0>Begin: FPU Functional Test
2025-09-01 02:06:49.173 1:0:0>Begin: FPU Functional Test
2025-09-01 02:06:49.176 1:1:0>Begin: FPU Functional Test
2025-09-01 02:06:49.181 1:2:0>Begin: FPU Functional Test
2025-09-01 02:06:49.186 1:3:0>Begin: FPU Functional Test
2025-09-01 02:06:49.190 1:4:0>Begin: FPU Functional Test
2025-09-01 02:06:49.194 1:5:0>Begin: FPU Functional Test
2025-09-01 02:06:49.198 1:6:0>Begin: FPU Functional Test
2025-09-01 02:06:49.203 1:7:0>Begin: FPU Functional Test
2025-09-01 02:06:50.450 0:0:0>End : FPU Functional Test
2025-09-01 02:06:50.454 0:1:0>End : FPU Functional Test
2025-09-01 02:06:50.458 0:2:0>End : FPU Functional Test
2025-09-01 02:06:50.463 0:3:0>End : FPU Functional Test
2025-09-01 02:06:50.467 0:4:0>End : FPU Functional Test
2025-09-01 02:06:50.471 0:5:0>End : FPU Functional Test
2025-09-01 02:06:50.476 0:6:0>End : FPU Functional Test
2025-09-01 02:06:50.480 0:7:0>End : FPU Functional Test
2025-09-01 02:06:50.484 1:0:0>End : FPU Functional Test
2025-09-01 02:06:50.488 1:1:0>End : FPU Functional Test
2025-09-01 02:06:50.492 1:2:0>End : FPU Functional Test
2025-09-01 02:06:50.496 1:3:0>End : FPU Functional Test
2025-09-01 02:06:50.501 1:4:0>End : FPU Functional Test
2025-09-01 02:06:50.505 1:5:0>End : FPU Functional Test
2025-09-01 02:06:50.510 1:6:0>End : FPU Functional Test
2025-09-01 02:06:50.515 1:7:0>End : FPU Functional Test
2025-09-01 02:06:50.569 0:0:0>NCU Setup and PIU link train.....
2025-09-01 02:06:50.624 0:0:0>Begin: NCU INIT PCIE Base and Mask Regs.
2025-09-01 02:06:50.840 0:0:0>End : NCU INIT PCIE Base and Mask Regs.
2025-09-01 02:06:50.895 0:0:0>Begin: PIU link train
2025-09-01 02:06:52.401 0:0:0>End : PIU link train
2025-09-01 02:06:52.540 1:0:0>Begin: NCU INIT PCIE Base and Mask Regs.
2025-09-01 02:06:52.756 1:0:0>End : NCU INIT PCIE Base and Mask Regs.
2025-09-01 02:06:52.811 1:0:0>Begin: PIU link train
2025-09-01 02:06:54.317 1:0:0>End : PIU link train
2025-09-01 02:06:54.472 1:0:0>Begin: PIU INT init test
2025-09-01 02:06:54.684 1:0:0>End : PIU INT init test
2025-09-01 02:06:54.737 1:0:0>Begin: PIU MSI init test
2025-09-01 02:06:54.952 1:0:0>End : PIU MSI init test
2025-09-01 02:06:55.005 1:0:0>Begin: PIU ILU init test
2025-09-01 02:06:55.211 1:0:0>End : PIU ILU init test
2025-09-01 02:06:55.265 1:0:0>Begin: PIU TLU init test
2025-09-01 02:06:55.472 1:0:0>End : PIU TLU init test
2025-09-01 02:06:55.526 1:0:0>Begin: PIU PEU init test
2025-09-01 02:06:55.734 1:0:0>End : PIU PEU init test
2025-09-01 02:06:55.788 1:0:0>Begin: PIU intx interrupt test
2025-09-01 02:06:55.952 1:0:0>cpu_interrupt_handler, I/O interrupt.
2025-09-01 02:06:56.099 1:0:0>End : PIU intx interrupt test
2025-09-01 02:06:56.260 0:0:0>Begin: PIU INT init test
2025-09-01 02:06:56.472 0:0:0>End : PIU INT init test
2025-09-01 02:06:56.529 0:0:0>Begin: PIU MSI init test
2025-09-01 02:06:56.744 0:0:0>End : PIU MSI init test
2025-09-01 02:06:56.799 0:0:0>Begin: PIU ILU init test
2025-09-01 02:06:57.006 0:0:0>End : PIU ILU init test
2025-09-01 02:06:57.061 0:0:0>Begin: PIU TLU init test
2025-09-01 02:06:57.268 0:0:0>End : PIU TLU init test
2025-09-01 02:06:57.322 0:0:0>Begin: PIU PEU init test
2025-09-01 02:06:57.529 0:0:0>End : PIU PEU init test
2025-09-01 02:06:57.583 0:0:0>Begin: PIU intx interrupt test
2025-09-01 02:06:57.743 0:0:0>cpu_interrupt_handler, I/O interrupt.
2025-09-01 02:06:57.890 0:0:0>End : PIU intx interrupt test
2025-09-01 02:06:58.045 0:0:0>Begin: Probe PCI Devices
2025-09-01 02:06:58.219 0:0:0>| PLX Switch 8548 Width=0x08 G1 | VID=0x10b5 DID=0x8548 | NODE_0x00 PCI_0x00 Bus_0x02 Dev_0x00 Func_0x00 |
2025-09-01 02:06:58.367 0:0:0>| PLX Switch 8548 Width=0x01 G1 | VID=0x10b5 DID=0x8548 | NODE_0x00 PCI_0x00 Bus_0x03 Dev_0x01 Func_0x00 |
2025-09-01 02:06:58.497 0:0:0>| PLX Bridge 8112 Width=0x01 G1 | VID=0x10b5 DID=0x8112 | NODE_0x00 PCI_0x00 Bus_0x04 Dev_0x00 Func_0x00 |
2025-09-01 02:06:58.626 0:0:0>| NEC USB1.1 Width=0x00 G0 | VID=0x1033 DID=0x0035 | NODE_0x00 PCI_0x00 Bus_0x05 Dev_0x00 Func_0x00 |
2025-09-01 02:06:58.756 0:0:0>| NEC USB1.1 Width=0x00 G0 | VID=0x1033 DID=0x0035 | NODE_0x00 PCI_0x00 Bus_0x05 Dev_0x00 Func_0x01 |
2025-09-01 02:06:58.885 0:0:0>| NEC USB2.0 Width=0x00 G0 | VID=0x1033 DID=0x00e0 | NODE_0x00 PCI_0x00 Bus_0x05 Dev_0x00 Func_0x02 |
2025-09-01 02:07:00.230 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x00 PCI_0x00 Bus_0x03 Dev_0x02 Func_0x00 |
2025-09-01 02:07:01.032 0:0:0>| PLX Switch 8548 Width=0x08 G1 | VID=0x10b5 DID=0x8548 | NODE_0x00 PCI_0x00 Bus_0x03 Dev_0x08 Func_0x00 |
2025-09-01 02:07:01.163 0:0:0>| LSI 1068 PCIE SAS Width=0x08 G1 | VID=0x1000 DID=0x0058 | NODE_0x00 PCI_0x00 Bus_0x07 Dev_0x00 Func_0x00 |
2025-09-01 02:07:01.857 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x00 PCI_0x00 Bus_0x03 Dev_0x09 Func_0x00 |
2025-09-01 02:07:02.604 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x00 PCI_0x00 Bus_0x03 Dev_0x0c Func_0x00 |
2025-09-01 02:07:03.315 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x00 PCI_0x00 Bus_0x03 Dev_0x0d Func_0x00 |
2025-09-01 02:07:04.332 0:0:0>PCIE PROBE Node 0 devices found = 13
2025-09-01 02:07:04.408 0:0:0>| PLX Switch 8548 Width=0x08 G1 | VID=0x10b5 DID=0x8548 | NODE_0x01 PCI_0x00 Bus_0x02 Dev_0x00 Func_0x00 |
2025-09-01 02:07:05.034 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x01 PCI_0x00 Bus_0x03 Dev_0x01 Func_0x00 |
2025-09-01 02:07:05.854 0:0:0>| PLX Switch 8548 Width=0x08 G1 | VID=0x10b5 DID=0x8548 | NODE_0x01 PCI_0x00 Bus_0x03 Dev_0x08 Func_0x00 |
2025-09-01 02:07:05.985 0:0:0>| Neptune GBE Width=0x08 G1 | VID=0x108e DID=0xabcd | NODE_0x01 PCI_0x00 Bus_0x05 Dev_0x00 Func_0x00 |
2025-09-01 02:07:06.117 0:0:0>| Neptune GBE Width=0x08 G1 | VID=0x108e DID=0xabcd | NODE_0x01 PCI_0x00 Bus_0x05 Dev_0x00 Func_0x01 |
2025-09-01 02:07:06.250 0:0:0>| Neptune GBE Width=0x08 G1 | VID=0x108e DID=0xabcd | NODE_0x01 PCI_0x00 Bus_0x05 Dev_0x00 Func_0x02 |
2025-09-01 02:07:06.382 0:0:0>| Neptune GBE Width=0x08 G1 | VID=0x108e DID=0xabcd | NODE_0x01 PCI_0x00 Bus_0x05 Dev_0x00 Func_0x03 |
2025-09-01 02:07:07.270 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x01 PCI_0x00 Bus_0x03 Dev_0x09 Func_0x00 |
2025-09-01 02:07:08.019 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x01 PCI_0x00 Bus_0x03 Dev_0x0c Func_0x00 |
2025-09-01 02:07:08.731 0:0:0>| PLX Switch 8548 Width=0x00 G1 | VID=0x10b5 DID=0x8548 | NODE_0x01 PCI_0x00 Bus_0x03 Dev_0x0d Func_0x00 |
2025-09-01 02:07:09.751 0:0:0>PCIE PROBE Node 1 devices found = 11
2025-09-01 02:07:10.061 0:0:0>PCIE PROBE devices found = 24
2025-09-01 02:07:10.245 0:0:0>End : Probe PCI Devices
2025-09-01 02:07:10.298 0:0:0>Begin: DMA Init
2025-09-01 02:07:10.502 0:0:0>Setting up the System Hbridge IOMMU.
2025-09-01 02:07:10.756 0:0:0>Hbridge DMA Agents Discovery
2025-09-01 02:07:11.074 0:0:0>End : DMA Init
2025-09-01 02:07:11.127 0:0:0>Begin: PIU PCI id test
2025-09-01 02:07:11.384 0:0:0>End : PIU PCI id test
2025-09-01 02:07:11.437 0:0:0>Begin: Network Tests
2025-09-01 02:07:11.700 0:0:0>Testing Network Device: Neptune [MB/CMP1/PCI-SWITCH1/GBE] ...
2025-09-01 02:07:12.358 0:0:0>Neptune Interface Port 0 Tests ...
INIT: Id "ntpd" respawning too fast: disabled for 5 minutes
2025-09-01 02:07:25.929 0:0:0>Neptune Interface Port 1 Tests ...
2025-09-01 02:07:39.494 0:0:0>Neptune Interface Port 2 Tests ...
2025-09-01 02:07:52.498 0:0:0>Neptune Interface Port 3 Tests ...
2025-09-01 02:08:07.754 0:0:0>Begin: XMAC Loopback - Port 0
2025-09-01 02:08:08.799 0:0:0>End : XMAC Loopback - Port 0
2025-09-01 02:08:08.853 0:0:0>Begin: SerDes Loopback - Port 0
2025-09-01 02:08:09.922 0:0:0>End : SerDes Loopback - Port 0
2025-09-01 02:08:09.976 0:0:0>Begin: XMAC Loopback - Port 1
2025-09-01 02:08:11.018 0:0:0>End : XMAC Loopback - Port 1
2025-09-01 02:08:11.073 0:0:0>Begin: SerDes Loopback - Port 1
2025-09-01 02:08:12.144 0:0:0>End : SerDes Loopback - Port 1
2025-09-01 02:08:12.198 0:0:0>Begin: BMAC Loopback - Port 2
2025-09-01 02:08:12.962 0:0:0>End : BMAC Loopback - Port 2
2025-09-01 02:08:13.017 0:0:0>Begin: BMAC Loopback - Port 3
2025-09-01 02:08:13.781 0:0:0>End : BMAC Loopback - Port 3
2025-09-01 02:08:14.514 0:0:0>End : Network Tests
2025-09-01 02:08:14.569 0:0:0>INFO:
2025-09-01 02:08:14.621 0:0:0> POST Passed all devices.
2025-09-01 02:08:14.674 0:0:0>POST: Return to VBSC.
2025-09-01 02:08:14.728 0:0:0>Master set ACK for vbsc runpost command and spin...
|
WARNING: Error updating configuration variable. No space left, check SP and other logs
Configuration variable setting will not persist after a reset or power cycle
/
WARNING: Error storing configuration variable. No space left, check SP and other logs
Configuration variable setting will not persist after a reset or power cycle
-

T5240, No Keyboard
Copyright (c) 1998, 2017, Oracle and/or its affiliates. All rights reserved.
OpenBoot 4.33.6.h, 65312 MB memory available, Serial #95489728.
Ethernet address 0:21:28:b1:e:c0, Host ID: 85b10ec0.

Jeremy Leonard

JeremyL@elite4god.com

Cell: (517) 285-8309