trying the M3000 with Fujitsu SPARC VII+ cpu
Without getting into the silly bits about tftp/rarp setup etc I can tell
you with authority that the file name fetched does NOT have the "SUN4U"
suffix.
Well I was running wireshark elsewhere and watched the whole show up
until packet 15943 :
TFTP: Opcode = 3 (data packet)
TFTP: Data block = 18365 (last block)
TFTP: [ 368 bytes of data ]
The last 62 bytes were :
336: 0000 0000 0001 0000 0000 0000 0000 0000
352: 0011 0000 0003 0000 0000 0000 0000 0000
368: 0000 0000 0000 0000 0000 008f 6df8 0000
384: 0000 0000 01f1 0000 0000 0000 0000 0000
400: 0000 0000 0001 0000 0000 0000 0000
That looks perfect and I did check the sparc64 file.
It was accepted and ack sent :
UDP: ----- UDP Header -----
UDP:
UDP: Source port = 32768
UDP: Destination port = 33105
UDP: Length = 12
UDP: Checksum = ED95
UDP:
TFTP: ----- Trivial File Transfer Protocol -----
TFTP:
TFTP: Opcode = 4 (acknowledgement)
TFTP: Acknowledge block = 18365
Well .. not much good happens after that :-\
{0} ok boot net loglevel=6
Boot device: /pci@0,600000/pci@0/pci@1/network@0 File and args: loglevel=6
100 Mbps full duplex Link up
Requesting Internet Address for 8c:73:6e:c0:59:f8
Requesting Internet Address for 8c:73:6e:c0:59:f8
Requesting Internet Address for 8c:73:6e:c0:59:f8
Requesting Internet Address for 8c:73:6e:c0:59:f8
Requesting Internet Address for 8c:73:6e:c0:59:f8
Requesting Internet Address for 8c:73:6e:c0:59:f8
ERROR: Last Trap: Fast Data Access MMU Miss
%TL:1 %TT:68 %TPC:f000ada4 %TnPC:f000ad94 %TSTATE:6a001600
%PSTATE:16 ( IE:1 PRIV:1 PEF:1 )
DSFSR:4280804b ( FV:1 OW:1 PR:1 E:1 TM:1 ASI:80 NC:1 BERR:1 )
DSFAR:fda61000 DSFPAR:4018006ff000 D-TAG:cf6000
I may have been wrong with the param loglevel but I was hoping to see
more than the above.
Dennis
ps: somewhat annoying in that a system reset takes 5 minutes at least.
Resetting...
POST Sequence 01 CPU Check
POST Sequence 02 Banner
LSB#00 (XSB#00-0): POST 2.17.0 (2011/11/17 10:37)
POST Sequence 03 Fatal Check
POST Sequence 04 CPU Register
POST Sequence 05 STICK
POST Sequence 06 MMU
POST Sequence 07 Memory Initialize
POST Sequence 08 Memory
POST Sequence 09 Raw UE In Cache
POST Sequence 0A Floating Point Unit
POST Sequence 0B SC
POST Sequence 0C Cacheable Instruction
POST Sequence 0D Softint
POST Sequence 0E CPU Cross Call
POST Sequence 0F CMU-CH
POST Sequence 10 PCI-CH
POST Sequence 11 Master Device
POST Sequence 12 DSCP
POST Sequence 13 SC Check Before STICK Diag
POST Sequence 14 STICK Stop
POST Sequence 15 STICK Start
POST Sequence 16 Error CPU Check
POST Sequence 17 System Configuration
POST Sequence 18 System Status Check
POST Sequence 19 System Status Check After Sync
POST Sequence 1A OpenBoot Start...
POST Sequence Complete.
SPARC Enterprise M3000 Server, using Domain console
Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
Copyright (c) 2012, Oracle and/or its affiliates and Fujitsu Limited.
All rights reserved.
OpenBoot 4.33.5.d, 65536 MB memory installed, Serial #BADCAFFE. :-)
Ethernet address 0:b:5d:e2:6f:f6, Host ID: 80996ff6.
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