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Porting SableVM JVM to Sparc



Hi!

I am porting SableVM Java Virtual Machine to sparc platform.
There are two pieces needed.

1. Atomic compare and swap, which I already borrowed from atomicity.h
for sparc32 from glibc6.

static inline jboolean _svmh_compare_and_swap (volatile _svmt_word
 *pword, _svmt_word old_value, _svmt_word new_value)

  register long int result, tmp2;
  static unsigned char lock;
  __asm__ __volatile__("1:      ldstub  [%1], %0\n\t"
                       "        cmp     %0, 0\n\t"
                       "        bne     1b\n\t"
                       "         nop"
                       : "=&r" (tmp2)
                       : "r" (&lock)
                       : "memory");
  if (*pword != old_value)
     result = 0;
  else {
     *pword = new_value;
     result = 1;
  }
  __asm__ __volatile__("stb     %%g0, [%0]"
                       : /* no outputs */
                       : "r" (&lock)
                       : "memory");
           return result;

I've seen other implementations there, but I was getting error:
(Requires v9|v9a|v9b; requested architecture is sparclite.)
So for now I've left is as above.

Is the above implementation correct? Do you think it could/should
be improved somehow (if yes - how? and why?).

2. Instruction cache flush. Because the JVM acts a bit like a compiler
and copies code pieces from one location in memory to another - it needs
to assure, that the icache contains the current version of what was
just written to data memory.

I don't know much about sparc but I was googlin for longer time, looking
at glibc and kernel sparc-specific code. The code I found in kernel was:

icache/include/asm-sparc/pgtable.h
#define flush_icache_page(vma, pg)      do { } while(0)
#define flush_icache_user_range(vma,pg,adr,len)	do { } while (0)
(so it does nothing)

in glibc 2.3.1 sources I found the following pieces:
sysdeps/sparc/sparc32/dl-machine.h
contains function
sparc_fixup_plt (const Elf32_Rela *reloc, Elf32_Addr *reloc_addr,
  Elf32_Addr value, int t)
which in turn contains this (along with 30 lines of C code):
__asm __volatile ("flush %0" : : "r"(reloc_addr));

The question is whether sparc maintains icache<->memory<->dcache
coherency (like on x86 platform) or maybe I should call that
"flush %0" instruction (does it work on all sparcs?), or maybe
sth. else?

I'll be thankful for any help

					Grzegorz B. Prokopski

PS: SableVM already works on Sparc in it's slower mode. I need
proper flush function to make it work in fastest mode (which gives
avg. 2-3 times speedup).

-- 
Grzegorz B. Prokopski <gadek@debian.org>
Debian http://www.debian.org/

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