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Correct TEM mask for Sparc FSR

Can someone confirm or deny for me the normal state of the TEM (trap
enabled mask) bits in the FSR (floating-point status register) in the
Sparc V8 architecture.  Does setting a bit in the TEM enable or
disable the appropriate trap?

I don't have a Sparc V8 manual & am trying to track down a SIGFPE
problem on the Fujistsu TurboSparcs.  The TurboSparc documentations
suggests that you have to set bit to 1 to enable traps, whereas the
glibc pre2.1 code comments suggest the reverse.

I have a hard time believing that Fujitsu got it wrong, but an equally
hard time believing no-one else has run into this.  Maybe there's not
much sparc testing of glibc pre2.1 going on?

Perl is really designed more for the guys that will hack Perl at least
20 minutes a day for the rest of their career.  TCL/Python is more a
"20 minutes a week", and VB is probably in that "20 minutes a month"
group. :) -- Randal Schwartz

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