Bug#758115: Disabled wait state X'32EE' on IPL of zIPL
On Fri, 22 Aug 2014 08:02:42 -0400 (EDT), Michael Holzheu wrote:
>
> You can get a disassembly for the eckd boot loader code when you go
> to s390-tools/zipl/boot and:
>
> 1) make
> 2) objdump -S eckd2.exec > eckd2.list
> ...
>
> static inline int wait(void)
> {
> do {
> load_wait_psw(0x0102000180000000ULL, &S390_lowcore.external_new_psw);
> 33d0: e3 20 d0 00 00 04 lg %r2,0(%r13)
> 33d6: a7 39 01 b0 lghi %r3,432
> 33da: c0 e5 ff ff fc f7 brasl %r14,2dc8 <load_wait_psw>
> if (S390_lowcore.ext_int_code == 0x1004)
> 33e0: e3 10 00 86 00 91 llgh %r1,134
> 33e6: a7 1e 10 04 chi %r1,4100
> 33ea: a7 74 00 06 jne 33f6 <sclp_wait_for_int+0x9a>
> 33ee: a7 28 00 02 lhi %r2,2
> 33f2: a7 f4 00 08 j 3402 <sclp_wait_for_int+0xa6>
> return ETIMEOUT;
> } while (S390_lowcore.ext_int_code != 0x2401);
> 33f6: a7 1e 24 01 chi %r1,9217
> 33fa: a7 74 ff eb jne 33d0 <sclp_wait_for_int+0x74>
> 33fe: a7 28 00 00 lhi %r2,0
>
> Would be interesting how the disassembly looks on your system.
Indeed. Here is what I got:
-----
static inline int wait(void)
{
do {
load_wait_psw(0x0102000180000000ULL, &S390_lowcore.external_new_psw);
32d6: a7 39 01 b0 lghi %r3,432
32da: e3 20 d0 00 00 04 lg %r2,0(%r13)
32e0: c0 e5 ff ff fb b8 brasl %r14,2a50 <load_wait_psw>
if (S390_lowcore.ext_int_code == 0x1004)
32e6: 48 10 00 86 lh %r1,134
32ea: a7 f4 00 01 j 32ec <sclp_wait_for_int+0x84>
32ee: 07 07 nopr %r7
-----
Obviously bad code. Something is terribly wrong here. The complete eckd2.list
file is available for download at
http://users.wowway.com/~zlinuxman/zipl/eckd2.list
It was compiled with gcc version 4.9.1 (Debian 4.9.1-4) on a Debian jessie system.
--
.''`. Stephen Powell
: :' :
`. `'`
`-
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