Source: pcre2 Version: 10.42-4 Severity: wishlist Tags: patch User: debian-riscv@lists.debian.org Usertags: riscv64 X-Debbugs-Cc: debian-riscv@lists.debian.org Dear Maintainer, I backport the upstream commit[0] which to fix sv48/sv57 crashes issue suggested by other riscv64 developers. But in fact, 10.43 has contained the commit[1]. So I think the reportbug should be closed when 10.43 to be uploaded to unstable or if we will update 10.42 in unstable again. So I flags this with wishlist severity. [0]: https://github.com/zherczeg/sljit/pull/223 [1]: https://salsa.debian.org/debian/pcre2/-/blob/10.43/src/sljit/sljitNativeRISCV_common.c?ref_type=tags#L355 -- Regards, -- Bo YU
diff -u pcre2-10.42/debian/changelog pcre2-10.42/debian/changelog
--- pcre2-10.42/debian/changelog
+++ pcre2-10.42/debian/changelog
@@ -1,3 +1,11 @@
+pcre2 (10.42-4.1) UNRELEASED; urgency=medium
+
+ * Non-maintainer upload.
+ * Backport commit from sljit to fix sv48/sv57 crashes on riscv64.
+ (Closes: #-1)
+
+ -- Bo YU <tsu.yubo@gmail.com> Mon, 28 Oct 2024 09:59:14 +0000
+
pcre2 (10.42-4) unstable; urgency=medium
* Build with JIT support on riscv64 (Closes: #1050819)
only in patch2:
unchanged:
--- pcre2-10.42.orig/.pc/.quilt_patches
+++ pcre2-10.42/.pc/.quilt_patches
@@ -0,0 +1 @@
+debian/patches
only in patch2:
unchanged:
--- pcre2-10.42.orig/.pc/.quilt_series
+++ pcre2-10.42/.pc/.quilt_series
@@ -0,0 +1 @@
+series
only in patch2:
unchanged:
--- pcre2-10.42.orig/.pc/.version
+++ pcre2-10.42/.pc/.version
@@ -0,0 +1 @@
+2
only in patch2:
unchanged:
--- pcre2-10.42.orig/debian/patches/fix-sljit-on-riscv64.patch
+++ pcre2-10.42/debian/patches/fix-sljit-on-riscv64.patch
@@ -0,0 +1,28 @@
+Description: backport commit on riscv64
+ This patch fixes getput_arg() and load_addr_to_reg() for large immediate cases.
+Applied-Upstream: https://github.com/zherczeg/sljit/pull/223
+Last-Update: 2024-10-28
+---
+This patch header follows DEP-3: http://dep.debian.net/deps/dep3/
+Index: b/src/sljit/sljitNativeRISCV_common.c
+===================================================================
+--- a/src/sljit/sljitNativeRISCV_common.c
++++ b/src/sljit/sljitNativeRISCV_common.c
+@@ -351,6 +351,8 @@
+ SLJIT_ASSERT(addr <= S52_MAX);
+ inst[0] = LUI | RD(TMP_REG3) | (sljit_ins)(high << 12);
+ } else {
++ if ((high & 0x800) != 0)
++ high += 0x1000;
+ inst[0] = LUI | RD(TMP_REG3) | (sljit_ins)(high & ~0xfff);
+ inst[1] = ADDI | RD(TMP_REG3) | RS1(TMP_REG3) | IMM_I(high);
+ inst++;
+@@ -915,7 +917,7 @@
+
+ /* Since tmp can be the same as base or offset registers,
+ * these might be unavailable after modifying tmp. */
+- if ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA))
++ if ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA) && reg == TMP_REG2)
+ tmp_r = reg;
+
+ if (SLJIT_UNLIKELY(arg & OFFS_REG_MASK)) {
only in patch2:
unchanged:
--- pcre2-10.42.orig/debian/patches/series
+++ pcre2-10.42/debian/patches/series
@@ -0,0 +1 @@
+fix-sljit-on-riscv64.patch
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