Reading Machine ISA
Dear riscv64 porters,
I would like to check if the underlying riscv64 arch is supporting
Vector Extension 1.0. I was told this can be done by checking the misa
value.
However I am getting a SIGILL (again!) with a simple example such as
this one (*)
What did I missed here ? Steps:
$ gcc -g3 -ggdb3 -Wall -Wextra misa.c && ./a.out
Illegal instruction
$ gdb ./a.out
[...]
(gdb) r
Starting program: /home/malaterre/a.out
[Thread debugging using libthread_db enabled]
Using host libthread_db library "/lib/riscv64-linux-gnu/libthread_db.so.1".
Program received signal SIGILL, Illegal instruction.
csr_read_misa () at misa.c:18
18 __asm__ volatile ("csrr %0, misa"
(gdb) bt full
#0 csr_read_misa () at misa.c:18
value = 0
#1 0x0000002aaaaaa68e in main () at misa.c:27
misa = 99
(gdb) i all-r
zero 0x0 0
ra 0x2aaaaaa68e 0x2aaaaaa68e <main+12>
sp 0x3ffffff490 0x3ffffff490
gp 0x2aaaaac800 0x2aaaaac800
tp 0x3ff7fd9370 0x3ff7fd9370
t0 0x3ff7fe2408 274743567368
t1 0x3ff7fef0d0 274743619792
t2 0x3ff7fca310 274743468816
fp 0x3ffffff4b0 0x3ffffff4b0
s1 0x1 1
a0 0x1 1
a1 0x3ffffff658 274877904472
a2 0x3ffffff668 274877904488
a3 0x0 0
a4 0x3ffffff4f0 274877904112
a5 0x2aaaaaa682 183251936898
a6 0x3ff7fcad98 274743471512
a7 0x677c2f5b5a40014e 7456887152421372238
s2 0x0 0
s3 0x2aaaaabe18 183251942936
s4 0x2aaaaaa682 183251936898
s5 0x3ffffff668 274877904488
s6 0x2aaaaabe18 183251942936
s7 0x3ff7ffdd30 274743680304
s8 0x3ff7ffe058 274743681112
s9 0x2aaab97310 183252906768
s10 0x2aaab7ba18 183252793880
s11 0x63 99
t3 0x3ff7eaa988 274742290824
t4 0xd0d0 53456
t5 0x3 3
t6 0xffffffffffffffff -1
pc 0x2aaaaaa66e 0x2aaaaaa66e <csr_read_misa+6>
ft0 {float = 0, double = 0} (raw 0x0000000000000000)
ft1 {float = 0, double = 0} (raw 0x0000000000000000)
ft2 {float = 0, double = 0} (raw 0x0000000000000000)
ft3 {float = 0, double = 0} (raw 0x0000000000000000)
ft4 {float = 0, double = 0} (raw 0x0000000000000000)
ft5 {float = 0, double = 0} (raw 0x0000000000000000)
ft6 {float = 0, double = 0} (raw 0x0000000000000000)
ft7 {float = 0, double = 0} (raw 0x0000000000000000)
fs0 {float = 0, double = 0} (raw 0x0000000000000000)
fs1 {float = 0, double = 0} (raw 0x0000000000000000)
fa0 {float = 0, double = 0} (raw 0x0000000000000000)
fa1 {float = 0, double = 0} (raw 0x0000000000000000)
fa2 {float = 0, double = 0} (raw 0x0000000000000000)
fa3 {float = 0, double = 0} (raw 0x0000000000000000)
fa4 {float = 0, double = 0} (raw 0x0000000000000000)
fa5 {float = 0, double = 0} (raw 0x0000000000000000)
fa6 {float = 0, double = 0} (raw 0x0000000000000000)
fa7 {float = 0, double = 0} (raw 0x0000000000000000)
--Type <RET> for more, q to quit, c to continue without paging--
fs2 {float = 0, double = 0} (raw 0x0000000000000000)
fs3 {float = 0, double = 0} (raw 0x0000000000000000)
fs4 {float = 0, double = 0} (raw 0x0000000000000000)
fs5 {float = 0, double = 0} (raw 0x0000000000000000)
fs6 {float = 0, double = 0} (raw 0x0000000000000000)
fs7 {float = 0, double = 0} (raw 0x0000000000000000)
fs8 {float = 0, double = 0} (raw 0x0000000000000000)
fs9 {float = 0, double = 0} (raw 0x0000000000000000)
fs10 {float = 0, double = 0} (raw 0x0000000000000000)
fs11 {float = 0, double = 0} (raw 0x0000000000000000)
ft8 {float = 0, double = 0} (raw 0x0000000000000000)
ft9 {float = 0, double = 0} (raw 0x0000000000000000)
ft10 {float = 0, double = 0} (raw 0x0000000000000000)
ft11 {float = 0, double = 0} (raw 0x0000000000000000)
fflags <unavailable>
frm <unavailable>
fcsr 0x0 RD:0 NV:0 DZ:0 OF:0 UF:0 NX:0 FRM:0 [RNE
(round to nearest; ties to even)]
and:
[30013.407674] a.out[6501]: unhandled signal 4 code 0x1 at
0x0000002aad52366e in a.out[2aad523000+1000]
[30013.416109] CPU: 2 PID: 6501 Comm: a.out Tainted: G E
5.18.0-2-riscv64 #1 Debian 5.18.5-1
[30013.425652] Hardware name: SiFive HiFive Unmatched A00 (DT)
[30013.431204] epc : 0000002aad52366e ra : 0000002aad52368e sp :
0000003ff75ff4d0
[30013.438412] gp : 0000002aad525800 tp : 0000003f88816370 t0 :
0000003f8881f408
[30013.445617] t1 : 0000003f8882c0d0 t2 : 0000003f88807310 s0 :
0000003ff75ff4f0
[30013.452831] s1 : 0000000000000001 a0 : 0000000000000001 a1 :
0000003ff75ff698
[30013.460038] a2 : 0000003ff75ff6a8 a3 : 0000000000000000 a4 :
0000003ff75ff530
[30013.467255] a5 : 0000002aad523682 a6 : 0000003f88807d98 a7 :
677c2f5b5a40014e
[30013.474459] s2 : 0000000000000000 s3 : 0000002aad524e18 s4 :
0000002aad523682
[30013.481663] s5 : 0000003ff75ff6a8 s6 : 0000002aad524e18 s7 :
0000003f8883ad30
[30013.488876] s8 : 0000003f8883b058 s9 : 0000002ac7284420 s10:
0000002ab3c57858
[30013.496084] s11: 0000002ab3c577c8 t3 : 0000003f886e7988 t4 :
000000000000d0d0
[30013.503300] t5 : 0000000000000003 t6 : ffffffffffffffff
[30013.508589] status: 8000000200006020 badaddr: 00000000301027f3
cause: 0000000000000002
With
$ cat misa.c
#include <stdint.h>
#include <stdio.h>
#if __riscv_xlen==32
typedef uint32_t uint_xlen_t;
#elif __riscv_xlen==64
typedef uint64_t uint_xlen_t;
#else
#error "Unknown XLEN"
#endif
#if !defined(__riscv_zicsr)
#error "-march must include zicsr to access CSRs"
#endif
static inline uint_xlen_t csr_read_misa(void) {
uint_xlen_t value;
__asm__ volatile ("csrr %0, misa"
: "=r" (value) /* output : register */
: /* input : none */
: /* clobbers: none */);
return value;
}
int main()
{
uint_xlen_t misa = csr_read_misa() ;
printf("%lu\n", misa );
}
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