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Bug#892504: [PATCH] nspr: Please add support for the RISC-V architecture



Source: nspr
Version: 2:4.18-1
Severity: wishlist
Tags: patch
X-Debbugs-CC: debian-riscv@lists.debian.org
User: debian-riscv@lists.debian.org
Usertags: riscv64

Hello,

we are in the process of bootstrapping a Debian port for the
riscv64 architecture (https://wiki.debian.org/RISC-V).  The nspr
package is part of the build-dependency chain for the essential
package set, so we need to build it to be able to complete the
bootstrap process.

The nspr upstream currently doesn't have support for the RISC-V
architecture.  I am not familiar with the inner workings of nspr,
but AFAICS the only missing bits appear to be some type
definitions in nspr/pr/include/md/_linux.cfg and the architecture
names in nspr/pr/include/md/_linux.h.  Attached is a patch
against the Debian nspr 2:4.18-1 package that adds the missing
definitions for riscv32 and riscv64 based on the information in
the RISC-V ELF psABI specification:

  https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#default-abis-and-c-type-sizes

There is one thing that I am a bit unsure about, though, and that
is Mozilla's use of WORD and DWORD in their size definitions as I
haven't found any documentation about that.

Unfortunately the use of "word" / "halfword" / "longword" /
"doubleword" / "quadword" varies quite a bit between
architectures and operating systems.  From looking at the
definitions for existing architectures I have inferred that
Mozilla appears to use WORD-size for the native integer register
size and DWORD-size for either twice that (on 32bit platforms) or
also the native integer register size (on 64bit platforms).  If
this is wrong, please let me know so that I can adjust the patch
accordingly.

If the patch looks ok to you, I would apprechiate very much if
you could upload a new version of nspr with the patch applied to
unstable as that would allow us to continue with our bootstrap
efforts.

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.
>From 859830efcf03b5768423fe6956493704e361c40f Mon Sep 17 00:00:00 2001
From: Karsten Merker <merker@debian.org>
Date: Fri, 9 Mar 2018 20:34:57 +0100
Subject: [PATCH] Add definitions for the RISC-V architecture.

---
 ...e-definitions-for-the-RISC-V-architecture.patch | 131 +++++++++++++++++++++
 debian/patches/series                              |   1 +
 2 files changed, 132 insertions(+)
 create mode 100644 debian/patches/Add-type-definitions-for-the-RISC-V-architecture.patch

diff --git a/debian/patches/Add-type-definitions-for-the-RISC-V-architecture.patch b/debian/patches/Add-type-definitions-for-the-RISC-V-architecture.patch
new file mode 100644
index 0000000..49f01b2
--- /dev/null
+++ b/debian/patches/Add-type-definitions-for-the-RISC-V-architecture.patch
@@ -0,0 +1,131 @@
+From d4b3321b5eeb7976a8ca2169128a3754e3b2a8bd Mon Sep 17 00:00:00 2001
+From: Karsten Merker <merker@debian.org>
+Date: Fri, 9 Mar 2018 19:38:12 +0100
+Subject: [PATCH] Add type definitions for the RISC-V architecture.
+
+---
+ nspr/pr/include/md/_linux.cfg | 92 +++++++++++++++++++++++++++++++++++++++++++
+ nspr/pr/include/md/_linux.h   |  4 ++
+ 2 files changed, 96 insertions(+)
+
+diff --git a/nspr/pr/include/md/_linux.cfg b/nspr/pr/include/md/_linux.cfg
+index b4c0ed4..afc407c 100644
+--- a/nspr/pr/include/md/_linux.cfg
++++ b/nspr/pr/include/md/_linux.cfg
+@@ -1020,6 +1020,98 @@
+ #define PR_BYTES_PER_WORD_LOG2   2
+ #define PR_BYTES_PER_DWORD_LOG2  3
+ 
++#elif defined(__riscv) && (__riscv_xlen == 32)
++
++#undef  IS_BIG_ENDIAN
++#define IS_LITTLE_ENDIAN 1
++#undef  IS_64
++
++#define PR_BYTES_PER_BYTE   1
++#define PR_BYTES_PER_SHORT  2
++#define PR_BYTES_PER_INT    4
++#define PR_BYTES_PER_INT64  8
++#define PR_BYTES_PER_LONG   4
++#define PR_BYTES_PER_FLOAT  4
++#define PR_BYTES_PER_DOUBLE 8
++#define PR_BYTES_PER_WORD   4
++#define PR_BYTES_PER_DWORD  8
++
++#define PR_BITS_PER_BYTE    8
++#define PR_BITS_PER_SHORT   16
++#define PR_BITS_PER_INT     32
++#define PR_BITS_PER_INT64   64
++#define PR_BITS_PER_LONG    32
++#define PR_BITS_PER_FLOAT   32
++#define PR_BITS_PER_DOUBLE  64
++#define PR_BITS_PER_WORD    32
++
++#define PR_BITS_PER_BYTE_LOG2   3
++#define PR_BITS_PER_SHORT_LOG2  4
++#define PR_BITS_PER_INT_LOG2    5
++#define PR_BITS_PER_INT64_LOG2  6
++#define PR_BITS_PER_LONG_LOG2   5
++#define PR_BITS_PER_FLOAT_LOG2  5
++#define PR_BITS_PER_DOUBLE_LOG2 6
++#define PR_BITS_PER_WORD_LOG2   5
++
++#define PR_ALIGN_OF_SHORT   2
++#define PR_ALIGN_OF_INT     4
++#define PR_ALIGN_OF_LONG    4
++#define PR_ALIGN_OF_INT64   8
++#define PR_ALIGN_OF_FLOAT   4
++#define PR_ALIGN_OF_DOUBLE  8
++#define PR_ALIGN_OF_POINTER 4
++#define PR_ALIGN_OF_WORD    4
++
++#define PR_BYTES_PER_WORD_LOG2  2
++#define PR_BYTES_PER_DWORD_LOG2 3
++
++#elif defined(__riscv) && (__riscv_xlen == 64)
++
++#undef  IS_BIG_ENDIAN
++#define IS_LITTLE_ENDIAN 1
++#define IS_64
++
++#define PR_BYTES_PER_BYTE   1
++#define PR_BYTES_PER_SHORT  2
++#define PR_BYTES_PER_INT    4
++#define PR_BYTES_PER_INT64  8
++#define PR_BYTES_PER_LONG   8
++#define PR_BYTES_PER_FLOAT  4
++#define PR_BYTES_PER_DOUBLE 8
++#define PR_BYTES_PER_WORD   8
++#define PR_BYTES_PER_DWORD  8
++
++#define PR_BITS_PER_BYTE    8
++#define PR_BITS_PER_SHORT   16
++#define PR_BITS_PER_INT     32
++#define PR_BITS_PER_INT64   64
++#define PR_BITS_PER_LONG    64
++#define PR_BITS_PER_FLOAT   32
++#define PR_BITS_PER_DOUBLE  64
++#define PR_BITS_PER_WORD    64
++
++#define PR_BITS_PER_BYTE_LOG2   3
++#define PR_BITS_PER_SHORT_LOG2  4
++#define PR_BITS_PER_INT_LOG2    5
++#define PR_BITS_PER_INT64_LOG2  6
++#define PR_BITS_PER_LONG_LOG2   6
++#define PR_BITS_PER_FLOAT_LOG2  5
++#define PR_BITS_PER_DOUBLE_LOG2 6
++#define PR_BITS_PER_WORD_LOG2   6
++
++#define PR_ALIGN_OF_SHORT   2
++#define PR_ALIGN_OF_INT     4
++#define PR_ALIGN_OF_LONG    8
++#define PR_ALIGN_OF_INT64   8
++#define PR_ALIGN_OF_FLOAT   4
++#define PR_ALIGN_OF_DOUBLE  8
++#define PR_ALIGN_OF_POINTER 8
++#define PR_ALIGN_OF_WORD    8
++
++#define PR_BYTES_PER_WORD_LOG2  3
++#define PR_BYTES_PER_DWORD_LOG2 3
++
+ #else
+ 
+ #error "Unknown CPU architecture"
+diff --git a/nspr/pr/include/md/_linux.h b/nspr/pr/include/md/_linux.h
+index b4b298b..2370ab8 100644
+--- a/nspr/pr/include/md/_linux.h
++++ b/nspr/pr/include/md/_linux.h
+@@ -57,6 +57,10 @@
+ #define _PR_SI_ARCHITECTURE "m32r"
+ #elif defined(__or1k__)
+ #define _PR_SI_ARCHITECTURE "or1k"
++#elif defined(__riscv) && (__riscv_xlen == 32)
++#define _PR_SI_ARCHITECTURE "riscv32"
++#elif defined(__riscv) && (__riscv_xlen == 64)
++#define _PR_SI_ARCHITECTURE "riscv64"
+ #else
+ #error "Unknown CPU architecture"
+ #endif
+-- 
+2.11.0
+
diff --git a/debian/patches/series b/debian/patches/series
index 58a2faa..384eb55 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1 +1,2 @@
 bz1432638
+Add-type-definitions-for-the-RISC-V-architecture.patch
-- 
2.11.0


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