Bug#771195: (pre-approval) unblock: gcc-arm-none-eabi/4.8.3-13+12
Package: release.debian.org
Severity: normal
User: release.debian.org@packages.debian.org
Usertags: unblock
Hi there,
A new update release of the ARM embedded toolchain was released few days
before the freeze but we missed the deadline due to various reasons
(internal process, holidays, etc.). The update consists solely of
important bugfixes and support for the recently announced Cortex-M7
ARM processors.
I understand that this latter change is against the freeze policy which
is why we haven't uploaded the package to unstable yet but please
consider that it's a quite small change and isolated. It doesn't affect
the current support of other processors and in the worst case it would
only offer a broken support for this new processor. In addition, this is
considered as a minor update by ARM and is rigorously tested on a wide
range of devices.
I would understand and respect any decision you would make but I would
just ask you to consider the toolchain as a whole when making the
decision, i.e. approve or reject the unblock for all 3 [1] packages that
needs updating.
[1] binutils-arm-none-eabi, gcc-arm-none-eabi, gdb-arm-none-eabi
Since a typo in the name of the patch in debian/patches was fixed, the
true debdiff is large. I thus attached a debdiff without the file
renaming part.
unblock gcc-arm-none-eabi/4.8.3-13+12
-- System Information:
Debian Release: jessie/sid
APT prefers unstable
APT policy: (500, 'unstable')
Architecture: amd64 (x86_64)
Kernel: Linux 3.13.0-38-generic (SMP w/8 CPU cores)
Locale: LANG=en_US.UTF-8, LC_CTYPE=en_US.UTF-8 (charmap=UTF-8) (ignored:
LC_ALL set to en_US.UTF-8)
Shell: /bin/sh linked to /bin/dash
diff --git a/debian/changelog b/debian/changelog
index 50c3bd1..a261842 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+gcc-arm-none-eabi (12) UNRELEASED; urgency=medium
+
+ * New upstream release: 4.8-2014-q3-update.
+ * Modify patching so that patches can be version independent.
+
+ -- Thomas Preud'homme <thomas.preudhomme@arm.com> Mon, 20 Oct 2014 10:01:25 +0000
+
gcc-arm-none-eabi (11) unstable; urgency=medium
* Track GCC embedded branch.
diff --git a/debian/patches/0001-Ad-GNU-ARM-embedded-toolchain-patches.patch b/debian/patches/0001-Ad-GNU-ARM-embedded-toolchain-patches.patch
index 19be0f2..f1fed98 100644
--- a/debian/patches/0001-Ad-GNU-ARM-embedded-toolchain-patches.patch
+++ b/debian/patches/0001-Ad-GNU-ARM-embedded-toolchain-patches.patch
@@ -1,9 +1,25 @@
diff --git a/gcc/ChangeLog.arm b/gcc/ChangeLog.arm
new file mode 100644
-index 0000000..8f04bc3
+index 0000000..0ef5a74
--- /dev/null
-+++ b/gcc-4.8.3/gcc/ChangeLog.arm
-@@ -0,0 +1,311 @@
++++ b/gcc/ChangeLog.arm
+@@ -0,0 +1,327 @@
++2014-09-30 Terry Guo <terry.guo@arm.com>
++
++ Backport mainline r215711
++ 2014-09-30 Terry Guo <terry.guo@arm.com>
++
++ * config/arm/arm-cores.def (cortex-m7): New core name.
++ * config/arm/arm-fpus.def (fpv5-sp-d16): New fpu name.
++ (fpv5-d16): Ditto.
++ * config/arm/arm-tables.opt: Regenerated.
++ * config/arm/arm-tune.md: Regenerated.
++ * config/arm/arm.h (TARGET_VFP5): New macro.
++ * config/arm/bpabi.h (BE8_LINK_SPEC): Include cortex-m7.
++ * config/arm/vfp.md (<vrint_pattern><SDF:mode>2,
++ smax<mode>3, smin<mode>3): Enabled for FPU FPv5.
++ * doc/invoke.texi: Document new cpu and fpu names.
++
+2014-02-28 Joey Ye <joey.ye@arm.com>
+
+ Backport mainline r208217
@@ -315,16 +331,10 @@ index 0000000..8f04bc3
+ * configure: Regenerated.
+ * config/arm/t-mlibs: New files to define multilibs.
+ * config.gcc: Use above multilib fragment.
-diff --git a/gcc/DEV-PHASE b/gcc/DEV-PHASE
-index 373fbc6..d702569 100644
---- /dev/null
-+++ b/gcc-4.8.3/gcc/DEV-PHASE
-@@ -0,0 +1,1 @@
-+release
diff --git a/gcc/Makefile.in b/gcc/Makefile.in
index 2a4475b..56b7baa 100644
---- a/gcc-4.8.3/gcc/Makefile.in
-+++ b/gcc-4.8.3/gcc/Makefile.in
+--- a/gcc/Makefile.in
++++ b/gcc/Makefile.in
@@ -526,6 +526,7 @@ lang_opt_files=@lang_opt_files@ $(srcdir)/c-family/c.opt $(srcdir)/common.opt
lang_specs_files=@lang_specs_files@
lang_tree_files=@lang_tree_files@
@@ -337,7 +347,7 @@ diff --git a/gcc/c-family/ChangeLog.arm b/gcc/c-family/ChangeLog.arm
new file mode 100644
index 0000000..056bf52
--- /dev/null
-+++ b/gcc-4.8.3/gcc/c-family/ChangeLog.arm
++++ b/gcc/c-family/ChangeLog.arm
@@ -0,0 +1,8 @@
+2014-07-29 Terry Guo <terry.guo@arm.com>
+
@@ -349,8 +359,8 @@ index 0000000..056bf52
+ * c.opt (fshort-wchar): Likewise.
diff --git a/gcc/c-family/c.opt b/gcc/c-family/c.opt
index 4da80b0..8dfa739 100644
---- a/gcc-4.8.3/gcc/c-family/c.opt
-+++ b/gcc-4.8.3/gcc/c-family/c.opt
+--- a/gcc/c-family/c.opt
++++ b/gcc/c-family/c.opt
@@ -1121,11 +1121,11 @@ C ObjC C++ ObjC++ Optimization Var(flag_short_double)
Use the same size for double as for float
@@ -367,8 +377,8 @@ index 4da80b0..8dfa739 100644
fsigned-bitfields
diff --git a/gcc/calls.c b/gcc/calls.c
index bf0ba30..a066e52 100644
---- a/gcc-4.8.3/gcc/calls.c
-+++ b/gcc-4.8.3/gcc/calls.c
+--- a/gcc/calls.c
++++ b/gcc/calls.c
@@ -1027,7 +1027,7 @@ store_unaligned_arguments_into_pseudos (struct arg_data *args, int num_actuals)
int bitsize = MIN (bytes * BITS_PER_UNIT, BITS_PER_WORD);
@@ -380,8 +390,8 @@ index bf0ba30..a066e52 100644
/* There is no need to restrict this code to loading items
diff --git a/gcc/cfghooks.c b/gcc/cfghooks.c
index 5e3eeb5..0474de7 100644
---- a/gcc-4.8.3/gcc/cfghooks.c
-+++ b/gcc-4.8.3/gcc/cfghooks.c
+--- a/gcc/cfghooks.c
++++ b/gcc/cfghooks.c
@@ -1258,12 +1258,17 @@ end:
/* Duplicates N basic blocks stored in array BBS. Newly created basic blocks
@@ -445,8 +455,8 @@ index 5e3eeb5..0474de7 100644
diff --git a/gcc/cfghooks.h b/gcc/cfghooks.h
index bff0a0c..ec595a5 100644
---- a/gcc-4.8.3/gcc/cfghooks.h
-+++ b/gcc-4.8.3/gcc/cfghooks.h
+--- a/gcc/cfghooks.h
++++ b/gcc/cfghooks.h
@@ -201,7 +201,7 @@ extern void lv_add_condition_to_bb (basic_block, basic_block, basic_block,
extern bool can_copy_bbs_p (basic_block *, unsigned);
extern void copy_bbs (basic_block *, unsigned, basic_block *,
@@ -458,8 +468,8 @@ index bff0a0c..ec595a5 100644
diff --git a/gcc/cfgloopmanip.c b/gcc/cfgloopmanip.c
index 3e53aa0..90df4f0 100644
---- a/gcc-4.8.3/gcc/cfgloopmanip.c
-+++ b/gcc-4.8.3/gcc/cfgloopmanip.c
+--- a/gcc/cfgloopmanip.c
++++ b/gcc/cfgloopmanip.c
@@ -1297,7 +1297,7 @@ duplicate_loop_to_header_edge (struct loop *loop, edge e,
/* Copy bbs. */
@@ -471,8 +481,8 @@ index 3e53aa0..90df4f0 100644
if (flags & DLTHE_RECORD_COPY_NUMBER)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 2b54dd9..16dc35a 100644
---- a/gcc-4.8.3/gcc/config.gcc
-+++ b/gcc-4.8.3/gcc/config.gcc
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
@@ -537,7 +537,11 @@ x86_64-*-*)
fi
tm_file="vxworks-dummy.h ${tm_file}"
@@ -499,7 +509,7 @@ diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-
new file mode 100644
index 0000000..c3652a7
--- /dev/null
-+++ b/gcc-4.8.3/gcc/config/arm/aarch-common-protos.h
++++ b/gcc/config/arm/aarch-common-protos.h
@@ -0,0 +1,134 @@
+/* Functions and structures shared between arm and aarch64.
+
@@ -639,7 +649,7 @@ diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tabl
new file mode 100644
index 0000000..4b36abe
--- /dev/null
-+++ b/gcc-4.8.3/gcc/config/arm/aarch-cost-tables.h
++++ b/gcc/config/arm/aarch-cost-tables.h
@@ -0,0 +1,126 @@
+/* RTX cost tables shared between arm and aarch64.
+
@@ -768,25 +778,39 @@ index 0000000..4b36abe
+#endif /* GCC_AARCH_COST_TABLES_H */
+
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
-index a4cb7c6..ca282e2 100644
---- a/gcc-4.8.3/gcc/config/arm/arm-cores.def
-+++ b/gcc-4.8.3/gcc/config/arm/arm-cores.def
-@@ -132,8 +132,9 @@ ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_D
+index a4cb7c6..146a0f8 100644
+--- a/gcc/config/arm/arm-cores.def
++++ b/gcc/config/arm/arm-cores.def
+@@ -132,8 +132,10 @@ ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_D
ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex)
ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex)
ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
-ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex)
-ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex)
+ARM_CORE("cortex-r7", cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
++ARM_CORE("cortex-m7", cortexm7, 7EM, FL_LDSCHED, v7m)
+ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, v7m)
+ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, v7m)
ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, v6m)
ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, v6m)
ARM_CORE("cortex-m0plus", cortexm0plus, 6M, FL_LDSCHED, v6m)
+diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def
+index 6543942..a8ea1aa 100644
+--- a/gcc/config/arm/arm-fpus.def
++++ b/gcc/config/arm/arm-fpus.def
+@@ -37,6 +37,8 @@ ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true, false)
+ ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false)
+ ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false)
+ ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, false)
++ARM_FPU("fpv5-sp-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, false, true, false)
++ARM_FPU("fpv5-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_D16, false, true, false)
+ ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false)
+ ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false)
+ ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, false)
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index ffa00c0..6605655 100644
---- a/gcc-4.8.3/gcc/config/arm/arm-protos.h
-+++ b/gcc-4.8.3/gcc/config/arm/arm-protos.h
+--- a/gcc/config/arm/arm-protos.h
++++ b/gcc/config/arm/arm-protos.h
@@ -125,6 +125,7 @@ extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx, rtx);
extern rtx arm_gen_return_addr_mask (void);
extern void arm_reload_in_hi (rtx *);
@@ -809,34 +833,66 @@ index ffa00c0..6605655 100644
int constant_limit;
/* Maximum number of instructions to conditionalise in
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
-index 06a529d..ad52d18 100644
---- a/gcc-4.8.3/gcc/config/arm/arm-tables.opt
-+++ b/gcc-4.8.3/gcc/config/arm/arm-tables.opt
-@@ -259,6 +259,9 @@ EnumValue
+index 06a529d..07ffcf6 100644
+--- a/gcc/config/arm/arm-tables.opt
++++ b/gcc/config/arm/arm-tables.opt
+@@ -259,6 +259,12 @@ EnumValue
Enum(processor_type) String(cortex-r5) Value(cortexr5)
EnumValue
+Enum(processor_type) String(cortex-r7) Value(cortexr7)
+
+EnumValue
++Enum(processor_type) String(cortex-m7) Value(cortexm7)
++
++EnumValue
Enum(processor_type) String(cortex-m4) Value(cortexm4)
EnumValue
+@@ -399,17 +405,23 @@ EnumValue
+ Enum(arm_fpu) String(fpv4-sp-d16) Value(11)
+
+ EnumValue
+-Enum(arm_fpu) String(neon-vfpv4) Value(12)
++Enum(arm_fpu) String(fpv5-sp-d16) Value(12)
++
++EnumValue
++Enum(arm_fpu) String(fpv5-d16) Value(13)
++
++EnumValue
++Enum(arm_fpu) String(neon-vfpv4) Value(14)
+
+ EnumValue
+-Enum(arm_fpu) String(fp-armv8) Value(13)
++Enum(arm_fpu) String(fp-armv8) Value(15)
+
+ EnumValue
+-Enum(arm_fpu) String(neon-fp-armv8) Value(14)
++Enum(arm_fpu) String(neon-fp-armv8) Value(16)
+
+ EnumValue
+-Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(15)
++Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(17)
+
+ EnumValue
+-Enum(arm_fpu) String(vfp3) Value(16)
++Enum(arm_fpu) String(vfp3) Value(18)
+
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
-index 26c2e1f..ac85f94 100644
---- a/gcc-4.8.3/gcc/config/arm/arm-tune.md
-+++ b/gcc-4.8.3/gcc/config/arm/arm-tune.md
+index 26c2e1f..9b6158a 100644
+--- a/gcc/config/arm/arm-tune.md
++++ b/gcc/config/arm/arm-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from arm-cores.def
(define_attr "tune"
- "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
-+ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
++ "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa7,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexr7,cortexm7,cortexm4,cortexm3,cortexm1,cortexm0,cortexm0plus,marvell_pj4"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e42d0b9..74f7dca 100644
---- a/gcc-4.8.3/gcc/config/arm/arm.c
-+++ b/gcc-4.8.3/gcc/config/arm/arm.c
+--- a/gcc/config/arm/arm.c
++++ b/gcc/config/arm/arm.c
@@ -264,6 +264,7 @@ static reg_class_t arm_preferred_rename_class (reg_class_t rclass);
static unsigned int arm_autovectorize_vector_sizes (void);
static int arm_default_branch_cost (bool, bool);
@@ -3372,10 +3428,20 @@ index e42d0b9..74f7dca 100644
the function does use far jumps. */
cfun->machine->far_jump_used = 1;
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
-index 63fa3c1..8b15206 100644
---- a/gcc-4.8.3/gcc/config/arm/arm.h
-+++ b/gcc-4.8.3/gcc/config/arm/arm.h
-@@ -324,7 +324,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+index 63fa3c1..093b91b 100644
+--- a/gcc/config/arm/arm.h
++++ b/gcc/config/arm/arm.h
+@@ -280,6 +280,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
+ /* FPU supports VFPv3 instructions. */
+ #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3)
+
++/* FPU supports FPv5 instructions. */
++#define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5)
++
+ /* FPU only supports VFP single-precision instructions. */
+ #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE)
+
+@@ -324,7 +327,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
/* Should MOVW/MOVT be used in preference to a constant pool. */
#define TARGET_USE_MOVT \
@@ -3386,7 +3452,7 @@ index 63fa3c1..8b15206 100644
/* We could use unified syntax for arm mode, but for now we just use it
for Thumb-2. */
-@@ -539,6 +541,11 @@ extern int arm_arch_arm_hwdiv;
+@@ -539,6 +544,11 @@ extern int arm_arch_arm_hwdiv;
/* Nonzero if chip supports integer division instruction in Thumb mode. */
extern int arm_arch_thumb_hwdiv;
@@ -3398,7 +3464,7 @@ index 63fa3c1..8b15206 100644
#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_APCS_FRAME)
#endif
-@@ -553,6 +560,10 @@ extern int arm_arch_thumb_hwdiv;
+@@ -553,6 +563,10 @@ extern int arm_arch_thumb_hwdiv;
#define NEED_PLT_RELOC 0
#endif
@@ -3411,8 +3477,8 @@ index 63fa3c1..8b15206 100644
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 9050ec8..fd10ce8 100644
---- a/gcc-4.8.3/gcc/config/arm/arm.md
-+++ b/gcc-4.8.3/gcc/config/arm/arm.md
+--- a/gcc/config/arm/arm.md
++++ b/gcc/config/arm/arm.md
@@ -63,6 +63,122 @@
;; Processor type. This is created automatically from arm-cores.def.
(include "arm-tune.md")
@@ -3742,8 +3808,8 @@ index 9050ec8..fd10ce8 100644
;; and lo_sum would be merged back into memory load at cprop. However,
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index e778407..ff50283 100644
---- a/gcc-4.8.3/gcc/config/arm/arm.opt
-+++ b/gcc-4.8.3/gcc/config/arm/arm.opt
+--- a/gcc/config/arm/arm.opt
++++ b/gcc/config/arm/arm.opt
@@ -154,6 +154,10 @@ mlong-calls
Target Report Mask(LONG_CALLS)
Generate call insns as indirect calls, if necessary
@@ -3779,10 +3845,32 @@ index e778407..ff50283 100644
munaligned-access
Target Report Var(unaligned_access) Init(2)
Enable unaligned word and halfword accesses to packed data.
+diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h
+index bee429f..1a49772 100644
+--- a/gcc/config/arm/bpabi.h
++++ b/gcc/config/arm/bpabi.h
+@@ -62,7 +62,7 @@
+ |mcpu=marvell-pj4 \
+ |mcpu=generic-armv7-a \
+ |march=armv7-m|mcpu=cortex-m3 \
+- |march=armv7e-m|mcpu=cortex-m4 \
++ |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
+ |march=armv6-m|mcpu=cortex-m0 \
+ |march=armv8-a \
+ :%{!r:--be8}}}"
+@@ -74,7 +74,7 @@
+ |mcpu=marvell-pj4 \
+ |mcpu=generic-armv7-a \
+ |march=armv7-m|mcpu=cortex-m3 \
+- |march=armv7e-m|mcpu=cortex-m4 \
++ |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \
+ |march=armv6-m|mcpu=cortex-m0 \
+ |march=armv8-a \
+ :%{!r:--be8}}}"
diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md
index a1945be..4ce3f10 100644
---- a/gcc-4.8.3/gcc/config/arm/cortex-m4-fpu.md
-+++ b/gcc-4.8.3/gcc/config/arm/cortex-m4-fpu.md
+--- a/gcc/config/arm/cortex-m4-fpu.md
++++ b/gcc/config/arm/cortex-m4-fpu.md
@@ -18,10 +18,14 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
@@ -3832,8 +3920,8 @@ index a1945be..4ce3f10 100644
(and (eq_attr "tune" "cortexm4")
diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md
index 187867b..47b0364 100644
---- a/gcc-4.8.3/gcc/config/arm/cortex-m4.md
-+++ b/gcc-4.8.3/gcc/config/arm/cortex-m4.md
+--- a/gcc/config/arm/cortex-m4.md
++++ b/gcc/config/arm/cortex-m4.md
@@ -84,6 +84,10 @@
(eq_attr "type" "store4"))
"cortex_m4_ex*5")
@@ -3847,10 +3935,10 @@ index 187867b..47b0364 100644
diff --git a/gcc/config/arm/t-mlibs b/gcc/config/arm/t-mlibs
new file mode 100644
-index 0000000..c02118a
+index 0000000..5720cf7
--- /dev/null
-+++ b/gcc-4.8.3/gcc/config/arm/t-mlibs
-@@ -0,0 +1,86 @@
++++ b/gcc/config/arm/t-mlibs
+@@ -0,0 +1,89 @@
+# A set of predefined MULTILIB which can be used for different ARM targets.
+# Via the configure option --with-multilib-list, user can customize the
+# final MULTILIB implementation.
@@ -3874,6 +3962,7 @@ index 0000000..c02118a
+MULTILIB_MATCHES += march?armv6s-m=march?armv6-m
+MULTILIB_MATCHES += march?armv7-m=mcpu?cortex-m3
+MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m4
++MULTILIB_MATCHES += march?armv7e-m=mcpu?cortex-m7
+MULTILIB_MATCHES += march?armv7=march?armv7-r
+MULTILIB_MATCHES += march?armv7=march?armv7-a
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4
@@ -3885,6 +3974,8 @@ index 0000000..c02118a
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a9
+MULTILIB_MATCHES += march?armv7=mcpu?cortex-a15
++MULTILIB_MATCHES += mfpu?fpv4-sp-d16=mfpu?fpv5-sp-d16
++MULTILIB_MATCHES += mfpu?fpv4-sp-d16=mfpu?fpv5-d16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16
+MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-d16-fp16
@@ -3937,10 +4028,41 @@ index 0000000..c02118a
+MULTILIB_REUSE += mthumb/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d16=marm/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d16
+MULTILIB_REUSE += mthumb/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16=marm/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16
+endif
+diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
+index 13e151f..a6e7f48 100644
+--- a/gcc/config/arm/vfp.md
++++ b/gcc/config/arm/vfp.md
+@@ -1261,7 +1261,7 @@
+ (unspec:SDF [(match_operand:SDF 1
+ "register_operand" "<F_constraint>")]
+ VRINT))]
+- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
++ "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
+ "vrint<vrint_variant>%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1"
+ [(set_attr "predicable" "<vrint_predicable>")
+ (set_attr "conds" "<vrint_conds>")
+@@ -1279,7 +1279,7 @@
+ [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ (smax:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+ (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
+- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
++ "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
+ "vmaxnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+ [(set_attr "type" "f_minmax<vfp_type>")
+ (set_attr "conds" "unconditional")]
+@@ -1289,7 +1289,7 @@
+ [(set (match_operand:SDF 0 "register_operand" "=<F_constraint>")
+ (smin:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
+ (match_operand:SDF 2 "register_operand" "<F_constraint>")))]
+- "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 <vfp_double_cond>"
++ "TARGET_HARD_FLOAT && TARGET_VFP5 <vfp_double_cond>"
+ "vminnm.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+ [(set_attr "type" "f_minmax<vfp_type>")
+ (set_attr "conds" "unconditional")]
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index 502b953..be93a69 100644
---- a/gcc-4.8.3/gcc/config/tilegx/tilegx.c
-+++ b/gcc-4.8.3/gcc/config/tilegx/tilegx.c
+--- a/gcc/config/tilegx/tilegx.c
++++ b/gcc/config/tilegx/tilegx.c
@@ -1882,7 +1882,7 @@ tilegx_expand_unaligned_load (rtx dest_reg, rtx mem, HOST_WIDE_INT bitsize,
rtx extracted =
extract_bit_field (gen_lowpart (DImode, wide_result),
@@ -3952,8 +4074,8 @@ index 502b953..be93a69 100644
if (extracted != dest_reg)
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index 957146d..42ce1c7 100644
---- a/gcc-4.8.3/gcc/config/tilepro/tilepro.c
-+++ b/gcc-4.8.3/gcc/config/tilepro/tilepro.c
+--- a/gcc/config/tilepro/tilepro.c
++++ b/gcc/config/tilepro/tilepro.c
@@ -1676,7 +1676,7 @@ tilepro_expand_unaligned_load (rtx dest_reg, rtx mem, HOST_WIDE_INT bitsize,
rtx extracted =
extract_bit_field (gen_lowpart (SImode, wide_result),
@@ -3965,8 +4087,8 @@ index 957146d..42ce1c7 100644
if (extracted != dest_reg)
diff --git a/gcc/configure b/gcc/configure
index 3793681..177906f 100755
---- a/gcc-4.8.3/gcc/configure
-+++ b/gcc-4.8.3/gcc/configure
+--- a/gcc/configure
++++ b/gcc/configure
@@ -753,6 +753,7 @@ LN
LN_S
AWK
@@ -4012,8 +4134,8 @@ index 3793681..177906f 100755
#if HAVE_DLFCN_H
diff --git a/gcc/configure.ac b/gcc/configure.ac
index 3ee1d67..07c127e 100644
---- a/gcc-4.8.3/gcc/configure.ac
-+++ b/gcc-4.8.3/gcc/configure.ac
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
@@ -839,9 +839,10 @@ esac],
[enable_languages=c])
@@ -4028,8 +4150,8 @@ index 3ee1d67..07c127e 100644
# Checks for other programs
diff --git a/gcc/expmed.c b/gcc/expmed.c
index 8a6e4b9..9aa3326 100644
---- a/gcc-4.8.3/gcc/expmed.c
-+++ b/gcc-4.8.3/gcc/expmed.c
+--- a/gcc/expmed.c
++++ b/gcc/expmed.c
@@ -47,6 +47,9 @@ static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
unsigned HOST_WIDE_INT,
unsigned HOST_WIDE_INT,
@@ -4516,8 +4638,8 @@ index 8a6e4b9..9aa3326 100644
/* Shift this part into place for the result. */
diff --git a/gcc/expr.c b/gcc/expr.c
index 01697e9..94b3238 100644
---- a/gcc-4.8.3/gcc/expr.c
-+++ b/gcc-4.8.3/gcc/expr.c
+--- a/gcc/expr.c
++++ b/gcc/expr.c
@@ -1704,7 +1704,7 @@ emit_group_load_1 (rtx *tmps, rtx dst, rtx orig_src, tree type, int ssize)
&& (!REG_P (tmps[i]) || GET_MODE (tmps[i]) != mode))
tmps[i] = extract_bit_field (tmps[i], bytelen * BITS_PER_UNIT,
@@ -4680,8 +4802,8 @@ index 01697e9..94b3238 100644
ext_mode, ext_mode);
diff --git a/gcc/expr.h b/gcc/expr.h
index 98c9dae..0b36638 100644
---- a/gcc-4.8.3/gcc/expr.h
-+++ b/gcc-4.8.3/gcc/expr.h
+--- a/gcc/expr.h
++++ b/gcc/expr.h
@@ -704,7 +704,7 @@ extern void store_bit_field (rtx, unsigned HOST_WIDE_INT,
unsigned HOST_WIDE_INT,
enum machine_mode, rtx);
@@ -4693,8 +4815,8 @@ index 98c9dae..0b36638 100644
extern rtx expand_mult (enum machine_mode, rtx, rtx, rtx, int);
diff --git a/gcc/gimple.h b/gcc/gimple.h
index 4985446..bf659d9 100644
---- a/gcc-4.8.3/gcc/gimple.h
-+++ b/gcc-4.8.3/gcc/gimple.h
+--- a/gcc/gimple.h
++++ b/gcc/gimple.h
@@ -1036,6 +1036,9 @@ extern tree tree_ssa_strip_useless_type_conversions (tree);
extern bool useless_type_conversion_p (tree, tree);
extern bool types_compatible_p (tree, tree);
@@ -4709,7 +4831,7 @@ diff --git a/gcc/testsuite/ChangeLog.arm b/gcc/testsuite/ChangeLog.arm
new file mode 100644
index 0000000..14305a5
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/ChangeLog.arm
++++ b/gcc/testsuite/ChangeLog.arm
@@ -0,0 +1,89 @@
+2014-07-29 Terry Guo <terry.guo@arm.com>
+
@@ -4804,7 +4926,7 @@ diff --git a/gcc/testsuite/gcc.c-torture/compile/pr59134.c b/gcc/testsuite/gcc.c
new file mode 100644
index 0000000..5268805
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.c-torture/compile/pr59134.c
++++ b/gcc/testsuite/gcc.c-torture/compile/pr59134.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+
@@ -4826,7 +4948,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr23623.c b/gcc/testsuite/gcc.dg/pr23623.c
new file mode 100644
index 0000000..c844f94
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr23623.c
++++ b/gcc/testsuite/gcc.dg/pr23623.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-fstrict-volatile-bitfields -fdump-rtl-final" } */
@@ -4880,7 +5002,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr48784-1.c b/gcc/testsuite/gcc.dg/pr48784-1.c
new file mode 100644
index 0000000..bbcad9b
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr48784-1.c
++++ b/gcc/testsuite/gcc.dg/pr48784-1.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-fstrict-volatile-bitfields" } */
@@ -4904,7 +5026,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr48784-2.c b/gcc/testsuite/gcc.dg/pr48784-2.c
new file mode 100644
index 0000000..6d53263
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr48784-2.c
++++ b/gcc/testsuite/gcc.dg/pr48784-2.c
@@ -0,0 +1,18 @@
+/* { dg-do run } */
+/* { dg-options "-fno-strict-volatile-bitfields" } */
@@ -4928,7 +5050,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr56341-1.c b/gcc/testsuite/gcc.dg/pr56341-1.c
new file mode 100644
index 0000000..91cf80b
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr56341-1.c
++++ b/gcc/testsuite/gcc.dg/pr56341-1.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-fstrict-volatile-bitfields" } */
@@ -4974,7 +5096,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr56341-2.c b/gcc/testsuite/gcc.dg/pr56341-2.c
new file mode 100644
index 0000000..e6f6569
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr56341-2.c
++++ b/gcc/testsuite/gcc.dg/pr56341-2.c
@@ -0,0 +1,40 @@
+/* { dg-do run } */
+/* { dg-options "-fno-strict-volatile-bitfields" } */
@@ -5020,7 +5142,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr56997-1.c b/gcc/testsuite/gcc.dg/pr56997-1.c
new file mode 100644
index 0000000..42458a1
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr56997-1.c
++++ b/gcc/testsuite/gcc.dg/pr56997-1.c
@@ -0,0 +1,44 @@
+/* Test volatile access to unaligned field. */
+/* { dg-do run } */
@@ -5070,7 +5192,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr56997-2.c b/gcc/testsuite/gcc.dg/pr56997-2.c
new file mode 100644
index 0000000..08e6311
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr56997-2.c
++++ b/gcc/testsuite/gcc.dg/pr56997-2.c
@@ -0,0 +1,44 @@
+/* Test volatile access to unaligned field. */
+/* { dg-do run } */
@@ -5120,7 +5242,7 @@ diff --git a/gcc/testsuite/gcc.dg/pr56997-3.c b/gcc/testsuite/gcc.dg/pr56997-3.c
new file mode 100644
index 0000000..3754b10
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/pr56997-3.c
++++ b/gcc/testsuite/gcc.dg/pr56997-3.c
@@ -0,0 +1,44 @@
+/* Test volatile access to unaligned field. */
+/* { dg-do run } */
@@ -5170,7 +5292,7 @@ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/coalesce-1.c b/gcc/testsuite/gcc.dg/t
new file mode 100644
index 0000000..5cae9ae
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/tree-ssa/coalesce-1.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/coalesce-1.c
@@ -0,0 +1,195 @@
+/* { dg-do compile } */
+
@@ -5369,8 +5491,8 @@ index 0000000..5cae9ae
+
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c
index bf4f0f3..bda9fd5 100644
---- a/gcc-4.8.3/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c
+--- a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c
++++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c
@@ -6,10 +6,10 @@
/* { dg-do compile { target { ! "mips*-*-* s390*-*-* avr-*-* mn10300-*-*" } } } */
/* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-dom1 -fdump-tree-dom2" } */
@@ -5388,7 +5510,7 @@ diff --git a/gcc/testsuite/gcc.target/arm/lto/lto.exp b/gcc/testsuite/gcc.target
new file mode 100644
index 0000000..7513411
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.target/arm/lto/lto.exp
++++ b/gcc/testsuite/gcc.target/arm/lto/lto.exp
@@ -0,0 +1,59 @@
+# Copyright (C) 2009-2014 Free Software Foundation, Inc.
+
@@ -5453,7 +5575,7 @@ diff --git a/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c b/gcc/testsu
new file mode 100644
index 0000000..c23f9d8
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c
++++ b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_0.c
@@ -0,0 +1,22 @@
+/* { dg-lto-do link } */
+/* { dg-lto-options { { -fno-short-enums -Wl,-Ur,--no-enum-size-warning -Os -nostdlib -flto } } } */
@@ -5481,7 +5603,7 @@ diff --git a/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_1.c b/gcc/testsu
new file mode 100644
index 0000000..9561efa
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_1.c
++++ b/gcc/testsuite/gcc.target/arm/lto/pr61123-enum-size_1.c
@@ -0,0 +1,5 @@
+int
+foo2 (int y)
@@ -5492,7 +5614,7 @@ diff --git a/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c b/gcc/testsuite/gc
new file mode 100644
index 0000000..eb16d2f
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c
++++ b/gcc/testsuite/gcc.target/arm/thumb1-far-jump-1.c
@@ -0,0 +1,34 @@
+/* Check for thumb1 far jump. Shouldn't save lr for small leaf functions
+ * even with a branch in it. */
@@ -5532,7 +5654,7 @@ diff --git a/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c b/gcc/testsuite/gc
new file mode 100644
index 0000000..c6878f8
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c
++++ b/gcc/testsuite/gcc.target/arm/thumb1-far-jump-2.c
@@ -0,0 +1,57 @@
+/* Check for thumb1 far jump. This is the extreme case that far jump
+ * will be used with minimum number of instructions. By passing this case
@@ -5595,7 +5717,7 @@ diff --git a/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c b/gcc/testsuite/gc
new file mode 100644
index 0000000..1b1c717
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c
++++ b/gcc/testsuite/gcc.target/arm/thumb1-far-jump-3.c
@@ -0,0 +1,105 @@
+/* Catch reload ICE on target thumb1 with far jump optimization.
+ * It is also a valid case for non-thumb1 target. */
@@ -5706,7 +5828,7 @@ diff --git a/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c b/gcc/testsui
new file mode 100644
index 0000000..9852ea5
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c
++++ b/gcc/testsuite/gcc.target/arm/thumb2-slow-flash-data.c
@@ -0,0 +1,74 @@
+/* The option -mslow-flash-data is just for performance tuning, it
+ doesn't totally disable the use of literal pools. But for below
@@ -5786,7 +5908,7 @@ diff --git a/gcc/testsuite/gnat.dg/misaligned_volatile.adb b/gcc/testsuite/gnat.
new file mode 100644
index 0000000..c76975b
--- /dev/null
-+++ b/gcc-4.8.3/gcc/testsuite/gnat.dg/misaligned_volatile.adb
++++ b/gcc/testsuite/gnat.dg/misaligned_volatile.adb
@@ -0,0 +1,28 @@
+-- { dg-do run }
+-- { dg-options "-gnatp -fstrict-volatile-bitfields" }
@@ -5818,8 +5940,8 @@ index 0000000..c76975b
+end;
diff --git a/gcc/testsuite/lib/lto.exp b/gcc/testsuite/lib/lto.exp
index 8c2db33..b2e3fde 100644
---- a/gcc-4.8.3/gcc/testsuite/lib/lto.exp
-+++ b/gcc-4.8.3/gcc/testsuite/lib/lto.exp
+--- a/gcc/testsuite/lib/lto.exp
++++ b/gcc/testsuite/lib/lto.exp
@@ -633,3 +633,82 @@ proc scan-symbol { args } {
fail "scan-symbol $args"
}
@@ -5905,8 +6027,8 @@ index 8c2db33..b2e3fde 100644
+
diff --git a/gcc/trans-mem.c b/gcc/trans-mem.c
index b0f18b5..1b0b088 100644
---- a/gcc-4.8.3/gcc/trans-mem.c
-+++ b/gcc-4.8.3/gcc/trans-mem.c
+--- a/gcc/trans-mem.c
++++ b/gcc/trans-mem.c
@@ -3941,7 +3941,8 @@ ipa_uninstrument_transaction (struct tm_region *region,
int n = queue.length ();
basic_block *new_bbs = XNEWVEC (basic_block, n);
@@ -5919,8 +6041,8 @@ index b0f18b5..1b0b088 100644
diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c
index b32da2e..9d8014d 100644
---- a/gcc-4.8.3/gcc/tree-cfg.c
-+++ b/gcc-4.8.3/gcc/tree-cfg.c
+--- a/gcc/tree-cfg.c
++++ b/gcc/tree-cfg.c
@@ -5620,16 +5620,19 @@ add_phi_args_after_copy (basic_block *region_copy, unsigned n_region,
inside region is live over the other exit edges of the region. All entry
edges to the region must go to ENTRY->dest. The edge ENTRY is redirected
@@ -6003,8 +6125,8 @@ index b32da2e..9d8014d 100644
scale_bbs_frequencies_gcov_type (region, n_region,
diff --git a/gcc/tree-flow.h b/gcc/tree-flow.h
index e0aef5b..b6af4cc 100644
---- a/gcc-4.8.3/gcc/tree-flow.h
-+++ b/gcc-4.8.3/gcc/tree-flow.h
+--- a/gcc/tree-flow.h
++++ b/gcc/tree-flow.h
@@ -397,7 +397,7 @@ extern void verify_gimple_in_cfg (struct function *);
extern tree gimple_block_label (basic_block);
extern void extract_true_false_edges_from_block (basic_block, edge *, edge *);
@@ -6016,8 +6138,8 @@ index e0aef5b..b6af4cc 100644
extern void gather_blocks_in_sese_region (basic_block entry, basic_block exit,
diff --git a/gcc/tree-ssa-coalesce.c b/gcc/tree-ssa-coalesce.c
index fd9c2cb..1fada6a 100644
---- a/gcc-4.8.3/gcc/tree-ssa-coalesce.c
-+++ b/gcc-4.8.3/gcc/tree-ssa-coalesce.c
+--- a/gcc/tree-ssa-coalesce.c
++++ b/gcc/tree-ssa-coalesce.c
@@ -979,8 +979,7 @@ create_outofssa_var_map (coalesce_list_p cl, bitmap used_in_copy)
continue;
@@ -6109,8 +6231,8 @@ index fd9c2cb..1fada6a 100644
+}
diff --git a/gcc/tree-ssa-live.c b/gcc/tree-ssa-live.c
index 8456d7a..8794569 100644
---- a/gcc-4.8.3/gcc/tree-ssa-live.c
-+++ b/gcc-4.8.3/gcc/tree-ssa-live.c
+--- a/gcc/tree-ssa-live.c
++++ b/gcc/tree-ssa-live.c
@@ -88,8 +88,12 @@ var_map_base_init (var_map map)
as it restricts the sets we compute conflicts for.
Using TREE_TYPE to generate sets is the easies as
@@ -6128,8 +6250,8 @@ index 8456d7a..8794569 100644
m, INSERT);
diff --git a/gcc/tree-ssa-loop-ch.c b/gcc/tree-ssa-loop-ch.c
index b8dd1a3..82e14e6 100644
---- a/gcc-4.8.3/gcc/tree-ssa-loop-ch.c
-+++ b/gcc-4.8.3/gcc/tree-ssa-loop-ch.c
+--- a/gcc/tree-ssa-loop-ch.c
++++ b/gcc/tree-ssa-loop-ch.c
@@ -197,7 +197,8 @@ copy_loop_headers (void)
entry = loop_preheader_edge (loop);
@@ -6142,8 +6264,8 @@ index b8dd1a3..82e14e6 100644
continue;
diff --git a/gcc/tree-ssa-uncprop.c b/gcc/tree-ssa-uncprop.c
index c7eed9e..318985f 100644
---- a/gcc-4.8.3/gcc/tree-ssa-uncprop.c
-+++ b/gcc-4.8.3/gcc/tree-ssa-uncprop.c
+--- a/gcc/tree-ssa-uncprop.c
++++ b/gcc/tree-ssa-uncprop.c
@@ -466,12 +466,11 @@ uncprop_into_successor_phis (basic_block bb)
struct equiv_hash_elt equiv_hash_elt;
void **slot;
@@ -6182,8 +6304,8 @@ index c7eed9e..318985f 100644
break;
diff --git a/gcc/tree-vect-loop-manip.c b/gcc/tree-vect-loop-manip.c
index 559f6e9..64271a0 100644
---- a/gcc-4.8.3/gcc/tree-vect-loop-manip.c
-+++ b/gcc-4.8.3/gcc/tree-vect-loop-manip.c
+--- a/gcc/tree-vect-loop-manip.c
++++ b/gcc/tree-vect-loop-manip.c
@@ -735,7 +735,7 @@ slpeel_tree_duplicate_loop_to_edge_cfg (struct loop *loop, edge e)
copy_bbs (bbs, loop->num_nodes + 1, new_bbs,
@@ -6197,7 +6319,7 @@ diff --git a/libcpp/ChangeLog.arm b/libcpp/ChangeLog.arm
new file mode 100644
index 0000000..b8cff8a
--- /dev/null
-+++ b/gcc-4.8.3/libcpp/ChangeLog.arm
++++ b/libcpp/ChangeLog.arm
@@ -0,0 +1,8 @@
+2014-05-29 Terry Guo <terry.guo@arm.com>
+
@@ -6209,8 +6331,8 @@ index 0000000..b8cff8a
+ * init.c (ENABLE_CANONICAL_SYSTEM_HEADERS): Default enabled for DOS.
diff --git a/libcpp/files.c b/libcpp/files.c
index ea91b02..18b8895 100644
---- a/gcc-4.8.3/libcpp/files.c
-+++ b/gcc-4.8.3/libcpp/files.c
+--- a/libcpp/files.c
++++ b/libcpp/files.c
@@ -387,8 +387,14 @@ find_file_in_dir (cpp_reader *pfile, _cpp_file *file, bool *invalid_pch)
char *copy;
void **pp;
@@ -6230,8 +6352,8 @@ index ea91b02..18b8895 100644
if (canonical_path)
diff --git a/libcpp/init.c b/libcpp/init.c
index 3037ecd..4444040 100644
---- a/gcc-4.8.3/libcpp/init.c
-+++ b/gcc-4.8.3/libcpp/init.c
+--- a/libcpp/init.c
++++ b/libcpp/init.c
@@ -27,8 +27,12 @@ along with this program; see the file COPYING3. If not see
#include "filenames.h"
diff --git a/debian/patches/0002-Ignore-document-errors-during-build.patch b/debian/patches/0002-Ignore-document-errors-during-build.patch
index db80284..7406615 100644
--- a/debian/patches/0002-Ignore-document-errors-during-build.patch
+++ b/debian/patches/0002-Ignore-document-errors-during-build.patch
@@ -4,13 +4,13 @@ Date: Sun, 6 Oct 2013 15:23:05 -0700
Subject: [PATCH 2/3] Ignore document errors during build
---
- gcc-4.8.3/gcc/genhooks.c | 4 ++--
+ gcc/genhooks.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
-diff --git a/gcc-4.8.3/gcc/genhooks.c b/gcc-4.8.1/gcc/genhooks.c
+diff --git a/gcc/genhooks.c b/gcc/genhooks.c
index 28bb226..179fc68 100644
---- a/gcc-4.8.3/gcc/genhooks.c
-+++ b/gcc-4.8.3/gcc/genhooks.c
+--- a/gcc/genhooks.c
++++ b/gcc/genhooks.c
@@ -164,8 +164,8 @@ emit_documentation (const char *in_fname)
fatal ("Duplicate hook %s\n", sh.name);
shp->pos = i;
diff --git a/debian/rules b/debian/rules
index be6b943..a1910b3 100755
--- a/debian/rules
+++ b/debian/rules
@@ -84,7 +84,8 @@ configure_flags = \
$(unpack_stamp): $(tar_stamp)
set -ex; \
- for patch in debian/patches/[0-9]*.patch; do \
+ cd gcc-*; \
+ for patch in ../debian/patches/[0-9]*.patch; do \
echo Applying patch "$$patch"; \
patch -p1 < "$$patch"; \
done
diff --git a/debian/samples/readme.txt b/debian/samples/readme.txt
index 42588a5..8a2e3bc 100644
--- a/debian/samples/readme.txt
+++ b/debian/samples/readme.txt
@@ -16,7 +16,7 @@ pass USE_NANO= to make command line like:
$ make USE_NANO=
The makefile is configured to build for Cortex-M0 by default. To build for
-M3 or M4, pass CORTEX_M=3/4 respectively:
+M3, M4 or M7, pass CORTEX_M=3/4/7 respectively:
$ make CORTEX_M=3
* Porting *
diff --git a/debian/samples/startup/startup_ARMCM4.S b/debian/samples/startup/startup_ARMCM4.S
index 2d3d693..0724bf1 100644
--- a/debian/samples/startup/startup_ARMCM4.S
+++ b/debian/samples/startup/startup_ARMCM4.S
@@ -31,7 +31,7 @@
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
- .arch armv7-m
+ .arch armv7e-m
.section .stack
.align 3
diff --git a/debian/samples/startup/startup_ARMCM7.S b/debian/samples/startup/startup_ARMCM7.S
new file mode 100644
index 0000000..0c199ad
--- /dev/null
+++ b/debian/samples/startup/startup_ARMCM7.S
@@ -0,0 +1,257 @@
+/* File: startup_ARMCM7.S
+ * Purpose: startup file for Cortex-M7 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V2.0
+ * Date: 01 August 2014
+ *
+/* Copyright (c) 2011 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+ .syntax unified
+ .arch armv7e-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long Default_Handler
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+ def_irq_handler DEF_IRQHandler
+
+ .end
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