Bug#297849: marked as done (ts10: FTBFS (amd64/gcc-4.0): static declaration of 'dataMode' follows non-static declaration)
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and subject line Bug#297849: fixed in ts10 0.8.030519-1
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Received: (at submit) by bugs.debian.org; 3 Mar 2005 09:25:12 +0000
>From aj@andaco.de Thu Mar 03 01:25:12 2005
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To: Debian Bug Tracking System <submit@bugs.debian.org>
From: Andreas Jochens <aj@andaco.de>
Subject: ts10: FTBFS (amd64/gcc-4.0): static declaration of 'dataMode' follows non-static declaration
Message-Id: <E1D6nWK-0005NL-9h@localhost.localdomain>
Date: Thu, 03 Mar 2005 11:25:28 +0100
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Package: ts10
Severity: normal
Tags: patch
When building 'ts10' on amd64 with gcc-4.0,
I get the following error:
gcc -g -O3 -c -DHAVE_SIGACTION -DDEBUG -DOPT_XADR -I.. -I. cpu_extend.c
cpu_extend.c:235: error: static declaration of 'dataMode' follows non-static declaration
../pdp10/defs.h:477: error: previous declaration of 'dataMode' was here
make[2]: *** [cpu_extend.o] Error 1
make[2]: Leaving directory `/ts10-0.8.021004/pdp10'
With the attached patch 'ts10' can be compiled
on amd64 using gcc-4.0.
Regards
Andreas Jochens
diff -urN ../tmp-orig/ts10-0.8.021004/pdp10/cpu_extend.c ./pdp10/cpu_extend.c
--- ../tmp-orig/ts10-0.8.021004/pdp10/cpu_extend.c 2002-08-12 19:35:34.000000000 +0200
+++ ./pdp10/cpu_extend.c 2005-03-02 18:27:20.000000000 +0100
@@ -232,6 +232,7 @@
static int18 ext_Offset; // Offset Register
+#define dataMode dataMode_cpu_extend
static int dataMode;
extern int30 (*KX10_CalcEffAddr)(int30, int30, int);
diff -urN ../tmp-orig/ts10-0.8.021004/pdp11/cpu2.c ./pdp11/cpu2.c
--- ../tmp-orig/ts10-0.8.021004/pdp11/cpu2.c 2002-10-04 15:03:40.000000000 +0200
+++ ./pdp11/cpu2.c 2005-03-03 10:38:56.000000000 +0100
@@ -365,10 +365,10 @@
// Exchange all registers R0-R5 with R0'-R5'
for (idx = 0; idx < 6; idx++) {
GPREG(idx, oldSet) = REGW(idx);
- REGW(idx) = GPREG(idx, newSet);
+ p11->wkRegs[idx] = GPREG(idx, newSet);
}
}
- SP = STKREG(newMode);
+ p11->wkRegs[6] /* SP */ = STKREG(newMode);
PSW = newPSW & ~CC_ALL;
CC = newPSW & CC_ALL;
diff -urN ../tmp-orig/ts10-0.8.021004/pdp11/cpu_eis.c ./pdp11/cpu_eis.c
--- ../tmp-orig/ts10-0.8.021004/pdp11/cpu_eis.c 2002-09-30 16:29:18.000000000 +0200
+++ ./pdp11/cpu_eis.c 2005-03-02 18:30:46.000000000 +0100
@@ -63,7 +63,7 @@
if ((int16)dst == 0) CC |= CC_Z;
// Write results back.
- REGW(srcSpec) = dst;
+ p11->wkRegs[srcSpec] = dst;
#ifdef DEBUG
if (dbg_Check(DBG_TRACE|DBG_DATA))
@@ -106,8 +106,8 @@
if (dst == 0) CC |= CC_Z;
// Write results back.
- REGW(srcSpec) = dst >> 16;
- REGW(srcSpec | 1) = dst;
+ p11->wkRegs[srcSpec] = dst >> 16;
+ p11->wkRegs[srcSpec | 1] = dst;
#ifdef DEBUG
if (dbg_Check(DBG_TRACE|DBG_DATA))
@@ -135,8 +135,8 @@
CC |= CC_C;
// Write results back
- UREGW(srcSpec) = prod >> 16;
- UREGW(srcSpec | 1) = prod;
+ p11->wkRegs[srcSpec] = prod >> 16;
+ p11->wkRegs[srcSpec | 1] = prod;
#ifdef DEBUG
if (dbg_Check(DBG_TRACE|DBG_DATA))
@@ -173,8 +173,8 @@
} else {
CC_IIZZ_I(quo);
// Write results back
- UREGW(srcSpec) = quo;
- UREGW(srcSpec | 1) = rem;
+ p11->wkRegs[srcSpec] = quo;
+ p11->wkRegs[srcSpec | 1] = rem;
}
}
diff -urN ../tmp-orig/ts10-0.8.021004/pdp11/cpu_main.c ./pdp11/cpu_main.c
--- ../tmp-orig/ts10-0.8.021004/pdp11/cpu_main.c 2002-09-30 17:00:22.000000000 +0200
+++ ./pdp11/cpu_main.c 2005-03-03 11:03:51.000000000 +0100
@@ -72,7 +72,7 @@
TRAP_FPE
};
-#define BRANCH(op) PC += (int8)op << 1
+#define BRANCH(op) p11->wkRegs[7] /* PC */ += (int8)op << 1
#define N (((CC & CC_N) >> 3) & 1)
#define Z (((CC & CC_Z) >> 2) & 1)
@@ -93,15 +93,15 @@
case 1: // (Rn)
return (UREGW(reg) | ds);
case 2: // (Rn)+
- UREGW(reg) = (adr = UREGW(reg)) + 2;
+ p11->wkRegs[reg] = (adr = UREGW(reg)) + 2;
if (UpdateMM) SetMMR1(020 | reg);
return (adr | ds);
case 3: // @(Rn)+
- UREGW(reg) = (adr = UREGW(reg)) + 2;
+ p11->wkRegs[reg] = (adr = UREGW(reg)) + 2;
if (UpdateMM) SetMMR1(020 | reg);
return ((uint16)ReadW(adr | ds) | DSPACE);
case 4: // -(Rn)
- UREGW(reg) = (adr = (UREGW(reg) - 2));
+ p11->wkRegs[reg] = (adr = (UREGW(reg) - 2));
if (UpdateMM) SetMMR1(0360 | reg);
if ((reg == 6) && (adr < STKLIM) && (PSW_GETCUR(PSW) == AM_KERNEL)) {
SET_TRAP(TRAP_YEL);
@@ -109,7 +109,7 @@
}
return (adr | ds);
case 5: // @-(Rn)
- UREGW(reg) = (adr = (UREGW(reg) - 2));
+ p11->wkRegs[reg] = (adr = (UREGW(reg) - 2));
if (UpdateMM) SetMMR1(0360 | reg);
if ((reg == 6) && (adr < STKLIM) && (PSW_GETCUR(PSW) == AM_KERNEL)) {
SET_TRAP(TRAP_YEL);
@@ -117,10 +117,10 @@
}
return ((uint16)ReadW(adr | ds) | DSPACE);
case 6: // d(Rn)
- adr = ReadW(PC | (VA_INST|ISPACE)); PC += 2;
+ adr = ReadW(PC | (VA_INST|ISPACE)); p11->wkRegs[7] /* PC */ += 2;
return (((uint16)(UREGW(reg) + adr)) | DSPACE);
case 7: // @d(Rn)
- adr = ReadW(PC | (VA_INST|ISPACE)); PC += 2;
+ adr = ReadW(PC | (VA_INST|ISPACE)); p11->wkRegs[7] /* PC */ += 2;
adr = ReadW(((uint16)(UREGW(reg) + adr)) | DSPACE);
return (adr | DSPACE);
}
@@ -139,16 +139,16 @@
return (UREGW(reg) | ds);
case 2: // (Rn)+
delta = 1 + (reg >= 6);
- UREGW(reg) = (adr = UREGW(reg)) + delta;
+ p11->wkRegs[reg] = (adr = UREGW(reg)) + delta;
if (UpdateMM) SetMMR1((delta << 3) | reg);
return (adr | ds);
case 3: // @(Rn)+
- UREGW(reg) = (adr = UREGW(reg)) + 2;
+ p11->wkRegs[reg] = (adr = UREGW(reg)) + 2;
if (UpdateMM) SetMMR1(020 | reg);
return ((uint16)ReadW(adr | ds) | DSPACE);
case 4: // -(Rn)
delta = 1 + (reg >= 6);
- UREGW(reg) = (adr = (UREGW(reg) - delta));
+ p11->wkRegs[reg] = (adr = (UREGW(reg) - delta));
if (UpdateMM) SetMMR1((((-delta) & 037) << 3) | reg);
if ((reg == 6) && (adr < STKLIM) && (PSW_GETCUR(PSW) == AM_KERNEL)) {
SET_TRAP(TRAP_YEL);
@@ -156,7 +156,7 @@
}
return (adr | ds);
case 5: // @-(Rn)
- UREGW(reg) = (adr = (UREGW(reg) - 2));
+ p11->wkRegs[reg] = (adr = (UREGW(reg) - 2));
if (UpdateMM) SetMMR1(0360 | reg);
if ((reg == 6) && (adr < STKLIM) && (PSW_GETCUR(PSW) == AM_KERNEL)) {
SET_TRAP(TRAP_YEL);
@@ -164,10 +164,10 @@
}
return ((uint16)ReadW(adr | ds) | DSPACE);
case 6: // d(Rn)
- adr = ReadW(PC | (VA_INST|ISPACE)); PC += 2;
+ adr = ReadW(PC | (VA_INST|ISPACE)); p11->wkRegs[7] /* PC */ += 2;
return (((uint16)(UREGW(reg) + adr)) | DSPACE);
case 7: // @d(Rn)
- adr = ReadW(PC | (VA_INST|ISPACE)); PC += 2;
+ adr = ReadW(PC | (VA_INST|ISPACE)); p11->wkRegs[7] /* PC */ += 2;
adr = ReadW(((uint16)(UREGW(reg) + adr)) | DSPACE);
return (adr | DSPACE);
}
@@ -198,7 +198,7 @@
newPC = ReadW(SP | DSPACE);
newPSW = ReadW((SP+2) | DSPACE);
- STKREG(oldMode) = (SP += 4);
+ STKREG(oldMode) = (p11->wkRegs[6] /* SP */ += 4);
if (oldMode != AM_KERNEL)
newPSW |= (oldPSW & (PSW_CM|PSW_PM|PSW_RS));
@@ -211,16 +211,16 @@
// Exchange all R0-R5 with R0'-R5' registers
for (idx = 0; idx < 6; idx++) {
GPREG(idx, oldSet) = REGW(idx);
- REGW(idx) = GPREG(idx, newSet);
+ p11->wkRegs[idx] = GPREG(idx, newSet);
}
}
ISPACE = GetISpace(newMode);
DSPACE = GetDSpace(newMode);
- SP = STKREG(newMode);
+ p11->wkRegs[6] /* SP */ = STKREG(newMode);
PSW = newPSW & ~CC_ALL;
CC = newPSW & CC_ALL;
- PC = newPC;
+ p11->wkRegs[7] /* PC */ = newPC;
// Update Interrupt Requests
uq11_EvalIRQ(p11, GET_IPL(PSW));
@@ -893,7 +893,7 @@
return;
}
- PC = GeteaW(dstSpec);
+ p11->wkRegs[7] /* PC */ = GeteaW(dstSpec);
#ifdef DEBUG
if (dbg_Check(DBG_TRACE|DBG_DATA))
@@ -913,15 +913,15 @@
return;
}
dst = GeteaW(dstSpec);
- SP -= 2;
+ p11->wkRegs[6] /* SP */ -= 2;
if (UpdateMM) SetMMR1(0366);
WriteW(SP | DSPACE, REGW(srcSpec));
if (((uint16)SP < STKLIM) && (PSW_GETCUR(PSW) == AM_KERNEL)) {
SET_TRAP(TRAP_YEL);
SET_CPUERR(CPUE_YEL);
}
- REGW(srcSpec) = PC;
- PC = dst;
+ p11->wkRegs[srcSpec] = PC;
+ p11->wkRegs[7] /* PC */ = dst;
}
// Halt Processor
@@ -940,9 +940,9 @@
uint16 mark = IR & 077;
uint16 newSP = (PC + (mark << 1));
- PC = R5;
- R5 = ReadW(newSP | DSPACE);
- SP = newSP + 2;
+ p11->wkRegs[7] /* PC */ = R5;
+ p11->wkRegs[5] = ReadW(newSP | DSPACE);
+ p11->wkRegs[6] /* SP */ = newSP + 2;
}
// Move From Previous Data
@@ -964,7 +964,7 @@
CC_IIZP_W(dst);
// Push data into stack
- SP -= OP_WORD;
+ p11->wkRegs[6] /* SP */ -= OP_WORD;
if (UpdateMM) SetMMR1(0366);
WriteW(SP | DSPACE, dst);
if ((SP < STKLIM) && (curMode == AM_KERNEL)) {
@@ -995,7 +995,7 @@
CC_IIZP_W(dst);
// Push data into stack
- SP -= OP_WORD;
+ p11->wkRegs[6] /* SP */ -= OP_WORD;
if (UpdateMM) SetMMR1(0366);
WriteW(SP | DSPACE, dst);
if ((SP < STKLIM) && (curMode == AM_KERNEL)) {
@@ -1013,7 +1013,7 @@
CC_IIZP_B(dst);
// Write value to destination
- if (dstSpec <= 7) REGW(dstSpec) = dst;
+ if (dstSpec <= 7) p11->wkRegs[dstSpec] = dst;
else WriteB(p11_GeteaB(p11, dstSpec), dst);
#ifdef DEBUG
@@ -1026,7 +1026,7 @@
// Move From Processor Type
INSDEF(p11, MFPT)
{
- R0 = CPUID;
+ p11->wkRegs[0] = CPUID;
}
INSDEF(p11, MOV)
@@ -1050,7 +1050,7 @@
CC_IIZP_W(dst);
// Write value to destination
- if (dstSpec <= 7) REGW(dstSpec) = dst;
+ if (dstSpec <= 7) p11->wkRegs[dstSpec] = dst;
else WriteW(eAddr, dst);
#ifdef DEBUG
@@ -1081,7 +1081,7 @@
CC_IIZP_B(dst);
// Write value to destination
- if (dstSpec <= 7) REGW(dstSpec) = dst;
+ if (dstSpec <= 7) p11->wkRegs[dstSpec] = dst;
else WriteB(eAddr, dst);
#ifdef DEBUG
@@ -1100,7 +1100,7 @@
int16 dst;
// Pop data from stack
- dst = ReadW(SP | DSPACE); SP += 2;
+ dst = ReadW(SP | DSPACE); p11->wkRegs[6] /* SP */ += 2;
if (UpdateMM) SetMMR1(026);
// Update condition codes
@@ -1111,7 +1111,7 @@
if ((dstSpec == 6) && (curMode != prvMode))
STKREG(prvMode) = dst;
else
- REGW(dstSpec) = dst;
+ p11->wkRegs[dstSpec] = dst;
} else
WriteW(GeteaW(dstSpec) | GetDSpace(prvMode), dst);
}
@@ -1125,7 +1125,7 @@
int16 dst;
// Pop data from stack
- dst = ReadW(SP | DSPACE); SP += 2;
+ dst = ReadW(SP | DSPACE); p11->wkRegs[6] /* SP */ += 2;
if (UpdateMM) SetMMR1(026);
// Update condition codes
@@ -1136,7 +1136,7 @@
if ((dstSpec == 6) && (curMode != prvMode))
STKREG(prvMode) = dst;
else
- REGW(dstSpec) = dst;
+ p11->wkRegs[dstSpec] = dst;
} else
WriteW(GeteaW(dstSpec) | GetISpace(prvMode), dst);
}
@@ -1341,9 +1341,9 @@
{
uint32 dstSpec = IR & 7;
- PC = REGW(dstSpec);
- REGW(dstSpec) = ReadW(SP | DSPACE);
- if (dstSpec != 6) SP += 2;
+ p11->wkRegs[7] /* PC */ = REGW(dstSpec);
+ p11->wkRegs[dstSpec] = ReadW(SP | DSPACE);
+ if (dstSpec != 6) p11->wkRegs[6] /* SP */ += 2;
}
// Return From Trap
@@ -1411,8 +1411,8 @@
{
register int dstSpec = (IR >> 6) & 7;
- if (--REGW(dstSpec))
- PC -= (IR & 077) << 1;
+ if (--p11->wkRegs[dstSpec])
+ p11->wkRegs[7] /* PC */ -= (IR & 077) << 1;
#ifdef DEBUG
if (dbg_Check(DBG_TRACE|DBG_DATA)) {
@@ -1584,7 +1584,7 @@
if (dst & 1) CC |= CC_C;
// Write results back.
- R0 = dst;
+ p11->wkRegs[0] = dst;
StoreMW(dstSpec, pAddr, (dst | 1));
}
@@ -1733,15 +1733,15 @@
// Exchange all R0-R5 with R0'-R5' registers
for (idx = 0; idx < 6; idx++) {
GPREG(idx, oldSet) = REGW(idx);
- REGW(idx) = GPREG(idx, newSet);
+ p11->wkRegs[idx] = GPREG(idx, newSet);
}
}
- SP = STKREG(newMode) - 4;
+ p11->wkRegs[6] /* SP */ = STKREG(newMode) - 4;
// Load new PC and PSW and continue.
PSW = ((oldMode << PSW_P_PM) | (newPSW & ~PSW_PM)) & ~CC_ALL;
CC = newPSW & CC_ALL;
- PC = newPC;
+ p11->wkRegs[7] /* PC */ = newPC;
// Set Instruction/Data Space for Memory Mangement
ISPACE = GetISpace(newMode);
@@ -1804,7 +1804,7 @@
SET_CPUERR(CPUE_RED);
STKREG(AM_KERNEL) = 4;
if (PSW_GETCUR(PSW) == AM_KERNEL)
- SP = 4;
+ p11->wkRegs[6] /* SP */ = 4;
}
}
@@ -1841,7 +1841,7 @@
MMR2 = PC;
}
IR = opCode = ReadW(PC | (VA_INST|ISPACE));
- PC += 2;
+ p11->wkRegs[7] /* PC */ += 2;
// Count and execute instruction.
CIPS++;
@@ -1857,5 +1857,5 @@
p11->StopTimer(p11);
ts10_StopTimer();
- printf("%s: Stopped at PC %06o\n", p11->Unit.devName, (uint16)PC);
+ printf("%s: Stopped at p11->wkRegs[7] /* PC */ %06o\n", p11->Unit.devName, (uint16)PC);
}
diff -urN ../tmp-orig/ts10-0.8.021004/pdp11/defs.h ./pdp11/defs.h
--- ../tmp-orig/ts10-0.8.021004/pdp11/defs.h 2002-10-05 04:55:43.000000000 +0200
+++ ./pdp11/defs.h 2005-03-03 10:57:44.000000000 +0100
@@ -404,7 +404,7 @@
((spec <= 7) ? REGB(spec) : (int8)ReadMB(GeteaB(spec), pa))
#define StoreW(spec, data) \
- if (spec <= 7) REGW(spec) = data; \
+ if (spec <= 7) p11->wkRegs[spec] = data; \
else WriteW(GeteaW(spec), data);
#define StoreB(spec, data) \
@@ -412,7 +412,7 @@
else WriteB(GeteaB(spec), data);
#define StoreMW(spec, pa, data) \
- if (spec <= 7) REGW(spec) = data; \
+ if (spec <= 7) p11->wkRegs[spec] = data; \
else WritePW(pa, data);
#define StoreMB(spec, pa, data) \
diff -urN ../tmp-orig/ts10-0.8.021004/pdp11/kdf11_sys.c ./pdp11/kdf11_sys.c
--- ../tmp-orig/ts10-0.8.021004/pdp11/kdf11_sys.c 2002-10-05 04:58:16.000000000 +0200
+++ ./pdp11/kdf11_sys.c 2005-03-03 11:04:30.000000000 +0100
@@ -295,7 +295,7 @@
f11_ResetCPU(f11);
// Initial Power On
- PC = 0173000;
+ p11->wkRegs[7] /* PC */ = 0173000;
// Enable F11 Processor to run.
// Finally, transfer control to
diff -urN ../tmp-orig/ts10-0.8.021004/pdp11/kdj11_sys.c ./pdp11/kdj11_sys.c
--- ../tmp-orig/ts10-0.8.021004/pdp11/kdj11_sys.c 2002-10-05 04:57:48.000000000 +0200
+++ ./pdp11/kdj11_sys.c 2005-03-03 11:04:53.000000000 +0100
@@ -296,7 +296,7 @@
// Initial Power On
MAINT = (SID_KDJ11A << SID_POS) | (PUO_BOOT << PUO_POS) | CPU_PWOK;
- PC = 0173000; // Boot Address 173000
+ p11->wkRegs[7] /* PC */ = 0173000; // Boot Address 173000
PSW = 0000340; // Process Status, IPL = 7.
// Enable J11 Processor to run.
diff -urN ../tmp-orig/ts10-0.8.021004/vax/ka630_sys.c ./vax/ka630_sys.c
--- ../tmp-orig/ts10-0.8.021004/vax/ka630_sys.c 2002-09-25 21:50:55.000000000 +0200
+++ ./vax/ka630_sys.c 2005-03-03 11:20:47.171727656 +0100
@@ -286,7 +286,7 @@
{
switch (pReg) {
case PR_KSP: // Kernel Stack Pointer
- ((PSL & PSL_IS) ? KSP : SP) = data;
+ if (PSL & PSL_IS) KSP = data; else SP = data;
break;
case PR_ESP: // Executive Stack Pointer
@@ -296,7 +296,7 @@
break;
case PR_ISP: // Interrupt Stack Pointer
- ((PSL & PSL_IS) ? SP : ISP) = data;
+ if (PSL & PSL_IS) SP = data; else ISP = data;
break;
case PR_P0BR:
diff -urN ../tmp-orig/ts10-0.8.021004/vax/ka650_sys.c ./vax/ka650_sys.c
--- ../tmp-orig/ts10-0.8.021004/vax/ka650_sys.c 2002-09-25 19:59:13.000000000 +0200
+++ ./vax/ka650_sys.c 2005-03-03 11:21:19.963398258 +0100
@@ -266,7 +266,7 @@
{
switch (pReg) {
case PR_KSP: // Kernel Stack Pointer
- ((PSL & PSL_IS) ? KSP : SP) = data;
+ if (PSL & PSL_IS) KSP = data; else SP = data;
break;
case PR_ESP: // Executive Stack Pointer
@@ -276,7 +276,7 @@
break;
case PR_ISP: // Interrupt Stack Pointer
- ((PSL & PSL_IS) ? SP : ISP) = data;
+ if (PSL & PSL_IS) SP = data; else ISP = data;
break;
case PR_P0BR:
diff -urN ../tmp-orig/ts10-0.8.021004/vax/ka780_sys.c ./vax/ka780_sys.c
--- ../tmp-orig/ts10-0.8.021004/vax/ka780_sys.c 2002-06-07 15:53:20.000000000 +0200
+++ ./vax/ka780_sys.c 2005-03-03 11:21:49.861627349 +0100
@@ -205,7 +205,7 @@
switch (pReg) {
case nKSP: // Kernel Stack Pointer
- ((PSL & PSL_IS) ? KSP : SP) = data;
+ if (PSL & PSL_IS) KSP = data; else SP = data;
break;
case nESP: // Executive Stack Pointer
@@ -215,7 +215,7 @@
break;
case nISP: // Interrupt Stack Pointer
- ((PSL & PSL_IS) ? SP : ISP) = data;
+ if (PSL & PSL_IS) SP = data; else ISP = data;
break;
case nP0BR:
---------------------------------------
Received: (at 297849-close) by bugs.debian.org; 18 Aug 2005 16:09:30 +0000
>From katie@spohr.debian.org Thu Aug 18 09:09:30 2005
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From: Matej Vela <vela@debian.org>
To: 297849-close@bugs.debian.org
X-Katie: $Revision: 1.56 $
Subject: Bug#297849: fixed in ts10 0.8.030519-1
Message-Id: <E1E5mqc-0007EX-00@spohr.debian.org>
Sender: Archive Administrator <katie@spohr.debian.org>
Date: Thu, 18 Aug 2005 09:02:30 -0700
Delivered-To: 297849-close@bugs.debian.org
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autolearn=no version=2.60-bugs.debian.org_2005_01_02
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Source: ts10
Source-Version: 0.8.030519-1
We believe that the bug you reported is fixed in the latest version of
ts10, which is due to be installed in the Debian FTP archive:
ts10_0.8.030519-1.diff.gz
to pool/main/t/ts10/ts10_0.8.030519-1.diff.gz
ts10_0.8.030519-1.dsc
to pool/main/t/ts10/ts10_0.8.030519-1.dsc
ts10_0.8.030519-1_i386.deb
to pool/main/t/ts10/ts10_0.8.030519-1_i386.deb
ts10_0.8.030519.orig.tar.gz
to pool/main/t/ts10/ts10_0.8.030519.orig.tar.gz
A summary of the changes between this version and the previous one is
attached.
Thank you for reporting the bug, which will now be closed. If you
have further comments please address them to 297849@bugs.debian.org,
and the maintainer will reopen the bug report if appropriate.
Debian distribution maintenance software
pp.
Matej Vela <vela@debian.org> (supplier of updated ts10 package)
(This message was generated automatically at their request; if you
believe that there is a problem with it please contact the archive
administrators by mailing ftpmaster@debian.org)
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Format: 1.7
Date: Thu, 18 Aug 2005 17:38:58 +0200
Source: ts10
Binary: ts10
Architecture: source i386
Version: 0.8.030519-1
Distribution: unstable
Urgency: high
Maintainer: Debian QA Group <packages@qa.debian.org>
Changed-By: Matej Vela <vela@debian.org>
Description:
ts10 - Emulators for PDP-10, PDP-11, VAX
Closes: 181220 297849
Changes:
ts10 (0.8.030519-1) unstable; urgency=high
.
* QA upload.
* New upstream release.
* Switch to dpatch.
* Fix build failure with gcc 4.0. Closes: #297849.
- invalid-lvalue.dpatch: Casts and conditionals are no longer accepted
as lvalues.
- name-clash.dpatch: A static global variable is not allowed to have the
same name as a non-static one.
* signed-char.dpatch: char is by default unsigned on arm, powerpc, and s390;
explicitly declare int8 as signed. Closes: #181220.
* const-too-large.dpatch: Fix "integer constant is too large for 'long'
type".
* copts.dpatch: Allow optimization flags to be overriden from debian/rules
so that DEB_BUILD_OPTIONS=noopt actually works.
* TI-99 is no longer supported; remove it from the description.
* Install cfg files as examples rather than documentation.
* Install all ChangeLog and ReadMe files.
* debian/copyright: Update.
* debian/ts10.1: Boils down to the dh_make template; leave it out for now.
* debian/upstream.txt: Replace with an equivalent watch file.
* Conforms to Standards version 3.6.2.
Files:
5646a747f87688203ae233f6c1641301 575 otherosfs optional ts10_0.8.030519-1.dsc
cc9822cbeea8fd85f0950df43537fd71 585289 otherosfs optional ts10_0.8.030519.orig.tar.gz
04d923ed9812be0fe65e0771368c6d0b 8138 otherosfs optional ts10_0.8.030519-1.diff.gz
bd03dc0a229025d8a844c25c6f666686 267668 otherosfs optional ts10_0.8.030519-1_i386.deb
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