Re: Delay slot in PowerISA?
Hi Felix,
On Tue, 2026-01-13 at 14:56 -0800, Felix Lechner wrote:
> When I searched for "powerpc64 delay slot" today, the SearchAssist
> bubble on DuckDuckGo called delay slots are a "feature" on PowerPC. The
> full text is at the bottom of this message.
>
> However, both references in the text state the opposite, namely:
>
> "Some RISCs like PowerPC and ARM do not have a delay slot" [1]
>
> and
>
> "MC88000 [...] and SPARC are RISC architectures that each have a
> single branch delay slot; PowerPC, ARM, Alpha, V850, and RISC-V do
> not have any." [2]
>
> Personally, I remain uncertain because sample code in a presentation
> from 2014 has 'nop' instructions after the 'bl' instructions. [3] Does
> the PowerPC architecture have delay slots, please?
My understanding is that research had shown that branch prediction was
much more efficient and faster than delay slots which is why all newer
designs do not use them.
I know for sure that both SPARC and SuperH use them, haven't about PowerPC
using them and given the fact that PowerPC was created in the early 90s,
I don't think it ever had delay slots.
It seems that one of the symbols to look for in GCC in this matter is called
"define_delay" [1]. Searching for it in the GCC source code shows no usw
for rs6000 (the GCC name for the PowerPC backend) [2].
>From that search, GCC uses them for the following architectures:
- PA-RISC
- ARC
- FRV
- CRIS
- OR1k
- IQ2000
- MIPS
- Microblaze
- H8300
- Visium
- FR30
- SPARC
Interestingly though, "define_delay" is also not used in the SH backend
which definitely supports delay slots.
Adrian
> [1] https://gcc.gnu.org/onlinedocs/gcc-3.4.2/gccint/Delay-Slots.html
> [2] https://github.com/search?q=repo%3Agcc-mirror%2Fgcc%20define_delay&type=code
--
.''`. John Paul Adrian Glaubitz
: :' : Debian Developer
`. `' Physicist
`- GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
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