Re: Bug#885245: linux: FTBFS on powerpcspe: sstep.c: ptesync unrecognized
That will be wrong for PPC spe, as its got differing and conflicting instructions compared with other CPUs in its class. The attached patch built and is finishing up modules now .
Michael
to get the latest kernel to compile on a powermac g5 takes removing the power8 instructions from sstep.c it will compile with -mpower8 but then wont boot if you dont get rid of the instructions
commit 8a6358dfdf06a35d2aa9cf171b8444a716ad0c2a
Author: threader <michael.heltne@gmail.com>
Date: Fri Jan 21 20:36:33 2022 +0100
arch: powerpc: fix building, 'dssall' in mmu_context.c is an altivec instruction, so build that accordingly if such is the case.
'ptesync' is a PPC64 instruction, so dont go there for PPC32. And apparently ifdefined __powerpc64__ isnt enough in all configurations(?) and 'stbcix' sticks its head up.
Signed-off-by: Micahel B Heltne <michael.heltne@gmail.com>
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index beba4979bff9..cb09701ed114 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -334,7 +334,7 @@ static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
}
#define __raw_writel __raw_writel
-#ifdef __powerpc64__
+#ifdef CONFIG_PPC64
static inline unsigned long __raw_readq(const volatile void __iomem *addr)
{
return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 86f49e3e7cf5..becbe2898e10 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -3267,9 +3267,11 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
case BARRIER_LWSYNC:
asm volatile("lwsync" : : : "memory");
break;
+#ifdef CONFIG_PPC64
case BARRIER_PTESYNC:
asm volatile("ptesync" : : : "memory");
break;
+#endif
}
break;
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index df8172da2301..2f87e7731599 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -4,6 +4,9 @@
#
ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
+ifeq ($(CONFIG_ALTIVEC),y)
+CFLAGS_mmu_context.o += $(call cc-option, -maltivec, -mabi=altivec)
+endif
obj-y := fault.o mem.o pgtable.o mmap.o maccess.o pageattr.o \
init_$(BITS).o pgtable_$(BITS).o \
diff --git a/arch/powerpc/mm/pageattr.c b/arch/powerpc/mm/pageattr.c
index edea388e9d3f..ccd04a386e28 100644
--- a/arch/powerpc/mm/pageattr.c
+++ b/arch/powerpc/mm/pageattr.c
@@ -54,11 +54,11 @@ static int change_page_attr(pte_t *ptep, unsigned long addr, void *data)
}
pte_update(&init_mm, addr, ptep, ~0UL, pte_val(pte), 0);
-
+#ifdef CONFIG_PPC64
/* See ptesync comment in radix__set_pte_at() */
if (radix_enabled())
asm volatile("ptesync": : :"memory");
-
+#endif
flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
spin_unlock(&init_mm.page_table_lock);
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