Re: Not coherent cache DMA for G3/G4 CPUs: clarification needed
On Fri, Apr 21, 2006 at 07:06:13AM +1000, Benjamin Herrenschmidt wrote:
> (On 6xx this is deadly even if you don't access those cacheable pages
> because the CPU prefetch may do it for you).
Here is another thought if this "prefetch" theory is correct.
You guys seems to focus on
dma_alloc_coherent()/pci_alloc_consistent(), but forgeting about so
called "streaming" mappings.
You cannot just flush/invalidate cache any more, because "CPU can
prefetch this data back". So, to be completely correct (if you insist
on "6xx can prefetch"-theory), you have to actually _copy_ data to
your consistent memory on dma_map_single(). You can imagine
performance implications. I suspect even 440 will be faster in this
case than G4 :).