Re: instruction cache throttling

[Joerg Sommer <joerg@alea.gnuu.de>]

John Steele Scott <toojays@toojays.net> wrote:
> --=-=-=
>
> Joerg Sommer <joerg@alea.gnuu.de> writes:
>> Hi,
>>
>> inspired by John Steele (<87k6nrlw6n.fsf@toojays.net>,
>> <news:3N2N5-6u3-23@gated-at.bofh.it>) I searched a little bit with google
>> and found that the instruction cache throttling register is named in the
>> Kernel source (include/asm-ppc/reg.h). A todo note is made in
>> arch/ppc/kernel/temp.c.
>>
>> I here next semester a lecture about kernel hacking. My idea is to
>> implements the instruction cache throttling register in this lecture. Are
>> there any plans to do this? Should there be a new node in
>> /sys/devices/system/cpu/cpu?/ to control the contents of the register? Is
>> there any similar at any other platform?
>
> I don't think there should be a new node to control the register; it should be
> done through the cpufreq mechanism. You can get a start by reading the

Do you mean the powersave governor should controll this register too?

> I'm interested to discuss this more. I have been wanting this feature for a
> while; and even have written some code for it a couple of times, but I tend to
> get distracted too easily when it comes to hobby code.

Is your code anywher available?

Jörg.

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