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Re: Powerbook G4 1.33 GHz CPU temperature

On Thu, 2004-09-23 at 18:31, Michael Schmitz wrote:
> > > You mentioned a patch for hardcoding the PLL; any specific pointer for
> > > that?
> >
> > Look at radeon_fixup_panel_info() in radeon_monitor.c, let me know if
> > adding your machine type there helps.
> At least the feedback divider and post divider there (for the albook 5,3)
> are different from what I've got (1, and 56 vs. 4 and 80)

What do you have at boot in in PPLL_DIV_0 ? It's the value set by OF,
Linux uses PPLL_DIV_3 to set it's own.

> With that patch, the console image is fine. Now the PLL fails to lock
> properly in X.

Weird... well, X should be tweaked to use the same value as it had
upon entry as well, taht is something I should write a patch for, we
should basically avoid using a different PLL value than what the ROM
set on LVDS panels. 

> What other combinations of fb_div and post_div can I try? iBooks use 6,
> ad, is that safe to use?

Read what OF sets. the 2 bits 0x00000300 of CLOCK_CNTL_INDEX define
which of the 4 PPLL_DIV_n register is to be used. Apple uses 0 and we
use 3. The nice side effect is that apple value isn't overriden by
linux so you can still read it without having to reboot :)

What should be done ideally is an option for the X driver that for
heads of type LVDS, would read CLOCK_CNTL_INDEX to see what is the
current divider register used, then read that register, and use that
as the PLL value. X already has a UseBIOSDividers variable for when
the BIOS tables provide the value, so we just need to feed those same
variables, but from whatever is in the PLL register that was active
when X was started (that assumes we had something working of course).

Also, check the value you have and send me a proper patch for radeonfb :)


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