Re: booting 500 MHz G4 from cd?
[CC: to Cort, and to debian-powerpc for people to try that patch on their
own]
> > Please include my patch for broken PCI setup on atyfb by OF - or better,
> > let me send you a fresh one.
>
> Sure, send it to me. Better yet, send it to Cort, since I use his
> bitkeeper repository for kernels.
The patch is against 2.2.17pre20 from BenH (but atyfb.c hasn't changed
much in the last weeks).
What it does is remap the Mach64 MMIO region to avoid overlap with the
VRAM region (this would upset the XFree86 4.x X server). The new address
for MMIO is guessed for lack of PCI resource bookkeeping in 2.2 kernels.
Michael
--- drivers/video/atyfb.c.benh2 Fri Aug 25 22:51:04 2000
+++ drivers/video/atyfb.c Fri Aug 25 22:53:03 2000
@@ -3244,11 +3244,11 @@
#ifdef CONFIG_FB_OF
__initfunc(void atyfb_of_init(struct device_node *dp))
{
- unsigned long addr;
+ unsigned long addr, io_base=NULL;
u8 bus, devfn;
u16 cmd;
struct fb_info_aty *info;
- int i;
+ int i, i_frame, i_regs, i_io, naddr;
if (device_is_compatible(dp, "ATY,264LTPro")) {
/* XXX kludge for now */
@@ -3283,6 +3283,12 @@
}
memset(info, 0, sizeof(struct fb_info_aty));
+ /*
+ * Use register set in the little endian aperture regardless of what was set
+ * up in OF or the PCI registers for MMIO. We could use the registers in the
+ * big endian aperture as well (at least on some LTPro), or set up a separate
+ * PCI mapping. Seems to work either way (again, on my Lombard) - MSch.
+ */
info->ati_regbase_phys = 0x7ff000+addr;
info->ati_regbase = (unsigned long)ioremap(info->ati_regbase_phys,
0x2000);
@@ -3296,8 +3302,49 @@
info->ati_regbase_phys += 0xc00;
info->ati_regbase += 0xc00;
- /* enable memory-space accesses using config-space command register */
+ /* search PCI config space for VRAM, IO and MMIO regions */
if (pci_device_loc(dp, &bus, &devfn) == 0) {
+
+ for (i = 0; i < dp->n_addrs + 2; i++) {
+ int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
+ unsigned long base;
+ u32 size, pbase;
+
+ base = dp->addrs[i].address;
+
+ pcibios_read_config_dword(bus, devfn, breg, &pbase);
+ pcibios_write_config_dword(bus, devfn, breg, 0xffffffff);
+ pcibios_read_config_dword(bus, devfn, breg, &size);
+ pcibios_write_config_dword(bus, devfn, breg, pbase);
+
+ io = (pbase & PCI_BASE_ADDRESS_SPACE)==PCI_BASE_ADDRESS_SPACE_IO;
+
+ if (io) {
+ size &= ~1;
+ pbase &= ~1;
+ i_io = i;
+ }
+
+ size = ~(size) + 1;
+
+ if (size == 0)
+ break;
+
+ if (!base) {
+ dp->addrs[i].address = pbase;
+ dp->addrs[i].size = size;
+ }
+ if (pbase == addr) {
+ i_frame = i;
+ } else if (size == 0x1000) {
+ i_regs = i;
+ io_base = pbase;
+ }
+ }
+
+ naddr = i;
+
+ /* enable memory-space accesses using config-space command register */
pcibios_read_config_word(bus, devfn, PCI_COMMAND, &cmd);
if (cmd != 0xffff) {
cmd |= PCI_COMMAND_MEMORY;
@@ -3318,6 +3365,87 @@
printk("atyfb_init: ioremap() returned NULL\n");
kfree(info);
return;
+ }
+
+ /*
+ * Fix MMIO mapping if MMIO and VRAM PCI mappings overlap - MSch.
+ * Note that we can't move the VRAM base address to the BE aperture (this would move the whole
+ * VRAM region, not resize it) so it's easier to remap MMIO someplace else.
+ */
+ if ( (dp->addrs[i_frame].address < dp->addrs[i_regs].address+dp->addrs[i_regs].size
+ && dp->addrs[i_frame].address+dp->addrs[i_frame].size >= dp->addrs[i_regs].address)
+ || (dp->addrs[i_regs].address < dp->addrs[i_frame].address+dp->addrs[i_frame].size
+ && dp->addrs[i_regs].address+dp->addrs[i_regs].size >= dp->addrs[i_frame].address) ) {
+
+ struct pci_dev *pdev = pci_find_slot(bus, devfn);
+ int io, breg = PCI_BASE_ADDRESS_0 + (i_regs << 2);
+ int flags;
+ unsigned long base;
+ u32 size, pbase, new;
+
+ base = dp->addrs[i_regs].address;
+
+ pcibios_read_config_dword(bus, devfn, breg, &pbase);
+ pcibios_write_config_dword(bus, devfn, breg, 0xffffffff);
+ pcibios_read_config_dword(bus, devfn, breg, &size);
+ pcibios_write_config_dword(bus, devfn, breg, pbase);
+
+ io = (pbase & PCI_BASE_ADDRESS_SPACE)==PCI_BASE_ADDRESS_SPACE_IO;
+ flags = (pbase & PCI_BASE_ADDRESS_MEM_MASK);
+
+ if (io) {
+ size &= ~1;
+ pbase &= ~1;
+ }
+ size = ~(size) + 1;
+
+ printk("atyfb: region %d ofbase 0x%lx breg %d io %d pbase 0x%lx size 0x%lx overlaps VRAM ",
+ i_regs, base, breg, io, pbase, size);
+
+ /* move MMIO before frame buffer and past I/O for now. Need to walk PCI resources to find safe place */
+ if (dp->addrs[i_io].address+dp->addrs[i_io].size+dp->addrs[i_regs].size < dp->addrs[i_frame].address) {
+ new = (dp->addrs[i_io].address&0xff000000) | (dp->addrs[i_regs].address&0x00ffffff) | (flags & 0x0f);
+ } else {
+ new = (dp->addrs[i_frame].address+dp->addrs[i_frame].size) | (flags & 0x0f);
+ }
+
+ pcibios_write_config_dword(bus, devfn, breg, new);
+
+ pcibios_read_config_dword(bus, devfn, breg, &pbase);
+ pcibios_write_config_dword(bus, devfn, breg, 0xffffffff);
+ pcibios_read_config_dword(bus, devfn, breg, &size);
+ pcibios_write_config_dword(bus, devfn, breg, pbase);
+
+ if (new != pbase)
+ printk("atyfb: failed to remap MMIO region! \n");
+
+ /* update PCI struct */
+ if (!pdev)
+ printk("atyfb: no pci_dev registered for device!\n");
+ else
+ pdev->base_address[i_regs] = pbase;
+
+ io = (pbase & PCI_BASE_ADDRESS_SPACE)==PCI_BASE_ADDRESS_SPACE_IO;
+ flags = (pbase & ~PCI_BASE_ADDRESS_MEM_MASK);
+
+ if (io) {
+ size &= ~1;
+ pbase &= ~1;
+ }
+ size = ~(size) + 1;
+
+ printk(" - reassigned to pbase 0x%lx size 0x%lx ! \n", pbase, size);
+
+ /* update OF device tree */
+ dp->addrs[i_regs].address = pbase;
+
+ /*
+ * Note: we only fixed up PCI config and brought the OF device tree
+ * in line with the new PCI config. regbase still is mapped to the original
+ * location in the LE aperture which overlaps with the full (LE and BE)
+ * VRAM. If someone at xfree ever starts to check if regbase falls within
+ * the PCI region of VRAM, slap them silly - MSch.
+ */
}
if (!aty_init(info, dp->full_name)) {
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