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Re: Release sprint results - team changes, auto-rm and arch status

On Sat, Nov 30, 2013 at 11:25:01PM +0000, Ben Hutchings wrote:
> > MUL is a MIPS32 instruction, which is not present on MIPS3 CPUs like the
> > Loongson 2, MULT + MFLO should be used instead. There is no CPU bug
> > there, it's like trying to build x86 code with SSE4 instructions, and
> > then saying that all x86 CPUs which do not support the SSE4 instructions
> > are buggy.
> That was only the first problem; read the whole entry.

The other problem can be attributed to a bug in the CPU... or not. The
fact that mono works on one CPU and not on the other, while they have
different instruction sets can not be attributed to the NOP issue.
Without the analysis done in this same blog entry, the MUL "issue" could
also have been taken for a CPU bug.

Said otherwise, if a code works on a Pentium Pro, but not on a Pentium,
one can't be sure that the problem is the F0 0F bug. It could also be
code using the cmov instruction.

Also note that the latest batches of the Loongson-2F CPUs have the bug

Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

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