Thomas Bogendoerfer wrote:
no suprise here. As Ralf already noted cache barrier is a restricted instruction, it will always cause a illegal instruction when used in user space. Nevertheless it looks like all IP28 are affected by the simple exploit. Flo built glibc 2.7 with LLSC war workaround and this avoids triggering the hang.
Ah, didn't know the 'cache' instructions was kernel-mode only. Explains why it survived then :)
How does one enable the LLSC war workaround in glibc? --Kumba -- Gentoo/MIPS Team Lead"Such is oft the course of deeds that move the wheels of the world: small hands do them because they must, while the eyes of the great are elsewhere." --Elrond