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Re: Tester with IP27/IP30 needed

On Fri, Jan 25, 2008 at 10:12:50PM -0500, Kumba wrote:
> f  - cache barriers on load and stores (-mr10k-cache-barrier=2)
> f2 - cache barriers on loads only (-mr10k-cache-barrier=1)
> f3 - no cache barriers (flag omitted from gcc)
> Running 'f' and 'f2' generates an "Illegal instruction" error, then drops 
> back to the command line, while 'f3' hangs the box.  This is an IP28 

no suprise here. As Ralf already noted cache barrier is a restricted
instruction, it will always cause a illegal instruction when used
in user space. Nevertheless it looks like all IP28 are affected
by the simple exploit. Flo built glibc 2.7 with LLSC war workaround
and this avoids triggering the hang.

> FYI, CPU rev in this machine is R10000 v2.5.  I think that's the same for 
> all IP28 systems.

Flo and mine also have rev 2.5 cpus.


Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

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