Bug#1117002: WARNING: CPU: 1 PID: 0 at arch/x86/kernel/cpu/cpuid-deps.c:123 do_clear_cpu_cap+0xdc/0x130 on Intel(R) Atom(TM) CPU N450 system

[Sohil Mehta <sohil.mehta@intel.com>]

On 10/17/2025 8:36 AM, Andi Kleen wrote:
>> [    0.351035] smp: Bringing up secondary CPUs ...
>> [    0.351876] smpboot: x86: Booting SMP configuration:
>> [    0.351888] .... node  #0, CPUs:      #1
>> [    0.008282] Disabled fast string operations
> 
> It's probably caused by that. I guess he disabled fast strings in his
> BIOS and if he switches that setting it would go away.
> 
> The related code would need to be moved earlier in the boot sequence to
> make the alternative patching work.
> 

I am not sure about moving the code.

Based on the CPU information in the dmesg:
smpboot: CPU0: Intel(R) Atom(TM) CPU N450   @ 1.66GHz (family: 0x6,
model: 0x1c, stepping: 0xa)

This code should behave the same way on Boot CPU and secondary CPUs. So,
as Dave mentioned, it is likely to be an (BIOS) issue if it is exposed
inconsistently across CPUs.

	if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) {
		rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
		if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
			/* X86_FEATURE_ERMS is set based on CPUID */
			set_cpu_cap(c, X86_FEATURE_REP_GOOD);
		} else {
			pr_info("Disabled fast string operations\n");
			setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
			setup_clear_cpu_cap(X86_FEATURE_ERMS);
		}
	}



> But in practice it's unlikely it causes any real functional problems
>