Bug#964734: Patch to revert bad commit
Tags: patch
Attached is a patch to revert the mentioned commit
It is based on kernel v4.19.131.
From: Berni Turmann <bernhard@turmann.eu>
Date: Thu, 9 Jul 2020 13:00:00 +0200
Subject: Revert: PCI: Add boot interrupt quirk mechanism for Xeon chipsets
Fixes: commit d2345d1231d80ecbea5fb764eb43123440861462
("PCI: Add boot interrupt quirk mechanism for Xeon chipsets")
With the above mentioned commit included, the ddbridge module is loading,
but dmesg reports i2c timeouts and the dvb card is not working.
This patch fixes the regression introduced with kernel v4.19.116.
Loading of dvb kernel module ddbridge fails.
Affected Hardware: Supermicro Super Server / X10SDV-TLN4F
CPU: Intel(R) Xeon(R) CPU D-1541 @ 2.10GHz
Affected DVB adapter: Digital Devices Cine S2 V7 Advanced
Index: linux/drivers/pci/quirks.c
===================================================================
--- linux.orig/drivers/pci/quirks.c
+++ linux/drivers/pci/quirks.c
@@ -1947,92 +1947,26 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_I
/*
* IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
* 300641-004US, section 5.7.3.
- *
- * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
- * Core IO on Xeon E5 v2, see Intel order no 329188-003.
- * Core IO on Xeon E7 v2, see Intel order no 329595-002.
- * Core IO on Xeon E5 v3, see Intel order no 330784-003.
- * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
- * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
- * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
- * Core IO on Xeon D-1500, see Intel order no 332051-001.
- * Core IO on Xeon Scalable, see Intel order no 610950.
*/
-#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
+#define INTEL_6300_IOAPIC_ABAR 0x40
#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
-#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
-#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
-
static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
{
u16 pci_config_word;
- u32 pci_config_dword;
if (noioapicquirk)
return;
- switch (dev->device) {
- case PCI_DEVICE_ID_INTEL_ESB_10:
- pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
- &pci_config_word);
- pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
- pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
- pci_config_word);
- break;
- case 0x3c28: /* Xeon E5 1600/2600/4600 */
- case 0x0e28: /* Xeon E5/E7 V2 */
- case 0x2f28: /* Xeon E5/E7 V3,V4 */
- case 0x6f28: /* Xeon D-1500 */
- case 0x2034: /* Xeon Scalable Family */
- pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
- &pci_config_dword);
- pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
- pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
- pci_config_dword);
- break;
- default:
- return;
- }
+ pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
+ pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
+ pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
+
pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
dev->vendor, dev->device);
}
-/*
- * Device 29 Func 5 Device IDs of IO-APIC
- * containing ABAR—APIC1 Alternate Base Address Register
- */
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
- quirk_disable_intel_boot_interrupt);
-
-/*
- * Device 5 Func 0 Device IDs of Core IO modules/hubs
- * containing Coherent Interface Protocol Interrupt Control
- *
- * Device IDs obtained from volume 2 datasheets of commented
- * families above.
- */
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
- quirk_disable_intel_boot_interrupt);
-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
- quirk_disable_intel_boot_interrupt);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
+DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
/* Disable boot interrupts on HT-1000 */
#define BC_HT1000_FEATURE_REG 0x64
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