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Bug#834505: arm64 boot failure with large physical memory range



On Fri, 2016-08-19 at 13:42 +0100, Leif Lindholm wrote:
> On Fri, Aug 19, 2016 at 12:50:49PM +0100, Ben Hutchings wrote:
> > 
> > > 
> > > > 
> > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > everything using mozilla-js).
> > > > [...]
> > > > 
> > > > Could we possibly work around that by reducing
> > > > CONFIG_ARCH_MMAP_RND_BITS_MAX?  (That's not directly configurable; it
> > > > requires patching arch/arm64/Kconfig.)
> > > 
> > > I think this would be opening up a real can of worms. Not all sizes
> > > are supported by the architecture, and only certain VA_BITS/pagesize
> > > combinations work in the kernel.
> > > 
> > > We could switch to 42-bit VA, but that would require switching to 64K
> > > pagesize, which would be an even huger can.
> > 
> > I'm not suggesting using any unusual page table configuration. Just
> > reducing the ASLR range that is currently implied by a 48-bit VA.
> 
> But would that help anything?
> Even if you don't allocate to the top bits, if they're used for
> tagging, you'll still segfault.

I seem to remember that AArch64 has the ill-advised rule that VA bits
outside the range of the current page table format are ignored, so
presumably you're concerned that the code relies on this.  But since
other 64-bit architectures (at least x86, PowerPC and SPARC) behave
otherwise, I would expect semi-portable code to mask out the tag bits.

Ben.

-- 
Ben Hutchings
It's easier to fight for one's principles than to live up to them.

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