I noticed some additional patches relevent to HiKey hit mainline, so
attempted to apply them to the linux 4.6 packages in debian.
With the following patches pulled from linux 4.7-rc1 and applied against
4.6-1~exp2 (which didn't actually get uploaded?), which is able to boot
a serial console and load an initrd, but not USB, eMMC or microSD... so
it's still not very useful.
I do get these messages:
[ 2.488036] Synopsys Designware Multimedia Card Interface Driver
[ 2.490010] i2c_designware f7100000.i2c: could not find pctldev for
node /soc/pinmux@f7010000/i2c0_pmx_func, deferring probe
[ 2.490038] i2c_designware f7101000.i2c: could not find pctldev for
node /soc/pinmux@f7010000/i2c1_pmx_func, deferring probe
[ 2.517901] dwmmc_k3 f723d000.dwmmc0: could not find pctldev for node
/soc/pinmux@f7010000/emmc_pmx_func, deferring probe
[ 2.528958] dwmmc_k3 f723e000.dwmmc1: could not find pctldev for node
/soc/pinmux@f7010000/sd_pmx_func, deferring probe
[ 2.539780] dwmmc_k3 f723f000.dwmmc2: could not find pctldev for node
/soc/pinmux@f7010000/sdio_pmx_func, deferring probe
Which seem to be relevent to eMMC/microSD...
I also was unable to get a working serial console with
0012-arm64-dts-hi6220-add-pinctrl-for-uarts-and-enable-th.patch applied,
so I've disabled it.
diff --git a/debian/config/arm64/config b/debian/config/arm64/config
index 5f30a22..d931b64 100644
--- a/debian/config/arm64/config
+++ b/debian/config/arm64/config
@@ -453,3 +453,13 @@ CONFIG_SND_SOC_TEGRA_ALC5632=m
CONFIG_SND_SOC_TEGRA_MAX98090=m
CONFIG_SND_SOC_TEGRA_RT5677=m
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WL18XX=m
+CONFIG_COMMON_RESET_HI6220=m
+CONFIG_PHY_HI6220_USB=m
+CONFIG_MAILBOX=y
+CONFIG_HI6220_MBOX=y
+CONFIG_REGULATOR_HI655X=m
+CONFIG_MFD_HI655X_PMIC=m
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_STUB_CLK_HI6220=y
diff --git a/debian/patches/hikey-4.7-rc1/0001-arm64-dts-Reserve-memory-regions-for-hi6220.patch b/debian/patches/hikey-4.7-rc1/0001-arm64-dts-Reserve-memory-regions-for-hi6220.patch
new file mode 100644
index 0000000..79b71a5
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0001-arm64-dts-Reserve-memory-regions-for-hi6220.patch
@@ -0,0 +1,59 @@
+From 6da3aba6f056b861c9f54ef104425ceb5e9389ad Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:37 +0800
+Subject: [PATCH 01/24] arm64: dts: Reserve memory regions for hi6220
+
+On Hi6220, below memory regions in DDR have specific purpose:
+
+ 0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
+ 0x06df,f000 - 0x06df,ffff: For mailbox message data;
+ 0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
+ 0x3e00,0000 - 0x3fff,ffff: For OP-TEE.
+
+This patch reserves these memory regions in DT.
+
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+index 8185251..17bd793 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -7,9 +7,6 @@
+
+ /dts-v1/;
+
+-/*Reserved 1MB memory for MCU*/
+-/memreserve/ 0x05e00000 0x00100000;
+-
+ #include "hi6220.dtsi"
+
+ / {
+@@ -27,9 +24,20 @@
+ stdout-path = "serial3:115200n8";
+ };
+
++ /*
++ * Reserve below regions from memory node:
++ *
++ * 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
++ * 0x06df,f000 - 0x06df,ffff: Mailbox message data
++ * 0x0740,f000 - 0x0740,ffff: MCU firmware section
++ * 0x3e00,0000 - 0x3fff,ffff: OP-TEE
++ */
+ memory@0 {
+ device_type = "memory";
+- reg = <0x0 0x0 0x0 0x40000000>;
++ reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
++ <0x00000000 0x05f00000 0x00000000 0x00eff000>,
++ <0x00000000 0x06e00000 0x00000000 0x0060f000>,
++ <0x00000000 0x07410000 0x00000000 0x36bf0000>;
+ };
+ };
+
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0002-arm64-dts-add-sp804-timer-node-for-Hi6220.patch b/debian/patches/hikey-4.7-rc1/0002-arm64-dts-add-sp804-timer-node-for-Hi6220.patch
new file mode 100644
index 0000000..9c7e6bd
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0002-arm64-dts-add-sp804-timer-node-for-Hi6220.patch
@@ -0,0 +1,37 @@
+From 9e92703165d982b3df35e551c4d15a93ab9fba3d Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:38 +0800
+Subject: [PATCH 02/24] arm64: dts: add sp804 timer node for Hi6220
+
+Add sp804 timer for hi6220, so it can be used as broadcast timer.
+
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index ad1f1eb..b975286 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -209,5 +209,16 @@
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
++
++ dual_timer0: timer@f8008000 {
++ compatible = "arm,sp804", "arm,primecell";
++ reg = <0x0 0xf8008000 0x0 0x1000>;
++ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
++ <&ao_ctrl HI6220_TIMER0_PCLK>,
++ <&ao_ctrl HI6220_TIMER0_PCLK>;
++ clock-names = "timer1", "timer2", "apb_pclk";
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0003-arm64-dts-enable-idle-states-for-Hi6220.patch b/debian/patches/hikey-4.7-rc1/0003-arm64-dts-enable-idle-states-for-Hi6220.patch
new file mode 100644
index 0000000..224cf48
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0003-arm64-dts-enable-idle-states-for-Hi6220.patch
@@ -0,0 +1,113 @@
+From 58fa29bfbe5e908e0f5d2627c5f15001696b1666 Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:39 +0800
+Subject: [PATCH 03/24] arm64: dts: enable idle states for Hi6220
+
+Add cpu and cluster level's low power state for Hi6220.
+
+Acked-by: Sudeep Holla <sudeep.holla@arm.com>
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index b975286..dc7f21a 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -53,11 +53,35 @@
+ };
+ };
+
++ idle-states {
++ entry-method = "psci";
++
++ CPU_SLEEP: cpu-sleep {
++ compatible = "arm,idle-state";
++ local-timer-stop;
++ arm,psci-suspend-param = <0x0010000>;
++ entry-latency-us = <700>;
++ exit-latency-us = <250>;
++ min-residency-us = <1000>;
++ };
++
++ CLUSTER_SLEEP: cluster-sleep {
++ compatible = "arm,idle-state";
++ local-timer-stop;
++ arm,psci-suspend-param = <0x1010000>;
++ entry-latency-us = <1000>;
++ exit-latency-us = <700>;
++ min-residency-us = <2700>;
++ wakeup-latency-us = <1500>;
++ };
++ };
++
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+ cpu1: cpu@1 {
+@@ -65,6 +89,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+ cpu2: cpu@2 {
+@@ -72,6 +97,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+ cpu3: cpu@3 {
+@@ -79,6 +105,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+ cpu4: cpu@100 {
+@@ -86,6 +113,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+ cpu5: cpu@101 {
+@@ -93,6 +121,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+ cpu6: cpu@102 {
+@@ -100,6 +129,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+ cpu7: cpu@103 {
+@@ -107,6 +137,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
++ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+ };
+
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0004-arm64-dts-Add-Hi6220-gpio-configuration-nodes.patch b/debian/patches/hikey-4.7-rc1/0004-arm64-dts-Add-Hi6220-gpio-configuration-nodes.patch
new file mode 100644
index 0000000..f8ec046
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0004-arm64-dts-Add-Hi6220-gpio-configuration-nodes.patch
@@ -0,0 +1,269 @@
+From f2bfacf9ddcff49103c08ee7e83bf3fffe6e37ba Mon Sep 17 00:00:00 2001
+From: Zhong Kaihua <zhongkaihua@huawei.com>
+Date: Wed, 13 Apr 2016 07:55:40 +0800
+Subject: [PATCH 04/24] arm64: dts: Add Hi6220 gpio configuration nodes
+
+Add Hi6220 gpio configuration nodes
+
+Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
+Signed-off-by: Kong Xinwei <kong.kongxinwei@hisilicon.com>
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 239 ++++++++++++++++++++++++++++++
+ 1 file changed, 239 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index dc7f21a..493bbb0 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -251,5 +251,244 @@
+ <&ao_ctrl HI6220_TIMER0_PCLK>;
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
++
++ gpio0: gpio@f8011000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf8011000 0x0 0x1000>;
++ interrupts = <0 52 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio1: gpio@f8012000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf8012000 0x0 0x1000>;
++ interrupts = <0 53 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio2: gpio@f8013000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf8013000 0x0 0x1000>;
++ interrupts = <0 54 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio3: gpio@f8014000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf8014000 0x0 0x1000>;
++ interrupts = <0 55 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio4: gpio@f7020000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7020000 0x0 0x1000>;
++ interrupts = <0 56 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio5: gpio@f7021000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7021000 0x0 0x1000>;
++ interrupts = <0 57 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio6: gpio@f7022000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7022000 0x0 0x1000>;
++ interrupts = <0 58 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio7: gpio@f7023000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7023000 0x0 0x1000>;
++ interrupts = <0 59 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio8: gpio@f7024000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7024000 0x0 0x1000>;
++ interrupts = <0 60 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio9: gpio@f7025000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7025000 0x0 0x1000>;
++ interrupts = <0 61 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio10: gpio@f7026000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7026000 0x0 0x1000>;
++ interrupts = <0 62 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio11: gpio@f7027000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7027000 0x0 0x1000>;
++ interrupts = <0 63 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio12: gpio@f7028000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7028000 0x0 0x1000>;
++ interrupts = <0 64 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio13: gpio@f7029000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf7029000 0x0 0x1000>;
++ interrupts = <0 65 0x4>;
++ gpio-controller;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio14: gpio@f702a000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf702a000 0x0 0x1000>;
++ interrupts = <0 66 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio15: gpio@f702b000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf702b000 0x0 0x1000>;
++ interrupts = <0 67 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio16: gpio@f702c000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf702c000 0x0 0x1000>;
++ interrupts = <0 68 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio17: gpio@f702d000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf702d000 0x0 0x1000>;
++ interrupts = <0 69 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio18: gpio@f702e000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf702e000 0x0 0x1000>;
++ interrupts = <0 70 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
++
++ gpio19: gpio@f702f000 {
++ compatible = "arm,pl061", "arm,primecell";
++ reg = <0x0 0xf702f000 0x0 0x1000>;
++ interrupts = <0 71 0x4>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ clocks = <&ao_ctrl 2>;
++ clock-names = "apb_pclk";
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0005-arm64-dts-add-Hi6220-pinctrl-configuration-nodes.patch b/debian/patches/hikey-4.7-rc1/0005-arm64-dts-add-Hi6220-pinctrl-configuration-nodes.patch
new file mode 100644
index 0000000..5b57a17
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0005-arm64-dts-add-Hi6220-pinctrl-configuration-nodes.patch
@@ -0,0 +1,1005 @@
+From 379e9bf52daaaa841ecc4eed3f2c5c86845c45a9 Mon Sep 17 00:00:00 2001
+From: Zhong Kaihua <zhongkaihua@huawei.com>
+Date: Wed, 13 Apr 2016 07:55:41 +0800
+Subject: [PATCH 05/24] arm64: dts: add Hi6220 pinctrl configuration nodes
+
+Add Hi6220 pinctrl configuration nodes
+
+Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
+Acked-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 1 +
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 77 +++
+ arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi | 684 +++++++++++++++++++++++
+ include/dt-bindings/pinctrl/hisi.h | 59 ++
+ 4 files changed, 821 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
+ create mode 100644 include/dt-bindings/pinctrl/hisi.h
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+index 17bd793..3d9e8b2 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -8,6 +8,7 @@
+ /dts-v1/;
+
+ #include "hi6220.dtsi"
++#include "hikey-pinctrl.dtsi"
+
+ / {
+ model = "HiKey Development Board";
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index 493bbb0..df56571 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -6,6 +6,7 @@
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/hi6220-clock.h>
++#include <dt-bindings/pinctrl/hisi.h>
+
+ / {
+ compatible = "hisilicon,hi6220";
+@@ -252,6 +253,60 @@
+ clock-names = "timer1", "timer2", "apb_pclk";
+ };
+
++ pmx0: pinmux@f7010000 {
++ compatible = "pinctrl-single";
++ reg = <0x0 0xf7010000 0x0 0x27c>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ #gpio-range-cells = <3>;
++ pinctrl-single,register-width = <32>;
++ pinctrl-single,function-mask = <7>;
++ pinctrl-single,gpio-range = <
++ &range 80 8 MUX_M0 /* gpio 3: [0..7] */
++ &range 88 8 MUX_M0 /* gpio 4: [0..7] */
++ &range 96 8 MUX_M0 /* gpio 5: [0..7] */
++ &range 104 8 MUX_M0 /* gpio 6: [0..7] */
++ &range 112 8 MUX_M0 /* gpio 7: [0..7] */
++ &range 120 2 MUX_M0 /* gpio 8: [0..1] */
++ &range 2 6 MUX_M1 /* gpio 8: [2..7] */
++ &range 8 8 MUX_M1 /* gpio 9: [0..7] */
++ &range 0 1 MUX_M1 /* gpio 10: [0] */
++ &range 16 7 MUX_M1 /* gpio 10: [1..7] */
++ &range 23 3 MUX_M1 /* gpio 11: [0..2] */
++ &range 28 5 MUX_M1 /* gpio 11: [3..7] */
++ &range 33 3 MUX_M1 /* gpio 12: [0..2] */
++ &range 43 5 MUX_M1 /* gpio 12: [3..7] */
++ &range 48 8 MUX_M1 /* gpio 13: [0..7] */
++ &range 56 8 MUX_M1 /* gpio 14: [0..7] */
++ &range 74 6 MUX_M1 /* gpio 15: [0..5] */
++ &range 122 1 MUX_M1 /* gpio 15: [6] */
++ &range 126 1 MUX_M1 /* gpio 15: [7] */
++ &range 127 8 MUX_M1 /* gpio 16: [0..7] */
++ &range 135 8 MUX_M1 /* gpio 17: [0..7] */
++ &range 143 8 MUX_M1 /* gpio 18: [0..7] */
++ &range 151 8 MUX_M1 /* gpio 19: [0..7] */
++ >;
++ range: gpio-range {
++ #pinctrl-single,gpio-range-cells = <3>;
++ };
++ };
++
++ pmx1: pinmux@f7010800 {
++ compatible = "pinconf-single";
++ reg = <0x0 0xf7010800 0x0 0x28c>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ pinctrl-single,register-width = <32>;
++ };
++
++ pmx2: pinmux@f8001800 {
++ compatible = "pinconf-single";
++ reg = <0x0 0xf8001800 0x0 0x78>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ pinctrl-single,register-width = <32>;
++ };
++
+ gpio0: gpio@f8011000 {
+ compatible = "arm,pl061", "arm,primecell";
+ reg = <0x0 0xf8011000 0x0 0x1000>;
+@@ -294,6 +349,7 @@
+ interrupts = <0 55 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 80 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -306,6 +362,7 @@
+ interrupts = <0 56 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 88 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -318,6 +375,7 @@
+ interrupts = <0 57 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 96 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -330,6 +388,7 @@
+ interrupts = <0 58 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 104 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -342,6 +401,7 @@
+ interrupts = <0 59 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 112 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -354,6 +414,7 @@
+ interrupts = <0 60 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -366,6 +427,7 @@
+ interrupts = <0 61 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 8 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -378,6 +440,7 @@
+ interrupts = <0 62 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -390,6 +453,7 @@
+ interrupts = <0 63 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -402,6 +466,7 @@
+ interrupts = <0 64 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -413,6 +478,8 @@
+ reg = <0x0 0xf7029000 0x0 0x1000>;
+ interrupts = <0 65 0x4>;
+ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 48 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -425,6 +492,7 @@
+ interrupts = <0 66 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 56 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -437,6 +505,11 @@
+ interrupts = <0 67 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <
++ &pmx0 0 74 6
++ &pmx0 6 122 1
++ &pmx0 7 126 1
++ >;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -449,6 +522,7 @@
+ interrupts = <0 68 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 127 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -461,6 +535,7 @@
+ interrupts = <0 69 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 135 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -473,6 +548,7 @@
+ interrupts = <0 70 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 143 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+@@ -485,6 +561,7 @@
+ interrupts = <0 71 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
++ gpio-ranges = <&pmx0 0 151 8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&ao_ctrl 2>;
+diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
+new file mode 100644
+index 0000000..28806df
+--- /dev/null
++++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
+@@ -0,0 +1,684 @@
++/*
++ * pinctrl dts fils for Hislicon HiKey development board
++ *
++ */
++#include <dt-bindings/pinctrl/hisi.h>
++
++/ {
++ soc {
++ pmx0: pinmux@f7010000 {
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &boot_sel_pmx_func
++ &hkadc_ssi_pmx_func
++ &codec_clk_pmx_func
++ &pwm_in_pmx_func
++ &bl_pwm_pmx_func
++ >;
++
++ boot_sel_pmx_func: boot_sel_pmx_func {
++ pinctrl-single,pins = <
++ 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
++ >;
++ };
++
++ emmc_pmx_func: emmc_pmx_func {
++ pinctrl-single,pins = <
++ 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
++ 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
++ 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
++ 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
++ 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
++ 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
++ 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
++ 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
++ 0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
++ 0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */
++ >;
++ };
++
++ sd_pmx_func: sd_pmx_func {
++ pinctrl-single,pins = <
++ 0xc MUX_M0 /* SD_CLK (IOMG003) */
++ 0x10 MUX_M0 /* SD_CMD (IOMG004) */
++ 0x14 MUX_M0 /* SD_DATA0 (IOMG005) */
++ 0x18 MUX_M0 /* SD_DATA1 (IOMG006) */
++ 0x1c MUX_M0 /* SD_DATA2 (IOMG007) */
++ 0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
++ >;
++ };
++ sd_pmx_idle: sd_pmx_idle {
++ pinctrl-single,pins = <
++ 0xc MUX_M1 /* SD_CLK (IOMG003) */
++ 0x10 MUX_M1 /* SD_CMD (IOMG004) */
++ 0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
++ 0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
++ 0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
++ 0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
++ >;
++ };
++
++ sdio_pmx_func: sdio_pmx_func {
++ pinctrl-single,pins = <
++ 0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
++ 0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
++ 0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */
++ 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
++ 0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */
++ 0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
++ >;
++ };
++ sdio_pmx_idle: sdio_pmx_idle {
++ pinctrl-single,pins = <
++ 0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
++ 0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
++ 0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
++ 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
++ 0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */
++ 0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */
++ >;
++ };
++
++ isp_pmx_func: isp_pmx_func {
++ pinctrl-single,pins = <
++ 0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
++ 0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
++ 0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */
++ 0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */
++ 0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */
++ 0x38 MUX_M1 /* ISP_PWM (IOMG014) */
++ 0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */
++ 0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */
++ 0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */
++ 0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */
++ 0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */
++ 0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */
++ 0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */
++ 0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */
++ 0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */
++ 0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */
++ >;
++ };
++
++ hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
++ pinctrl-single,pins = <
++ 0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
++ >;
++ };
++
++ codec_clk_pmx_func: codec_clk_pmx_func {
++ pinctrl-single,pins = <
++ 0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
++ >;
++ };
++
++ codec_pmx_func: codec_pmx_func {
++ pinctrl-single,pins = <
++ 0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
++ 0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
++ 0x78 MUX_M0 /* CODEC_DI (IOMG030) */
++ 0x7c MUX_M0 /* CODEC_DO (IOMG031) */
++ >;
++ };
++
++ fm_pmx_func: fm_pmx_func {
++ pinctrl-single,pins = <
++ 0x80 MUX_M1 /* FM_XCLK (IOMG032) */
++ 0x84 MUX_M1 /* FM_XFS (IOMG033) */
++ 0x88 MUX_M1 /* FM_DI (IOMG034) */
++ 0x8c MUX_M1 /* FM_DO (IOMG035) */
++ >;
++ };
++
++ bt_pmx_func: bt_pmx_func {
++ pinctrl-single,pins = <
++ 0x90 MUX_M0 /* BT_XCLK (IOMG036) */
++ 0x94 MUX_M0 /* BT_XFS (IOMG037) */
++ 0x98 MUX_M0 /* BT_DI (IOMG038) */
++ 0x9c MUX_M0 /* BT_DO (IOMG039) */
++ >;
++ };
++
++ pwm_in_pmx_func: pwm_in_pmx_func {
++ pinctrl-single,pins = <
++ 0xb8 MUX_M1 /* PWM_IN (IOMG046) */
++ >;
++ };
++
++ bl_pwm_pmx_func: bl_pwm_pmx_func {
++ pinctrl-single,pins = <
++ 0xbc MUX_M1 /* BL_PWM (IOMG047) */
++ >;
++ };
++
++ uart0_pmx_func: uart0_pmx_func {
++ pinctrl-single,pins = <
++ 0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
++ 0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
++ >;
++ };
++
++ uart1_pmx_func: uart1_pmx_func {
++ pinctrl-single,pins = <
++ 0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
++ 0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
++ 0xd0 MUX_M0 /* UART1_RXD (IOMG052) */
++ 0xd4 MUX_M0 /* UART1_TXD (IOMG053) */
++ >;
++ };
++
++ uart2_pmx_func: uart2_pmx_func {
++ pinctrl-single,pins = <
++ 0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
++ 0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
++ 0xe0 MUX_M0 /* UART2_RXD (IOMG056) */
++ 0xe4 MUX_M0 /* UART2_TXD (IOMG057) */
++ >;
++ };
++
++ uart3_pmx_func: uart3_pmx_func {
++ pinctrl-single,pins = <
++ 0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
++ 0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
++ 0x188 MUX_M1 /* UART3_RXD (IOMG098) */
++ 0x18c MUX_M1 /* UART3_TXD (IOMG099) */
++ >;
++ };
++
++ uart4_pmx_func: uart4_pmx_func {
++ pinctrl-single,pins = <
++ 0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
++ 0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
++ 0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */
++ 0x1dc MUX_M1 /* UART4_TXD (IOMG119) */
++ >;
++ };
++
++ uart5_pmx_func: uart5_pmx_func {
++ pinctrl-single,pins = <
++ 0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
++ 0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
++ >;
++ };
++
++ i2c0_pmx_func: i2c0_pmx_func {
++ pinctrl-single,pins = <
++ 0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
++ 0xec MUX_M0 /* I2C0_SDA (IOMG059) */
++ >;
++ };
++
++ i2c1_pmx_func: i2c1_pmx_func {
++ pinctrl-single,pins = <
++ 0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
++ 0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
++ >;
++ };
++
++ i2c2_pmx_func: i2c2_pmx_func {
++ pinctrl-single,pins = <
++ 0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
++ 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
++ >;
++ };
++ };
++
++ pmx1: pinmux@f7010800 {
++
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &boot_sel_cfg_func
++ &hkadc_ssi_cfg_func
++ &codec_clk_cfg_func
++ &pwm_in_cfg_func
++ &bl_pwm_cfg_func
++ >;
++
++ boot_sel_cfg_func: boot_sel_cfg_func {
++ pinctrl-single,pins = <
++ 0x0 0x0 /* BOOT_SEL (IOCFG000) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
++ pinctrl-single,pins = <
++ 0x6c 0x0 /* HKADC_SSI (IOCFG027) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ emmc_clk_cfg_func: emmc_clk_cfg_func {
++ pinctrl-single,pins = <
++ 0x104 0x0 /* EMMC_CLK (IOCFG065) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
++ };
++
++ emmc_cfg_func: emmc_cfg_func {
++ pinctrl-single,pins = <
++ 0x108 0x0 /* EMMC_CMD (IOCFG066) */
++ 0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
++ 0x110 0x0 /* EMMC_DATA1 (IOCFG068) */
++ 0x114 0x0 /* EMMC_DATA2 (IOCFG069) */
++ 0x118 0x0 /* EMMC_DATA3 (IOCFG070) */
++ 0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */
++ 0x120 0x0 /* EMMC_DATA5 (IOCFG072) */
++ 0x124 0x0 /* EMMC_DATA6 (IOCFG073) */
++ 0x128 0x0 /* EMMC_DATA7 (IOCFG074) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
++ };
++
++ emmc_rst_cfg_func: emmc_rst_cfg_func {
++ pinctrl-single,pins = <
++ 0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
++ };
++
++ sd_clk_cfg_func: sd_clk_cfg_func {
++ pinctrl-single,pins = <
++ 0xc 0x0 /* SD_CLK (IOCFG003) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
++ };
++ sd_clk_cfg_idle: sd_clk_cfg_idle {
++ pinctrl-single,pins = <
++ 0xc 0x0 /* SD_CLK (IOCFG003) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ sd_cfg_func: sd_cfg_func {
++ pinctrl-single,pins = <
++ 0x10 0x0 /* SD_CMD (IOCFG004) */
++ 0x14 0x0 /* SD_DATA0 (IOCFG005) */
++ 0x18 0x0 /* SD_DATA1 (IOCFG006) */
++ 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
++ 0x20 0x0 /* SD_DATA3 (IOCFG008) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
++ };
++ sd_cfg_idle: sd_cfg_idle {
++ pinctrl-single,pins = <
++ 0x10 0x0 /* SD_CMD (IOCFG004) */
++ 0x14 0x0 /* SD_DATA0 (IOCFG005) */
++ 0x18 0x0 /* SD_DATA1 (IOCFG006) */
++ 0x1c 0x0 /* SD_DATA2 (IOCFG007) */
++ 0x20 0x0 /* SD_DATA3 (IOCFG008) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ sdio_clk_cfg_func: sdio_clk_cfg_func {
++ pinctrl-single,pins = <
++ 0x134 0x0 /* SDIO_CLK (IOCFG077) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
++ };
++ sdio_clk_cfg_idle: sdio_clk_cfg_idle {
++ pinctrl-single,pins = <
++ 0x134 0x0 /* SDIO_CLK (IOCFG077) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ sdio_cfg_func: sdio_cfg_func {
++ pinctrl-single,pins = <
++ 0x138 0x0 /* SDIO_CMD (IOCFG078) */
++ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
++ 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
++ 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
++ 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
++ };
++ sdio_cfg_idle: sdio_cfg_idle {
++ pinctrl-single,pins = <
++ 0x138 0x0 /* SDIO_CMD (IOCFG078) */
++ 0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
++ 0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
++ 0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
++ 0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ isp_cfg_func1: isp_cfg_func1 {
++ pinctrl-single,pins = <
++ 0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
++ 0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
++ 0x30 0x0 /* ISP_PWDN2 (IOCFG012) */
++ 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
++ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
++ 0x3c 0x0 /* ISP_PWM (IOCFG015) */
++ 0x40 0x0 /* ISP_CCLK0 (IOCFG016) */
++ 0x44 0x0 /* ISP_CCLK1 (IOCFG017) */
++ 0x48 0x0 /* ISP_RESETB0 (IOCFG018) */
++ 0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */
++ 0x50 0x0 /* ISP_STROBE0 (IOCFG020) */
++ 0x58 0x0 /* ISP_SDA0 (IOCFG022) */
++ 0x5c 0x0 /* ISP_SCL0 (IOCFG023) */
++ 0x60 0x0 /* ISP_SDA1 (IOCFG024) */
++ 0x64 0x0 /* ISP_SCL1 (IOCFG025) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++ isp_cfg_idle1: isp_cfg_idle1 {
++ pinctrl-single,pins = <
++ 0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
++ 0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ isp_cfg_func2: isp_cfg_func2 {
++ pinctrl-single,pins = <
++ 0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ codec_clk_cfg_func: codec_clk_cfg_func {
++ pinctrl-single,pins = <
++ 0x70 0x0 /* CODEC_CLK (IOCFG028) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
++ };
++ codec_clk_cfg_idle: codec_clk_cfg_idle {
++ pinctrl-single,pins = <
++ 0x70 0x0 /* CODEC_CLK (IOCFG028) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ codec_cfg_func1: codec_cfg_func1 {
++ pinctrl-single,pins = <
++ 0x74 0x0 /* DMIC_CLK (IOCFG029) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ codec_cfg_func2: codec_cfg_func2 {
++ pinctrl-single,pins = <
++ 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
++ 0x7c 0x0 /* CODEC_DI (IOCFG031) */
++ 0x80 0x0 /* CODEC_DO (IOCFG032) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
++ };
++ codec_cfg_idle2: codec_cfg_idle2 {
++ pinctrl-single,pins = <
++ 0x78 0x0 /* CODEC_SYNC (IOCFG030) */
++ 0x7c 0x0 /* CODEC_DI (IOCFG031) */
++ 0x80 0x0 /* CODEC_DO (IOCFG032) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ fm_cfg_func: fm_cfg_func {
++ pinctrl-single,pins = <
++ 0x84 0x0 /* FM_XCLK (IOCFG033) */
++ 0x88 0x0 /* FM_XFS (IOCFG034) */
++ 0x8c 0x0 /* FM_DI (IOCFG035) */
++ 0x90 0x0 /* FM_DO (IOCFG036) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ bt_cfg_func: bt_cfg_func {
++ pinctrl-single,pins = <
++ 0x94 0x0 /* BT_XCLK (IOCFG037) */
++ 0x98 0x0 /* BT_XFS (IOCFG038) */
++ 0x9c 0x0 /* BT_DI (IOCFG039) */
++ 0xa0 0x0 /* BT_DO (IOCFG040) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++ bt_cfg_idle: bt_cfg_idle {
++ pinctrl-single,pins = <
++ 0x94 0x0 /* BT_XCLK (IOCFG037) */
++ 0x98 0x0 /* BT_XFS (IOCFG038) */
++ 0x9c 0x0 /* BT_DI (IOCFG039) */
++ 0xa0 0x0 /* BT_DO (IOCFG040) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ pwm_in_cfg_func: pwm_in_cfg_func {
++ pinctrl-single,pins = <
++ 0xbc 0x0 /* PWM_IN (IOCFG047) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ bl_pwm_cfg_func: bl_pwm_cfg_func {
++ pinctrl-single,pins = <
++ 0xc0 0x0 /* BL_PWM (IOCFG048) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ uart0_cfg_func1: uart0_cfg_func1 {
++ pinctrl-single,pins = <
++ 0xc4 0x0 /* UART0_RXD (IOCFG049) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ uart0_cfg_func2: uart0_cfg_func2 {
++ pinctrl-single,pins = <
++ 0xc8 0x0 /* UART0_TXD (IOCFG050) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
++ };
++
++ uart1_cfg_func1: uart1_cfg_func1 {
++ pinctrl-single,pins = <
++ 0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
++ 0xd4 0x0 /* UART1_RXD (IOCFG053) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ uart1_cfg_func2: uart1_cfg_func2 {
++ pinctrl-single,pins = <
++ 0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
++ 0xd8 0x0 /* UART1_TXD (IOCFG054) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ uart2_cfg_func: uart2_cfg_func {
++ pinctrl-single,pins = <
++ 0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
++ 0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
++ 0xe4 0x0 /* UART2_RXD (IOCFG057) */
++ 0xe8 0x0 /* UART2_TXD (IOCFG058) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ uart3_cfg_func: uart3_cfg_func {
++ pinctrl-single,pins = <
++ 0x190 0x0 /* UART3_CTS_N (IOCFG100) */
++ 0x194 0x0 /* UART3_RTS_N (IOCFG101) */
++ 0x198 0x0 /* UART3_RXD (IOCFG102) */
++ 0x19c 0x0 /* UART3_TXD (IOCFG103) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ uart4_cfg_func: uart4_cfg_func {
++ pinctrl-single,pins = <
++ 0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
++ 0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
++ 0x1e8 0x0 /* UART4_RXD (IOCFG122) */
++ 0x1ec 0x0 /* UART4_TXD (IOCFG123) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ uart5_cfg_func: uart5_cfg_func {
++ pinctrl-single,pins = <
++ 0x1d8 0x0 /* UART4_RXD (IOCFG118) */
++ 0x1dc 0x0 /* UART4_TXD (IOCFG119) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ i2c0_cfg_func: i2c0_cfg_func {
++ pinctrl-single,pins = <
++ 0xec 0x0 /* I2C0_SCL (IOCFG059) */
++ 0xf0 0x0 /* I2C0_SDA (IOCFG060) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ i2c1_cfg_func: i2c1_cfg_func {
++ pinctrl-single,pins = <
++ 0xf4 0x0 /* I2C1_SCL (IOCFG061) */
++ 0xf8 0x0 /* I2C1_SDA (IOCFG062) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ i2c2_cfg_func: i2c2_cfg_func {
++ pinctrl-single,pins = <
++ 0xfc 0x0 /* I2C2_SCL (IOCFG063) */
++ 0x100 0x0 /* I2C2_SDA (IOCFG064) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++ };
++
++ pmx2: pinmux@f8001800 {
++
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &rstout_n_cfg_func
++ >;
++
++ rstout_n_cfg_func: rstout_n_cfg_func {
++ pinctrl-single,pins = <
++ 0x0 0x0 /* RSTOUT_N (IOCFG000) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
++ pinctrl-single,pins = <
++ 0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ sysclk0_en_cfg_func: sysclk0_en_cfg_func {
++ pinctrl-single,pins = <
++ 0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++
++ jtag_tdo_cfg_func: jtag_tdo_cfg_func {
++ pinctrl-single,pins = <
++ 0xc 0x0 /* JTAG_TDO (IOCFG003) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
++ };
++
++ rf_reset_cfg_func: rf_reset_cfg_func {
++ pinctrl-single,pins = <
++ 0x70 0x0 /* RF_RESET0 (IOCFG028) */
++ 0x74 0x0 /* RF_RESET1 (IOCFG029) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
++ };
++ };
++};
+diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
+new file mode 100644
+index 0000000..38f1ea8
+--- /dev/null
++++ b/include/dt-bindings/pinctrl/hisi.h
+@@ -0,0 +1,59 @@
++/*
++ * This header provides constants for hisilicon pinctrl bindings.
++ *
++ * Copyright (c) 2015 Hisilicon Limited.
++ * Copyright (c) 2015 Linaro Limited.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#ifndef _DT_BINDINGS_PINCTRL_HISI_H
++#define _DT_BINDINGS_PINCTRL_HISI_H
++
++/* iomg bit definition */
++#define MUX_M0 0
++#define MUX_M1 1
++#define MUX_M2 2
++#define MUX_M3 3
++#define MUX_M4 4
++#define MUX_M5 5
++#define MUX_M6 6
++#define MUX_M7 7
++
++/* iocg bit definition */
++#define PULL_MASK (3)
++#define PULL_DIS (0)
++#define PULL_UP (1 << 0)
++#define PULL_DOWN (1 << 1)
++
++/* drive strength definition */
++#define DRIVE_MASK (7 << 4)
++#define DRIVE1_02MA (0 << 4)
++#define DRIVE1_04MA (1 << 4)
++#define DRIVE1_08MA (2 << 4)
++#define DRIVE1_10MA (3 << 4)
++#define DRIVE2_02MA (0 << 4)
++#define DRIVE2_04MA (1 << 4)
++#define DRIVE2_08MA (2 << 4)
++#define DRIVE2_10MA (3 << 4)
++#define DRIVE3_04MA (0 << 4)
++#define DRIVE3_08MA (1 << 4)
++#define DRIVE3_12MA (2 << 4)
++#define DRIVE3_16MA (3 << 4)
++#define DRIVE3_20MA (4 << 4)
++#define DRIVE3_24MA (5 << 4)
++#define DRIVE3_32MA (6 << 4)
++#define DRIVE3_40MA (7 << 4)
++#define DRIVE4_02MA (0 << 4)
++#define DRIVE4_04MA (2 << 4)
++#define DRIVE4_08MA (4 << 4)
++#define DRIVE4_10MA (6 << 4)
++
++#endif
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0006-arm64-dts-add-Hi6220-spi-configuration-nodes.patch b/debian/patches/hikey-4.7-rc1/0006-arm64-dts-add-Hi6220-spi-configuration-nodes.patch
new file mode 100644
index 0000000..6c6b4d9
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0006-arm64-dts-add-Hi6220-spi-configuration-nodes.patch
@@ -0,0 +1,102 @@
+From 60dac1b19b6af6ddc4df68d163e2d7508057c007 Mon Sep 17 00:00:00 2001
+From: Zhong Kaihua <zhongkaihua@huawei.com>
+Date: Wed, 13 Apr 2016 07:55:42 +0800
+Subject: [PATCH 06/24] arm64: dts: add Hi6220 spi configuration nodes
+
+Add Hi6220 spi configuration nodes. Disable by default in hi6220.dtsi
+and enable it in board dts for usage of 96boards LS mezzanine board.
+
+Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
+Signed-off-by: Guodong Xu <guodong.xu@linaro.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 6 ++++++
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 15 +++++++++++++++
+ arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi | 21 +++++++++++++++++++++
+ 3 files changed, 42 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+index 3d9e8b2..7545e36 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -40,6 +40,12 @@
+ <0x00000000 0x06e00000 0x00000000 0x0060f000>,
+ <0x00000000 0x07410000 0x00000000 0x36bf0000>;
+ };
++
++ soc {
++ spi0: spi@f7106000 {
++ status = "ok";
++ };
++ };
+ };
+
+ &uart2 {
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index df56571..7bcfffe 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -567,5 +567,20 @@
+ clocks = <&ao_ctrl 2>;
+ clock-names = "apb_pclk";
+ };
++
++ spi0: spi@f7106000 {
++ compatible = "arm,pl022", "arm,primecell";
++ reg = <0x0 0xf7106000 0x0 0x1000>;
++ interrupts = <0 50 4>;
++ bus-id = <0>;
++ enable-dma = <0>;
++ clocks = <&sys_ctrl HI6220_SPI_CLK>;
++ clock-names = "apb_pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
++ num-cs = <1>;
++ cs-gpios = <&gpio6 2 0>;
++ status = "disabled";
++ };
+ };
+ };
+diff --git a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
+index 28806df..0916e84 100644
+--- a/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hikey-pinctrl.dtsi
+@@ -221,6 +221,15 @@
+ 0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
+ >;
+ };
++
++ spi0_pmx_func: spi0_pmx_func {
++ pinctrl-single,pins = <
++ 0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */
++ 0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */
++ 0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */
++ 0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */
++ >;
++ };
+ };
+
+ pmx1: pinmux@f7010800 {
+@@ -625,6 +634,18 @@
+ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
+ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
+ };
++
++ spi0_cfg_func: spi0_cfg_func {
++ pinctrl-single,pins = <
++ 0x1b0 0x0 /* SPI0_DI (IOCFG108) */
++ 0x1b4 0x0 /* SPI0_DO (IOCFG109) */
++ 0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */
++ 0x1bc 0x0 /* SPI0_CLK (IOCFG111) */
++ >;
++ pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
++ pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
++ pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
++ };
+ };
+
+ pmx2: pinmux@f8001800 {
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0007-arm64-dts-add-all-hi6220-i2c-nodes.patch b/debian/patches/hikey-4.7-rc1/0007-arm64-dts-add-all-hi6220-i2c-nodes.patch
new file mode 100644
index 0000000..4565590
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0007-arm64-dts-add-all-hi6220-i2c-nodes.patch
@@ -0,0 +1,61 @@
+From 5ff3a4ddd142ac2ac4e6d4aa65cf0f7bf2d9679a Mon Sep 17 00:00:00 2001
+From: Xinwei Kong <kong.kongxinwei@hisilicon.com>
+Date: Wed, 13 Apr 2016 07:55:43 +0800
+Subject: [PATCH 07/24] arm64: dts: add all hi6220 i2c nodes
+
+This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
+use this I2C IP of Synopsys Designware for HiKey board.
+
+Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
+Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 33 +++++++++++++++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index 7bcfffe..4fc0347 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -582,5 +582,38 @@
+ cs-gpios = <&gpio6 2 0>;
+ status = "disabled";
+ };
++
++ i2c0: i2c@f7100000 {
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0xf7100000 0x0 0x1000>;
++ interrupts = <0 44 4>;
++ clocks = <&sys_ctrl HI6220_I2C0_CLK>;
++ i2c-sda-hold-time-ns = <300>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@f7101000 {
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0xf7101000 0x0 0x1000>;
++ clocks = <&sys_ctrl HI6220_I2C1_CLK>;
++ interrupts = <0 45 4>;
++ i2c-sda-hold-time-ns = <300>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@f7102000 {
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0xf7102000 0x0 0x1000>;
++ clocks = <&sys_ctrl HI6220_I2C2_CLK>;
++ interrupts = <0 46 4>;
++ i2c-sda-hold-time-ns = <300>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
++ status = "disabled";
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0008-arm64-dts-hikey-enable-i2c0-and-i2c1-for-working-wit.patch b/debian/patches/hikey-4.7-rc1/0008-arm64-dts-hikey-enable-i2c0-and-i2c1-for-working-wit.patch
new file mode 100644
index 0000000..3415787
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0008-arm64-dts-hikey-enable-i2c0-and-i2c1-for-working-wit.patch
@@ -0,0 +1,37 @@
+From 0c2317512d51f62401fdb7dd9d2ab5c932ac0ab9 Mon Sep 17 00:00:00 2001
+From: Guodong Xu <guodong.xu@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:44 +0800
+Subject: [PATCH 08/24] arm64: dts: hikey: enable i2c0 and i2c1 for working
+ with mezzanine boards
+
+In HiKey board dts file, enable i2c0 and i2c1 for working with 96boards' LS
+mezzanine.
+
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+index 7545e36..3dbf51b 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -45,6 +45,14 @@
+ spi0: spi@f7106000 {
+ status = "ok";
+ };
++
++ i2c0: i2c@f7100000 {
++ status = "ok";
++ };
++
++ i2c1: i2c@f7101000 {
++ status = "ok";
++ };
+ };
+ };
+
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0009-arm64-dts-Add-hi6220-usb-node.patch b/debian/patches/hikey-4.7-rc1/0009-arm64-dts-Add-hi6220-usb-node.patch
new file mode 100644
index 0000000..046d143
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0009-arm64-dts-Add-hi6220-usb-node.patch
@@ -0,0 +1,59 @@
+From b4b31a7cd797dcadba32a2f283923aec7583462e Mon Sep 17 00:00:00 2001
+From: Zhangfei Gao <zhangfei.gao@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:45 +0800
+Subject: [PATCH 09/24] arm64: dts: Add hi6220 usb node
+
+Add USB nodes for Hi6220
+
+Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 32 +++++++++++++++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index 4fc0347..4d1d31f 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -615,5 +615,37 @@
+ pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
+ status = "disabled";
+ };
++
++ fixed_5v_hub: regulator@0 {
++ compatible = "regulator-fixed";
++ regulator-name = "fixed_5v_hub";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-boot-on;
++ gpio = <&gpio0 7 0>;
++ regulator-always-on;
++ };
++
++ usb_phy: usbphy {
++ compatible = "hisilicon,hi6220-usb-phy";
++ #phy-cells = <0>;
++ phy-supply = <&fixed_5v_hub>;
++ hisilicon,peripheral-syscon = <&sys_ctrl>;
++ };
++
++ usb: usb@f72c0000 {
++ compatible = "hisilicon,hi6220-usb";
++ reg = <0x0 0xf72c0000 0x0 0x40000>;
++ phys = <&usb_phy>;
++ phy-names = "usb2-phy";
++ clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
++ clock-names = "otg";
++ dr_mode = "otg";
++ g-use-dma;
++ g-rx-fifo-size = <512>;
++ g-np-tx-fifo-size = <128>;
++ g-tx-fifo-size = <128 128 128 128 128 128>;
++ interrupts = <0 77 0x4>;
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0010-arm64-dts-add-mailbox-node-for-Hi6220.patch b/debian/patches/hikey-4.7-rc1/0010-arm64-dts-add-mailbox-node-for-Hi6220.patch
new file mode 100644
index 0000000..78c0333
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0010-arm64-dts-add-mailbox-node-for-Hi6220.patch
@@ -0,0 +1,35 @@
+From 8607357016f6b643787727cf35ecdcfb49c3cf23 Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:46 +0800
+Subject: [PATCH 10/24] arm64: dts: add mailbox node for Hi6220
+
+This patch add device mailbox node for Hi6220 in DT.
+
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index 4d1d31f..d71c51f 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -647,5 +647,13 @@
+ g-tx-fifo-size = <128 128 128 128 128 128>;
+ interrupts = <0 77 0x4>;
+ };
++
++ mailbox: mailbox@f7510000 {
++ compatible = "hisilicon,hi6220-mbox";
++ reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
++ <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
++ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
++ #mbox-cells = <3>;
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0011-arm64-dts-add-Hi6220-s-stub-clock-node.patch b/debian/patches/hikey-4.7-rc1/0011-arm64-dts-add-Hi6220-s-stub-clock-node.patch
new file mode 100644
index 0000000..33825c3
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0011-arm64-dts-add-Hi6220-s-stub-clock-node.patch
@@ -0,0 +1,156 @@
+From 998605407249dd278aef28c1cc2ce00f90c09eaa Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:47 +0800
+Subject: [PATCH 11/24] arm64: dts: add Hi6220's stub clock node
+
+Enable SRAM node and stub clock node for Hi6220, which uses mailbox
+channel 1 for CPU's frequency change.
+
+Furthermore, add the CPU clock phandle in CPU's node and using
+operating-points-v2 to register operating points. So can be used by
+cpufreq-dt driver.
+
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 56 +++++++++++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index d71c51f..3a665ef 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -82,6 +82,11 @@
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
++ clocks = <&stub_clock 0>;
++ operating-points-v2 = <&cpu_opp_table>;
++ cooling-min-level = <4>;
++ cooling-max-level = <0>;
++ #cooling-cells = <2>; /* min followed by max */
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+@@ -90,6 +95,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
++ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+@@ -98,6 +104,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
++ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+@@ -106,6 +113,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
++ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+@@ -114,6 +122,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
++ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+@@ -122,6 +131,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
++ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+@@ -130,6 +140,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
++ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+
+@@ -138,10 +149,42 @@
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
++ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+ };
+
++ cpu_opp_table: cpu_opp_table {
++ compatible = "operating-points-v2";
++ opp-shared;
++
++ opp00 {
++ opp-hz = /bits/ 64 <208000000>;
++ opp-microvolt = <1040000>;
++ clock-latency-ns = <500000>;
++ };
++ opp01 {
++ opp-hz = /bits/ 64 <432000000>;
++ opp-microvolt = <1040000>;
++ clock-latency-ns = <500000>;
++ };
++ opp02 {
++ opp-hz = /bits/ 64 <729000000>;
++ opp-microvolt = <1090000>;
++ clock-latency-ns = <500000>;
++ };
++ opp03 {
++ opp-hz = /bits/ 64 <960000000>;
++ opp-microvolt = <1180000>;
++ clock-latency-ns = <500000>;
++ };
++ opp04 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt = <1330000>;
++ clock-latency-ns = <500000>;
++ };
++ };
++
+ gic: interrupt-controller@f6801000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
+@@ -169,6 +212,11 @@
+ #size-cells = <2>;
+ ranges;
+
++ sram: sram@fff80000 {
++ compatible = "hisilicon,hi6220-sramctrl", "syscon";
++ reg = <0x0 0xfff80000 0x0 0x12000>;
++ };
++
+ ao_ctrl: ao_ctrl@f7800000 {
+ compatible = "hisilicon,hi6220-aoctrl", "syscon";
+ reg = <0x0 0xf7800000 0x0 0x2000>;
+@@ -194,6 +242,14 @@
+ #clock-cells = <1>;
+ };
+
++ stub_clock: stub_clock {
++ compatible = "hisilicon,hi6220-stub-clk";
++ hisilicon,hi6220-clk-sram = <&sram>;
++ #clock-cells = <1>;
++ mbox-names = "mbox-tx";
++ mboxes = <&mailbox 1 0 11>;
++ };
++
+ uart0: uart@f8015000 { /* console */
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xf8015000 0x0 0x1000>;
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0012-arm64-dts-hi6220-add-pinctrl-for-uarts-and-enable-th.patch b/debian/patches/hikey-4.7-rc1/0012-arm64-dts-hi6220-add-pinctrl-for-uarts-and-enable-th.patch
new file mode 100644
index 0000000..22d51d1
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0012-arm64-dts-hi6220-add-pinctrl-for-uarts-and-enable-th.patch
@@ -0,0 +1,82 @@
+From c2aad93200fa2dbbc6c48632e619494080d64796 Mon Sep 17 00:00:00 2001
+From: Guodong Xu <guodong.xu@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:48 +0800
+Subject: [PATCH 12/24] arm64: dts: hi6220: add pinctrl for uarts and enable
+ them
+
+Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3.
+
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 12 ++++++++++++
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++
+ 2 files changed, 21 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+index 3dbf51b..30c92bd 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -53,6 +53,18 @@
+ i2c1: i2c@f7101000 {
+ status = "ok";
+ };
++
++ uart1: uart@f7111000 {
++ status = "ok";
++ };
++
++ uart2: uart@f7112000 {
++ status = "ok";
++ };
++
++ uart3: uart@f7113000 {
++ status = "ok";
++ };
+ };
+ };
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index 3a665ef..e8bb81f 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -266,6 +266,8 @@
+ clocks = <&sys_ctrl HI6220_UART1_PCLK>,
+ <&sys_ctrl HI6220_UART1_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
+ status = "disabled";
+ };
+
+@@ -276,6 +278,8 @@
+ clocks = <&sys_ctrl HI6220_UART2_PCLK>,
+ <&sys_ctrl HI6220_UART2_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
+ status = "disabled";
+ };
+
+@@ -286,6 +290,9 @@
+ clocks = <&sys_ctrl HI6220_UART3_PCLK>,
+ <&sys_ctrl HI6220_UART3_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
++ status = "disabled";
+ };
+
+ uart4: uart@f7114000 {
+@@ -295,6 +302,8 @@
+ clocks = <&sys_ctrl HI6220_UART4_PCLK>,
+ <&sys_ctrl HI6220_UART4_PCLK>;
+ clock-names = "uartclk", "apb_pclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
+ status = "disabled";
+ };
+
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0013-arm64-dts-add-LED-nodes-for-hi6220-hikey.patch b/debian/patches/hikey-4.7-rc1/0013-arm64-dts-add-LED-nodes-for-hi6220-hikey.patch
new file mode 100644
index 0000000..c28275a
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0013-arm64-dts-add-LED-nodes-for-hi6220-hikey.patch
@@ -0,0 +1,70 @@
+From ad05f38ba98ab01aebf52cc1d788df8272e6daa8 Mon Sep 17 00:00:00 2001
+From: Guodong Xu <guodong.xu@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:49 +0800
+Subject: [PATCH 13/24] arm64: dts: add LED nodes for hi6220-hikey
+
+Add LED nodes for hi6220-hikey. There are total 6 LEDs on HiKey.
+Four general purposed, one for WiFi activity, and one for Bluetooth
+activity.
+
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 41 ++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+index 30c92bd..b7c41f8 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -66,6 +66,47 @@
+ status = "ok";
+ };
+ };
++
++ leds {
++ compatible = "gpio-leds";
++ user_led4 {
++ label = "user_led4";
++ gpios = <&gpio4 0 0>; /* <&gpio_user_led_1>; */
++ linux,default-trigger = "heartbeat";
++ };
++
++ user_led3 {
++ label = "user_led3";
++ gpios = <&gpio4 1 0>; /* <&gpio_user_led_2>; */
++ linux,default-trigger = "mmc0";
++ };
++
++ user_led2 {
++ label = "user_led2";
++ gpios = <&gpio4 2 0>; /* <&gpio_user_led_3>; */
++ linux,default-trigger = "mmc1";
++ };
++
++ user_led1 {
++ label = "user_led1";
++ gpios = <&gpio4 3 0>; /* <&gpio_user_led_4>; */
++ linux,default-trigger = "cpu0";
++ };
++
++ wlan_active_led {
++ label = "wifi_active";
++ gpios = <&gpio3 5 0>; /* <&gpio_wlan_active_led>; */
++ linux,default-trigger = "phy0tx";
++ default-state = "off";
++ };
++
++ bt_active_led {
++ label = "bt_active";
++ gpios = <&gpio4 7 0>; /* <&gpio_bt_active_led>; */
++ linux,default-trigger = "hci0rx";
++ default-state = "off";
++ };
++ };
+ };
+
+ &uart2 {
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0014-arm64-dts-hikey-Add-hi655x-pmic-dts-node.patch b/debian/patches/hikey-4.7-rc1/0014-arm64-dts-hikey-Add-hi655x-pmic-dts-node.patch
new file mode 100644
index 0000000..0ddc677
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0014-arm64-dts-hikey-Add-hi655x-pmic-dts-node.patch
@@ -0,0 +1,129 @@
+From a817137a6c3079c99954396afe94bb5a7cbfa251 Mon Sep 17 00:00:00 2001
+From: Chen Feng <puck.chen@hisilicon.com>
+Date: Wed, 13 Apr 2016 07:55:50 +0800
+Subject: [PATCH 14/24] arm64: dts: hikey: Add hi655x pmic dts node
+
+Add the mfd hi655x dts node and regulator support on hi6220 platform.
+
+Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
+Signed-off-by: Fei Wang <w.f@huawei.com>
+Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Acked-by: Lee Jones <lee.jones@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 87 +++++++++++++++++++++++++-
+ 1 file changed, 86 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+index b7c41f8..cc1148d 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -6,9 +6,9 @@
+ */
+
+ /dts-v1/;
+-
+ #include "hi6220.dtsi"
+ #include "hikey-pinctrl.dtsi"
++#include <dt-bindings/gpio/gpio.h>
+
+ / {
+ model = "HiKey Development Board";
+@@ -107,6 +107,91 @@
+ default-state = "off";
+ };
+ };
++
++ pmic: pmic@f8000000 {
++ compatible = "hisilicon,hi655x-pmic";
++ reg = <0x0 0xf8000000 0x0 0x1000>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++
++ regulators {
++ ldo2: LDO2 {
++ regulator-name = "LDO2_2V8";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <3200000>;
++ regulator-enable-ramp-delay = <120>;
++ };
++
++ ldo7: LDO7 {
++ regulator-name = "LDO7_SDIO";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-enable-ramp-delay = <120>;
++ };
++
++ ldo10: LDO10 {
++ regulator-name = "LDO10_2V85";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-enable-ramp-delay = <360>;
++ };
++
++ ldo13: LDO13 {
++ regulator-name = "LDO13_1V8";
++ regulator-min-microvolt = <1600000>;
++ regulator-max-microvolt = <1950000>;
++ regulator-enable-ramp-delay = <120>;
++ };
++
++ ldo14: LDO14 {
++ regulator-name = "LDO14_2V8";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <3200000>;
++ regulator-enable-ramp-delay = <120>;
++ };
++
++ ldo15: LDO15 {
++ regulator-name = "LDO15_1V8";
++ regulator-min-microvolt = <1600000>;
++ regulator-max-microvolt = <1950000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-enable-ramp-delay = <120>;
++ };
++
++ ldo17: LDO17 {
++ regulator-name = "LDO17_2V5";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <3200000>;
++ regulator-enable-ramp-delay = <120>;
++ };
++
++ ldo19: LDO19 {
++ regulator-name = "LDO19_3V0";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-enable-ramp-delay = <360>;
++ };
++
++ ldo21: LDO21 {
++ regulator-name = "LDO21_1V8";
++ regulator-min-microvolt = <1650000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-always-on;
++ regulator-enable-ramp-delay = <120>;
++ };
++
++ ldo22: LDO22 {
++ regulator-name = "LDO22_1V2";
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-enable-ramp-delay = <120>;
++ };
++ };
++ };
+ };
+
+ &uart2 {
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0015-arm64-dts-add-dwmmc-nodes-for-hi6220.patch b/debian/patches/hikey-4.7-rc1/0015-arm64-dts-add-dwmmc-nodes-for-hi6220.patch
new file mode 100644
index 0000000..3886566
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0015-arm64-dts-add-dwmmc-nodes-for-hi6220.patch
@@ -0,0 +1,79 @@
+From d6b259d4faa1670f372969141323c6fe4b3b7db9 Mon Sep 17 00:00:00 2001
+From: Xinwei Kong <kong.kongxinwei@hisilicon.com>
+Date: Wed, 13 Apr 2016 07:55:51 +0800
+Subject: [PATCH 15/24] arm64: dts: add dwmmc nodes for hi6220
+
+Add all three dwmmc nodes description for hi6220
+
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 52 +++++++++++++++++++++++++++++++
+ 1 file changed, 52 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index e8bb81f..7b7bbf6 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -720,5 +720,57 @@
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <3>;
+ };
++
++ dwmmc_0: dwmmc0@f723d000 {
++ compatible = "hisilicon,hi6220-dw-mshc";
++ num-slots = <0x1>;
++ cap-mmc-highspeed;
++ non-removable;
++ reg = <0x0 0xf723d000 0x0 0x1000>;
++ interrupts = <0x0 0x48 0x4>;
++ clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
++ clock-names = "ciu", "biu";
++ bus-width = <0x8>;
++ vmmc-supply = <&ldo19>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
++ &emmc_cfg_func &emmc_rst_cfg_func>;
++ };
++
++ dwmmc_1: dwmmc1@f723e000 {
++ compatible = "hisilicon,hi6220-dw-mshc";
++ num-slots = <0x1>;
++ card-detect-delay = <200>;
++ hisilicon,peripheral-syscon = <&ao_ctrl>;
++ cap-sd-highspeed;
++ reg = <0x0 0xf723e000 0x0 0x1000>;
++ interrupts = <0x0 0x49 0x4>;
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
++ clock-names = "ciu", "biu";
++ vqmmc-supply = <&ldo7>;
++ vmmc-supply = <&ldo10>;
++ bus-width = <0x4>;
++ disable-wp;
++ cd-gpios = <&gpio1 0 1>;
++ pinctrl-names = "default", "idle";
++ pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
++ pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
++ };
++
++ dwmmc_2: dwmmc2@f723f000 {
++ compatible = "hisilicon,hi6220-dw-mshc";
++ num-slots = <0x1>;
++ reg = <0x0 0xf723f000 0x0 0x1000>;
++ interrupts = <0x0 0x4a 0x4>;
++ clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
++ clock-names = "ciu", "biu";
++ bus-width = <0x4>;
++ broken-cd;
++ pinctrl-names = "default", "idle";
++ pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
++ pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0016-arm64-dts-add-wifi-nodes-support-for-hi6220-hikey.patch b/debian/patches/hikey-4.7-rc1/0016-arm64-dts-add-wifi-nodes-support-for-hi6220-hikey.patch
new file mode 100644
index 0000000..c641c32
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0016-arm64-dts-add-wifi-nodes-support-for-hi6220-hikey.patch
@@ -0,0 +1,53 @@
+From 841478d4ae2cb7205fc7940e7140ef0efb3fabf7 Mon Sep 17 00:00:00 2001
+From: Guodong Xu <guodong.xu@linaro.org>
+Date: Wed, 13 Apr 2016 07:55:52 +0800
+Subject: [PATCH 16/24] arm64: dts: add wifi nodes support for hi6220-hikey
+
+Add wifi nodes support for hi6220-hikey
+
+Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 29 ++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+Index: linux-4.6/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+===================================================================
+--- linux-4.6.orig/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
++++ linux-4.6/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+@@ -53,6 +53,35 @@
+ i2c1: i2c@f7101000 {
+ status = "ok";
+ };
++
++ dwmmc_2: dwmmc2@f723f000 {
++ ti,non-removable;
++ non-removable;
++ /* WL_EN */
++ vmmc-supply = <&wlan_en_reg>;
++
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ wlcore: wlcore@2 {
++ compatible = "ti,wl1835";
++ reg = <2>; /* sdio func num */
++ /* WL_IRQ, WL_HOST_WAKE_GPIO1_3 */
++ interrupt-parent = <&gpio1>;
++ interrupts = <3 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
++ wlan_en_reg: regulator@1 {
++ compatible = "regulator-fixed";
++ regulator-name = "wlan-en-regulator";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ /* WLAN_EN GPIO */
++ gpio = <&gpio0 5 0>;
++ /* WLAN card specific delay */
++ startup-delay-us = <70000>;
++ enable-active-high;
++ };
+ };
+
+ leds {
diff --git a/debian/patches/hikey-4.7-rc1/0017-arm64-dts-register-Hi6220-s-thermal-sensor.patch b/debian/patches/hikey-4.7-rc1/0017-arm64-dts-register-Hi6220-s-thermal-sensor.patch
new file mode 100644
index 0000000..60595ce
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0017-arm64-dts-register-Hi6220-s-thermal-sensor.patch
@@ -0,0 +1,35 @@
+From 2158ab084b721da7b0e4963ac91fd96775b80916 Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Tue, 29 Mar 2016 19:27:14 +0800
+Subject: [PATCH 17/24] arm64: dts: register Hi6220's thermal sensor
+
+Bind thermal sensor driver for Hi6220.
+
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index 7b7bbf6..fc61a16 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -772,5 +772,14 @@
+ pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
+ pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
+ };
++
++ tsensor: tsensor@0,f7030700 {
++ compatible = "hisilicon,tsensor";
++ reg = <0x0 0xf7030700 0x0 0x1000>;
++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&sys_ctrl 22>;
++ clock-names = "thermal_clk";
++ #thermal-sensor-cells = <1>;
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0018-arm64-dts-register-Hi6220-s-thermal-zone-for-power-a.patch b/debian/patches/hikey-4.7-rc1/0018-arm64-dts-register-Hi6220-s-thermal-zone-for-power-a.patch
new file mode 100644
index 0000000..d9ba9c3
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0018-arm64-dts-register-Hi6220-s-thermal-zone-for-power-a.patch
@@ -0,0 +1,81 @@
+From cd0b69ec0eb5e489954d7125b934457ac7acf6f7 Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Tue, 29 Mar 2016 19:27:15 +0800
+Subject: [PATCH 18/24] arm64: dts: register Hi6220's thermal zone for power
+ allocator
+
+With profiling Hi6220's power modeling so get dynamic coefficient and
+sustainable power. So pass these parameters from DT.
+
+Now enable power allocator with only one actor for CPU part, so directly
+use cluster0's thermal sensor for monitoring temperature.
+
+Reviewed-by: Javi Merino <javi.merino@arm.com>
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 35 +++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index fc61a16..0c8df8a 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -7,6 +7,7 @@
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/hi6220-clock.h>
+ #include <dt-bindings/pinctrl/hisi.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ compatible = "hisilicon,hi6220";
+@@ -88,6 +89,7 @@
+ cooling-max-level = <0>;
+ #cooling-cells = <2>; /* min followed by max */
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
++ dynamic-power-coefficient = <311>;
+ };
+
+ cpu1: cpu@1 {
+@@ -781,5 +783,38 @@
+ clock-names = "thermal_clk";
+ #thermal-sensor-cells = <1>;
+ };
++
++ thermal-zones {
++
++ cls0: cls0 {
++ polling-delay = <1000>;
++ polling-delay-passive = <100>;
++ sustainable-power = <3326>;
++
++ /* sensor ID */
++ thermal-sensors = <&tsensor 2>;
++
++ trips {
++ threshold: trip-point@0 {
++ temperature = <65000>;
++ hysteresis = <0>;
++ type = "passive";
++ };
++
++ target: trip-point@1 {
++ temperature = <75000>;
++ hysteresis = <0>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&target>;
++ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ };
++ };
++ };
++ };
+ };
+ };
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0019-arm64-dts-Add-L2-cache-topology-to-Hi6220.patch b/debian/patches/hikey-4.7-rc1/0019-arm64-dts-Add-L2-cache-topology-to-Hi6220.patch
new file mode 100644
index 0000000..0d71363
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0019-arm64-dts-Add-L2-cache-topology-to-Hi6220.patch
@@ -0,0 +1,96 @@
+From 6485160396fcec2fa8a0acfa7c8c090f020db694 Mon Sep 17 00:00:00 2001
+From: Leo Yan <leo.yan@linaro.org>
+Date: Fri, 26 Feb 2016 13:28:34 +0800
+Subject: [PATCH 19/24] arm64: dts: Add L2 cache topology to Hi6220
+
+This patch adds the L2 cache topology on Hi6220. Hi6220 has two
+clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).
+
+Signed-off-by: Leo Yan <leo.yan@linaro.org>
+Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
+---
+ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+index 0c8df8a..189d215 100644
+--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
++++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+@@ -83,6 +83,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER0_L2>;
+ clocks = <&stub_clock 0>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cooling-min-level = <4>;
+@@ -97,6 +98,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER0_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+@@ -106,6 +108,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER0_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+@@ -115,6 +118,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER0_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+@@ -124,6 +128,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+@@ -133,6 +138,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+@@ -142,6 +148,7 @@
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
+@@ -151,9 +158,18 @@
+ device_type = "cpu";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
++ next-level-cache = <&CLUSTER1_L2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+ };
++
++ CLUSTER0_L2: l2-cache0 {
++ compatible = "cache";
++ };
++
++ CLUSTER1_L2: l2-cache1 {
++ compatible = "cache";
++ };
+ };
+
+ cpu_opp_table: cpu_opp_table {
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0020-mfd-max77693-Allow-building-as-a-module.patch b/debian/patches/hikey-4.7-rc1/0020-mfd-max77693-Allow-building-as-a-module.patch
new file mode 100644
index 0000000..9afc2ca
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0020-mfd-max77693-Allow-building-as-a-module.patch
@@ -0,0 +1,68 @@
+From 073d4aca342029fc62fefa500bb11a556c5f7223 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <k.kozlowski@samsung.com>
+Date: Mon, 4 Apr 2016 16:54:18 +0900
+Subject: [PATCH 20/24] mfd: max77693: Allow building as a module
+
+The consumer of max77693 regulators on Trats2 board (samsung-usb2-phy
+driver) supports deferred probing so the max77693 main MFD driver can be
+built now as a module. This gives more flexibility and removes manual
+ordering of init calls.
+
+Suggested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+---
+ drivers/mfd/Kconfig | 4 ++--
+ drivers/mfd/max77693.c | 14 ++------------
+ 2 files changed, 4 insertions(+), 14 deletions(-)
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index eea61e3..aa1e7c3 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -543,8 +543,8 @@ config MFD_MAX77686
+ of the device.
+
+ config MFD_MAX77693
+- bool "Maxim Semiconductor MAX77693 PMIC Support"
+- depends on I2C=y
++ tristate "Maxim Semiconductor MAX77693 PMIC Support"
++ depends on I2C
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+diff --git a/drivers/mfd/max77693.c b/drivers/mfd/max77693.c
+index b83b7a7..78e501f 100644
+--- a/drivers/mfd/max77693.c
++++ b/drivers/mfd/max77693.c
+@@ -368,6 +368,7 @@ static const struct of_device_id max77693_dt_match[] = {
+ { .compatible = "maxim,max77693" },
+ {},
+ };
++MODULE_DEVICE_TABLE(of, max77693_dt_match);
+ #endif
+
+ static struct i2c_driver max77693_i2c_driver = {
+@@ -381,18 +382,7 @@ static struct i2c_driver max77693_i2c_driver = {
+ .id_table = max77693_i2c_id,
+ };
+
+-static int __init max77693_i2c_init(void)
+-{
+- return i2c_add_driver(&max77693_i2c_driver);
+-}
+-/* init early so consumer devices can complete system boot */
+-subsys_initcall(max77693_i2c_init);
+-
+-static void __exit max77693_i2c_exit(void)
+-{
+- i2c_del_driver(&max77693_i2c_driver);
+-}
+-module_exit(max77693_i2c_exit);
++module_i2c_driver(max77693_i2c_driver);
+
+ MODULE_DESCRIPTION("MAXIM 77693 multi-function core driver");
+ MODULE_AUTHOR("SangYoung, Son <hello.son@samsung.com>");
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0021-mfd-cros_ec-Allow-building-for-ARM64.patch b/debian/patches/hikey-4.7-rc1/0021-mfd-cros_ec-Allow-building-for-ARM64.patch
new file mode 100644
index 0000000..659904d
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0021-mfd-cros_ec-Allow-building-for-ARM64.patch
@@ -0,0 +1,31 @@
+From ba5776ab6f09800dd9ba8442185139661e065529 Mon Sep 17 00:00:00 2001
+From: Brian Norris <briannorris@chromium.org>
+Date: Mon, 11 Apr 2016 10:27:32 -0700
+Subject: [PATCH 21/24] mfd: cros_ec: Allow building for ARM64
+
+There are platforms using the ChromeOS embeded controller on ARM64 now,
+so let's allow using this driver (without having to use COMPILE_TEST).
+
+Signed-off-by: Brian Norris <briannorris@chromium.org>
+Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+---
+ drivers/mfd/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index aa1e7c3..cf7cbba 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -134,7 +134,7 @@ config MFD_CROS_EC
+ select MFD_CORE
+ select CHROME_PLATFORMS
+ select CROS_EC_PROTO
+- depends on X86 || ARM || COMPILE_TEST
++ depends on X86 || ARM || ARM64 || COMPILE_TEST
+ help
+ If you say Y here you get support for the ChromeOS Embedded
+ Controller (EC) providing keyboard, battery and power services.
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0022-mfd-max77620-Add-core-driver-for-MAX77620-MAX20024.patch b/debian/patches/hikey-4.7-rc1/0022-mfd-max77620-Add-core-driver-for-MAX77620-MAX20024.patch
new file mode 100644
index 0000000..d7ee854
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0022-mfd-max77620-Add-core-driver-for-MAX77620-MAX20024.patch
@@ -0,0 +1,1015 @@
+From 327156c593600e0f08575621c2a56f311d482e7a Mon Sep 17 00:00:00 2001
+From: Laxman Dewangan <ldewangan@nvidia.com>
+Date: Thu, 28 Apr 2016 15:28:56 +0530
+Subject: [PATCH 22/24] mfd: max77620: Add core driver for MAX77620/MAX20024
+
+MAX77620/MAX20024 are Power Management IC from the MAXIM.
+It supports RTC, multiple GPIOs, multiple DCDC and LDOs,
+watchdog, clock etc.
+
+Add MFD drier to provides common support for accessing the
+device; additional drivers is developed on respected subsystem
+in order to use the functionality of the device.
+
+Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
+Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
+Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+---
+ drivers/mfd/Kconfig | 15 ++
+ drivers/mfd/Makefile | 1 +
+ drivers/mfd/max77620.c | 590 +++++++++++++++++++++++++++++++++++++++++++
+ include/linux/mfd/max77620.h | 346 +++++++++++++++++++++++++
+ 4 files changed, 952 insertions(+)
+ create mode 100644 drivers/mfd/max77620.c
+ create mode 100644 include/linux/mfd/max77620.h
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index cf7cbba..16d0bef 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -527,6 +527,21 @@ config MFD_MAX14577
+ additional drivers must be enabled in order to use the functionality
+ of the device.
+
++config MFD_MAX77620
++ bool "Maxim Semiconductor MAX77620 and MAX20024 PMIC Support"
++ depends on I2C=y
++ depends on OF
++ select MFD_CORE
++ select REGMAP_I2C
++ select REGMAP_IRQ
++ select IRQ_DOMAIN
++ help
++ Say yes here to add support for Maxim Semiconductor MAX77620 and
++ MAX20024 which are Power Management IC with General purpose pins,
++ RTC, regulators, clock generator, watchdog etc. This driver
++ provides common support for accessing the device; additional drivers
++ must be enabled in order to use the functionality of the device.
++
+ config MFD_MAX77686
+ tristate "Maxim Semiconductor MAX77686/802 PMIC Support"
+ depends on I2C
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index 5eaa6465d..921a08d 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -128,6 +128,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
+ obj-$(CONFIG_MFD_DA9150) += da9150-core.o
+
+ obj-$(CONFIG_MFD_MAX14577) += max14577.o
++obj-$(CONFIG_MFD_MAX77620) += max77620.o
+ obj-$(CONFIG_MFD_MAX77686) += max77686.o
+ obj-$(CONFIG_MFD_MAX77693) += max77693.o
+ obj-$(CONFIG_MFD_MAX77843) += max77843.o
+diff --git a/drivers/mfd/max77620.c b/drivers/mfd/max77620.c
+new file mode 100644
+index 0000000..199d261
+--- /dev/null
++++ b/drivers/mfd/max77620.c
+@@ -0,0 +1,590 @@
++/*
++ * Maxim MAX77620 MFD Driver
++ *
++ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
++ *
++ * Author:
++ * Laxman Dewangan <ldewangan@nvidia.com>
++ * Chaitanya Bandi <bandik@nvidia.com>
++ * Mallikarjun Kasoju <mkasoju@nvidia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/****************** Teminology used in driver ********************
++ * Here are some terminology used from datasheet for quick reference:
++ * Flexible Power Sequence (FPS):
++ * The Flexible Power Sequencer (FPS) allows each regulator to power up under
++ * hardware or software control. Additionally, each regulator can power on
++ * independently or among a group of other regulators with an adjustable
++ * power-up and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can
++ * be programmed to be part of a sequence allowing external regulators to be
++ * sequenced along with internal regulators. 32KHz clock can be programmed to
++ * be part of a sequence.
++ * There is 3 FPS confguration registers and all resources are configured to
++ * any of these FPS or no FPS.
++ */
++
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/max77620.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++
++static struct resource gpio_resources[] = {
++ DEFINE_RES_IRQ(MAX77620_IRQ_TOP_GPIO),
++};
++
++static struct resource power_resources[] = {
++ DEFINE_RES_IRQ(MAX77620_IRQ_LBT_MBATLOW),
++};
++
++static struct resource rtc_resources[] = {
++ DEFINE_RES_IRQ(MAX77620_IRQ_TOP_RTC),
++};
++
++static struct resource thermal_resources[] = {
++ DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM1),
++ DEFINE_RES_IRQ(MAX77620_IRQ_LBT_TJALRM2),
++};
++
++static const struct regmap_irq max77620_top_irqs[] = {
++ REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GLBL, 0, MAX77620_IRQ_TOP_GLBL_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_TOP_SD, 0, MAX77620_IRQ_TOP_SD_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_TOP_LDO, 0, MAX77620_IRQ_TOP_LDO_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_TOP_GPIO, 0, MAX77620_IRQ_TOP_GPIO_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_TOP_RTC, 0, MAX77620_IRQ_TOP_RTC_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_TOP_32K, 0, MAX77620_IRQ_TOP_32K_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_TOP_ONOFF, 0, MAX77620_IRQ_TOP_ONOFF_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_LBT_MBATLOW, 1, MAX77620_IRQ_LBM_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM1, 1, MAX77620_IRQ_TJALRM1_MASK),
++ REGMAP_IRQ_REG(MAX77620_IRQ_LBT_TJALRM2, 1, MAX77620_IRQ_TJALRM2_MASK),
++};
++
++static const struct mfd_cell max77620_children[] = {
++ { .name = "max77620-pinctrl", },
++ { .name = "max77620-clock", },
++ { .name = "max77620-pmic", },
++ { .name = "max77620-watchdog", },
++ {
++ .name = "max77620-gpio",
++ .resources = gpio_resources,
++ .num_resources = ARRAY_SIZE(gpio_resources),
++ }, {
++ .name = "max77620-rtc",
++ .resources = rtc_resources,
++ .num_resources = ARRAY_SIZE(rtc_resources),
++ }, {
++ .name = "max77620-power",
++ .resources = power_resources,
++ .num_resources = ARRAY_SIZE(power_resources),
++ }, {
++ .name = "max77620-thermal",
++ .resources = thermal_resources,
++ .num_resources = ARRAY_SIZE(thermal_resources),
++ },
++};
++
++static const struct mfd_cell max20024_children[] = {
++ { .name = "max20024-pinctrl", },
++ { .name = "max77620-clock", },
++ { .name = "max20024-pmic", },
++ { .name = "max77620-watchdog", },
++ {
++ .name = "max77620-gpio",
++ .resources = gpio_resources,
++ .num_resources = ARRAY_SIZE(gpio_resources),
++ }, {
++ .name = "max77620-rtc",
++ .resources = rtc_resources,
++ .num_resources = ARRAY_SIZE(rtc_resources),
++ }, {
++ .name = "max20024-power",
++ .resources = power_resources,
++ .num_resources = ARRAY_SIZE(power_resources),
++ },
++};
++
++static struct regmap_irq_chip max77620_top_irq_chip = {
++ .name = "max77620-top",
++ .irqs = max77620_top_irqs,
++ .num_irqs = ARRAY_SIZE(max77620_top_irqs),
++ .num_regs = 2,
++ .status_base = MAX77620_REG_IRQTOP,
++ .mask_base = MAX77620_REG_IRQTOPM,
++};
++
++static const struct regmap_range max77620_readable_ranges[] = {
++ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
++};
++
++static const struct regmap_access_table max77620_readable_table = {
++ .yes_ranges = max77620_readable_ranges,
++ .n_yes_ranges = ARRAY_SIZE(max77620_readable_ranges),
++};
++
++static const struct regmap_range max20024_readable_ranges[] = {
++ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
++ regmap_reg_range(MAX20024_REG_MAX_ADD, MAX20024_REG_MAX_ADD),
++};
++
++static const struct regmap_access_table max20024_readable_table = {
++ .yes_ranges = max20024_readable_ranges,
++ .n_yes_ranges = ARRAY_SIZE(max20024_readable_ranges),
++};
++
++static const struct regmap_range max77620_writable_ranges[] = {
++ regmap_reg_range(MAX77620_REG_CNFGGLBL1, MAX77620_REG_DVSSD4),
++};
++
++static const struct regmap_access_table max77620_writable_table = {
++ .yes_ranges = max77620_writable_ranges,
++ .n_yes_ranges = ARRAY_SIZE(max77620_writable_ranges),
++};
++
++static const struct regmap_range max77620_cacheable_ranges[] = {
++ regmap_reg_range(MAX77620_REG_SD0_CFG, MAX77620_REG_LDO_CFG3),
++ regmap_reg_range(MAX77620_REG_FPS_CFG0, MAX77620_REG_FPS_SD3),
++};
++
++static const struct regmap_access_table max77620_volatile_table = {
++ .no_ranges = max77620_cacheable_ranges,
++ .n_no_ranges = ARRAY_SIZE(max77620_cacheable_ranges),
++};
++
++static const struct regmap_config max77620_regmap_config = {
++ .name = "power-slave",
++ .reg_bits = 8,
++ .val_bits = 8,
++ .max_register = MAX77620_REG_DVSSD4 + 1,
++ .cache_type = REGCACHE_RBTREE,
++ .rd_table = &max77620_readable_table,
++ .wr_table = &max77620_writable_table,
++ .volatile_table = &max77620_volatile_table,
++};
++
++static const struct regmap_config max20024_regmap_config = {
++ .name = "power-slave",
++ .reg_bits = 8,
++ .val_bits = 8,
++ .max_register = MAX20024_REG_MAX_ADD + 1,
++ .cache_type = REGCACHE_RBTREE,
++ .rd_table = &max20024_readable_table,
++ .wr_table = &max77620_writable_table,
++ .volatile_table = &max77620_volatile_table,
++};
++
++/* max77620_get_fps_period_reg_value: Get FPS bit field value from
++ * requested periods.
++ * MAX77620 supports the FPS period of 40, 80, 160, 320, 540, 1280, 2560
++ * and 5120 microseconds. MAX20024 supports the FPS period of 20, 40, 80,
++ * 160, 320, 540, 1280 and 2560 microseconds.
++ * The FPS register has 3 bits field to set the FPS period as
++ * bits max77620 max20024
++ * 000 40 20
++ * 001 80 40
++ * :::
++*/
++static int max77620_get_fps_period_reg_value(struct max77620_chip *chip,
++ int tperiod)
++{
++ int fps_min_period;
++ int i;
++
++ switch (chip->chip_id) {
++ case MAX20024:
++ fps_min_period = MAX20024_FPS_PERIOD_MIN_US;
++ break;
++ case MAX77620:
++ fps_min_period = MAX77620_FPS_PERIOD_MIN_US;
++ default:
++ return -EINVAL;
++ }
++
++ for (i = 0; i < 7; i++) {
++ if (fps_min_period >= tperiod)
++ return i;
++ fps_min_period *= 2;
++ }
++
++ return i;
++}
++
++/* max77620_config_fps: Configure FPS configuration registers
++ * based on platform specific information.
++ */
++static int max77620_config_fps(struct max77620_chip *chip,
++ struct device_node *fps_np)
++{
++ struct device *dev = chip->dev;
++ unsigned int mask = 0, config = 0;
++ u32 fps_max_period;
++ u32 param_val;
++ int tperiod, fps_id;
++ int ret;
++ char fps_name[10];
++
++ switch (chip->chip_id) {
++ case MAX20024:
++ fps_max_period = MAX20024_FPS_PERIOD_MAX_US;
++ break;
++ case MAX77620:
++ fps_max_period = MAX77620_FPS_PERIOD_MAX_US;
++ default:
++ return -EINVAL;
++ }
++
++ for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
++ sprintf(fps_name, "fps%d", fps_id);
++ if (!strcmp(fps_np->name, fps_name))
++ break;
++ }
++
++ if (fps_id == MAX77620_FPS_COUNT) {
++ dev_err(dev, "FPS node name %s is not valid\n", fps_np->name);
++ return -EINVAL;
++ }
++
++ ret = of_property_read_u32(fps_np, "maxim,shutdown-fps-time-period-us",
++ ¶m_val);
++ if (!ret) {
++ mask |= MAX77620_FPS_TIME_PERIOD_MASK;
++ chip->shutdown_fps_period[fps_id] = min(param_val,
++ fps_max_period);
++ tperiod = max77620_get_fps_period_reg_value(chip,
++ chip->shutdown_fps_period[fps_id]);
++ config |= tperiod << MAX77620_FPS_TIME_PERIOD_SHIFT;
++ }
++
++ ret = of_property_read_u32(fps_np, "maxim,suspend-fps-time-period-us",
++ ¶m_val);
++ if (!ret)
++ chip->suspend_fps_period[fps_id] = min(param_val,
++ fps_max_period);
++
++ ret = of_property_read_u32(fps_np, "maxim,fps-event-source",
++ ¶m_val);
++ if (!ret) {
++ if (param_val > 2) {
++ dev_err(dev, "FPS%d event-source invalid\n", fps_id);
++ return -EINVAL;
++ }
++ mask |= MAX77620_FPS_EN_SRC_MASK;
++ config |= param_val << MAX77620_FPS_EN_SRC_SHIFT;
++ if (param_val == 2) {
++ mask |= MAX77620_FPS_ENFPS_SW_MASK;
++ config |= MAX77620_FPS_ENFPS_SW;
++ }
++ }
++
++ if (!chip->sleep_enable && !chip->enable_global_lpm) {
++ ret = of_property_read_u32(fps_np,
++ "maxim,device-state-on-disabled-event",
++ ¶m_val);
++ if (!ret) {
++ if (param_val == 0)
++ chip->sleep_enable = true;
++ else if (param_val == 1)
++ chip->enable_global_lpm = true;
++ }
++ }
++
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
++ mask, config);
++ if (ret < 0) {
++ dev_err(dev, "Failed to update FPS CFG: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int max77620_initialise_fps(struct max77620_chip *chip)
++{
++ struct device *dev = chip->dev;
++ struct device_node *fps_np, *fps_child;
++ u8 config;
++ int fps_id;
++ int ret;
++
++ for (fps_id = 0; fps_id < MAX77620_FPS_COUNT; fps_id++) {
++ chip->shutdown_fps_period[fps_id] = -1;
++ chip->suspend_fps_period[fps_id] = -1;
++ }
++
++ fps_np = of_get_child_by_name(dev->of_node, "fps");
++ if (!fps_np)
++ goto skip_fps;
++
++ for_each_child_of_node(fps_np, fps_child) {
++ ret = max77620_config_fps(chip, fps_child);
++ if (ret < 0)
++ return ret;
++ }
++
++ config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
++ MAX77620_ONOFFCNFG2_SLP_LPM_MSK, config);
++ if (ret < 0) {
++ dev_err(dev, "Failed to update SLP_LPM: %d\n", ret);
++ return ret;
++ }
++
++skip_fps:
++ /* Enable wake on EN0 pin */
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
++ MAX77620_ONOFFCNFG2_WK_EN0,
++ MAX77620_ONOFFCNFG2_WK_EN0);
++ if (ret < 0) {
++ dev_err(dev, "Failed to update WK_EN0: %d\n", ret);
++ return ret;
++ }
++
++ /* For MAX20024, SLPEN will be POR reset if CLRSE is b11 */
++ if ((chip->chip_id == MAX20024) && chip->sleep_enable) {
++ config = MAX77620_ONOFFCNFG1_SLPEN | MAX20024_ONOFFCNFG1_CLRSE;
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
++ config, config);
++ if (ret < 0) {
++ dev_err(dev, "Failed to update SLPEN: %d\n", ret);
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static int max77620_read_es_version(struct max77620_chip *chip)
++{
++ unsigned int val;
++ u8 cid_val[6];
++ int i;
++ int ret;
++
++ for (i = MAX77620_REG_CID0; i <= MAX77620_REG_CID5; i++) {
++ ret = regmap_read(chip->rmap, i, &val);
++ if (ret < 0) {
++ dev_err(chip->dev, "Failed to read CID: %d\n", ret);
++ return ret;
++ }
++ dev_dbg(chip->dev, "CID%d: 0x%02x\n",
++ i - MAX77620_REG_CID0, val);
++ cid_val[i - MAX77620_REG_CID0] = val;
++ }
++
++ /* CID4 is OTP Version and CID5 is ES version */
++ dev_info(chip->dev, "PMIC Version OTP:0x%02X and ES:0x%X\n",
++ cid_val[4], MAX77620_CID5_DIDM(cid_val[5]));
++
++ return ret;
++}
++
++static int max77620_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ const struct regmap_config *rmap_config;
++ struct max77620_chip *chip;
++ const struct mfd_cell *mfd_cells;
++ int n_mfd_cells;
++ int ret;
++
++ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
++ if (!chip)
++ return -ENOMEM;
++
++ i2c_set_clientdata(client, chip);
++ chip->dev = &client->dev;
++ chip->irq_base = -1;
++ chip->chip_irq = client->irq;
++ chip->chip_id = (enum max77620_chip_id)id->driver_data;
++
++ switch (chip->chip_id) {
++ case MAX77620:
++ mfd_cells = max77620_children;
++ n_mfd_cells = ARRAY_SIZE(max77620_children);
++ rmap_config = &max77620_regmap_config;
++ break;
++ case MAX20024:
++ mfd_cells = max20024_children;
++ n_mfd_cells = ARRAY_SIZE(max20024_children);
++ rmap_config = &max20024_regmap_config;
++ break;
++ default:
++ dev_err(chip->dev, "ChipID is invalid %d\n", chip->chip_id);
++ return -EINVAL;
++ }
++
++ chip->rmap = devm_regmap_init_i2c(client, rmap_config);
++ if (IS_ERR(chip->rmap)) {
++ ret = PTR_ERR(chip->rmap);
++ dev_err(chip->dev, "Failed to intialise regmap: %d\n", ret);
++ return ret;
++ }
++
++ ret = max77620_read_es_version(chip);
++ if (ret < 0)
++ return ret;
++
++ ret = devm_regmap_add_irq_chip(chip->dev, chip->rmap, client->irq,
++ IRQF_ONESHOT | IRQF_SHARED,
++ chip->irq_base, &max77620_top_irq_chip,
++ &chip->top_irq_data);
++ if (ret < 0) {
++ dev_err(chip->dev, "Failed to add regmap irq: %d\n", ret);
++ return ret;
++ }
++
++ ret = max77620_initialise_fps(chip);
++ if (ret < 0)
++ return ret;
++
++ ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
++ mfd_cells, n_mfd_cells, NULL, 0,
++ regmap_irq_get_domain(chip->top_irq_data));
++ if (ret < 0) {
++ dev_err(chip->dev, "Failed to add MFD children: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int max77620_set_fps_period(struct max77620_chip *chip,
++ int fps_id, int time_period)
++{
++ int period = max77620_get_fps_period_reg_value(chip, time_period);
++ int ret;
++
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_FPS_CFG0 + fps_id,
++ MAX77620_FPS_TIME_PERIOD_MASK,
++ period << MAX77620_FPS_TIME_PERIOD_SHIFT);
++ if (ret < 0) {
++ dev_err(chip->dev, "Failed to update FPS period: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int max77620_i2c_suspend(struct device *dev)
++{
++ struct max77620_chip *chip = dev_get_drvdata(dev);
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned int config;
++ int fps;
++ int ret;
++
++ for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
++ if (chip->suspend_fps_period[fps] < 0)
++ continue;
++
++ ret = max77620_set_fps_period(chip, fps,
++ chip->suspend_fps_period[fps]);
++ if (ret < 0)
++ return ret;
++ }
++
++ /*
++ * For MAX20024: No need to configure SLPEN on suspend as
++ * it will be configured on Init.
++ */
++ if (chip->chip_id == MAX20024)
++ goto out;
++
++ config = (chip->sleep_enable) ? MAX77620_ONOFFCNFG1_SLPEN : 0;
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG1,
++ MAX77620_ONOFFCNFG1_SLPEN,
++ config);
++ if (ret < 0) {
++ dev_err(dev, "Failed to configure sleep in suspend: %d\n", ret);
++ return ret;
++ }
++
++ /* Disable WK_EN0 */
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
++ MAX77620_ONOFFCNFG2_WK_EN0, 0);
++ if (ret < 0) {
++ dev_err(dev, "Failed to configure WK_EN in suspend: %d\n", ret);
++ return ret;
++ }
++
++out:
++ disable_irq(client->irq);
++
++ return 0;
++}
++
++static int max77620_i2c_resume(struct device *dev)
++{
++ struct max77620_chip *chip = dev_get_drvdata(dev);
++ struct i2c_client *client = to_i2c_client(dev);
++ int ret;
++ int fps;
++
++ for (fps = 0; fps < MAX77620_FPS_COUNT; fps++) {
++ if (chip->shutdown_fps_period[fps] < 0)
++ continue;
++
++ ret = max77620_set_fps_period(chip, fps,
++ chip->shutdown_fps_period[fps]);
++ if (ret < 0)
++ return ret;
++ }
++
++ /*
++ * For MAX20024: No need to configure WKEN0 on resume as
++ * it is configured on Init.
++ */
++ if (chip->chip_id == MAX20024)
++ goto out;
++
++ /* Enable WK_EN0 */
++ ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,
++ MAX77620_ONOFFCNFG2_WK_EN0,
++ MAX77620_ONOFFCNFG2_WK_EN0);
++ if (ret < 0) {
++ dev_err(dev, "Failed to configure WK_EN0 n resume: %d\n", ret);
++ return ret;
++ }
++
++out:
++ enable_irq(client->irq);
++
++ return 0;
++}
++#endif
++
++static const struct i2c_device_id max77620_id[] = {
++ {"max77620", MAX77620},
++ {"max20024", MAX20024},
++ {},
++};
++MODULE_DEVICE_TABLE(i2c, max77620_id);
++
++static const struct dev_pm_ops max77620_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(max77620_i2c_suspend, max77620_i2c_resume)
++};
++
++static struct i2c_driver max77620_driver = {
++ .driver = {
++ .name = "max77620",
++ .pm = &max77620_pm_ops,
++ },
++ .probe = max77620_probe,
++ .id_table = max77620_id,
++};
++
++module_i2c_driver(max77620_driver);
++
++MODULE_DESCRIPTION("MAX77620/MAX20024 Multi Function Device Core Driver");
++MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
++MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
++MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
++MODULE_LICENSE("GPL v2");
+diff --git a/include/linux/mfd/max77620.h b/include/linux/mfd/max77620.h
+new file mode 100644
+index 0000000..3ca0af07
+--- /dev/null
++++ b/include/linux/mfd/max77620.h
+@@ -0,0 +1,346 @@
++/*
++ * Defining registers address and its bit definitions of MAX77620 and MAX20024
++ *
++ * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ */
++
++#ifndef _MFD_MAX77620_H_
++#define _MFD_MAX77620_H_
++
++#include <linux/types.h>
++
++/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
++#define MAX77620_REG_CNFGGLBL1 0x00
++#define MAX77620_REG_CNFGGLBL2 0x01
++#define MAX77620_REG_CNFGGLBL3 0x02
++#define MAX77620_REG_CNFG1_32K 0x03
++#define MAX77620_REG_CNFGBBC 0x04
++#define MAX77620_REG_IRQTOP 0x05
++#define MAX77620_REG_INTLBT 0x06
++#define MAX77620_REG_IRQSD 0x07
++#define MAX77620_REG_IRQ_LVL2_L0_7 0x08
++#define MAX77620_REG_IRQ_LVL2_L8 0x09
++#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A
++#define MAX77620_REG_ONOFFIRQ 0x0B
++#define MAX77620_REG_NVERC 0x0C
++#define MAX77620_REG_IRQTOPM 0x0D
++#define MAX77620_REG_INTENLBT 0x0E
++#define MAX77620_REG_IRQMASKSD 0x0F
++#define MAX77620_REG_IRQ_MSK_L0_7 0x10
++#define MAX77620_REG_IRQ_MSK_L8 0x11
++#define MAX77620_REG_ONOFFIRQM 0x12
++#define MAX77620_REG_STATLBT 0x13
++#define MAX77620_REG_STATSD 0x14
++#define MAX77620_REG_ONOFFSTAT 0x15
++
++/* SD and LDO Registers */
++#define MAX77620_REG_SD0 0x16
++#define MAX77620_REG_SD1 0x17
++#define MAX77620_REG_SD2 0x18
++#define MAX77620_REG_SD3 0x19
++#define MAX77620_REG_SD4 0x1A
++#define MAX77620_REG_DVSSD0 0x1B
++#define MAX77620_REG_DVSSD1 0x1C
++#define MAX77620_REG_SD0_CFG 0x1D
++#define MAX77620_REG_SD1_CFG 0x1E
++#define MAX77620_REG_SD2_CFG 0x1F
++#define MAX77620_REG_SD3_CFG 0x20
++#define MAX77620_REG_SD4_CFG 0x21
++#define MAX77620_REG_SD_CFG2 0x22
++#define MAX77620_REG_LDO0_CFG 0x23
++#define MAX77620_REG_LDO0_CFG2 0x24
++#define MAX77620_REG_LDO1_CFG 0x25
++#define MAX77620_REG_LDO1_CFG2 0x26
++#define MAX77620_REG_LDO2_CFG 0x27
++#define MAX77620_REG_LDO2_CFG2 0x28
++#define MAX77620_REG_LDO3_CFG 0x29
++#define MAX77620_REG_LDO3_CFG2 0x2A
++#define MAX77620_REG_LDO4_CFG 0x2B
++#define MAX77620_REG_LDO4_CFG2 0x2C
++#define MAX77620_REG_LDO5_CFG 0x2D
++#define MAX77620_REG_LDO5_CFG2 0x2E
++#define MAX77620_REG_LDO6_CFG 0x2F
++#define MAX77620_REG_LDO6_CFG2 0x30
++#define MAX77620_REG_LDO7_CFG 0x31
++#define MAX77620_REG_LDO7_CFG2 0x32
++#define MAX77620_REG_LDO8_CFG 0x33
++#define MAX77620_REG_LDO8_CFG2 0x34
++#define MAX77620_REG_LDO_CFG3 0x35
++
++#define MAX77620_LDO_SLEW_RATE_MASK 0x1
++
++/* LDO Configuration 3 */
++#define MAX77620_TRACK4_MASK BIT(5)
++#define MAX77620_TRACK4_SHIFT 5
++
++/* Voltage */
++#define MAX77620_SDX_VOLT_MASK 0xFF
++#define MAX77620_SD0_VOLT_MASK 0x3F
++#define MAX77620_SD1_VOLT_MASK 0x7F
++#define MAX77620_LDO_VOLT_MASK 0x3F
++
++#define MAX77620_REG_GPIO0 0x36
++#define MAX77620_REG_GPIO1 0x37
++#define MAX77620_REG_GPIO2 0x38
++#define MAX77620_REG_GPIO3 0x39
++#define MAX77620_REG_GPIO4 0x3A
++#define MAX77620_REG_GPIO5 0x3B
++#define MAX77620_REG_GPIO6 0x3C
++#define MAX77620_REG_GPIO7 0x3D
++#define MAX77620_REG_PUE_GPIO 0x3E
++#define MAX77620_REG_PDE_GPIO 0x3F
++#define MAX77620_REG_AME_GPIO 0x40
++#define MAX77620_REG_ONOFFCNFG1 0x41
++#define MAX77620_REG_ONOFFCNFG2 0x42
++
++/* FPS Registers */
++#define MAX77620_REG_FPS_CFG0 0x43
++#define MAX77620_REG_FPS_CFG1 0x44
++#define MAX77620_REG_FPS_CFG2 0x45
++#define MAX77620_REG_FPS_LDO0 0x46
++#define MAX77620_REG_FPS_LDO1 0x47
++#define MAX77620_REG_FPS_LDO2 0x48
++#define MAX77620_REG_FPS_LDO3 0x49
++#define MAX77620_REG_FPS_LDO4 0x4A
++#define MAX77620_REG_FPS_LDO5 0x4B
++#define MAX77620_REG_FPS_LDO6 0x4C
++#define MAX77620_REG_FPS_LDO7 0x4D
++#define MAX77620_REG_FPS_LDO8 0x4E
++#define MAX77620_REG_FPS_SD0 0x4F
++#define MAX77620_REG_FPS_SD1 0x50
++#define MAX77620_REG_FPS_SD2 0x51
++#define MAX77620_REG_FPS_SD3 0x52
++#define MAX77620_REG_FPS_SD4 0x53
++#define MAX77620_REG_FPS_NONE 0
++
++#define MAX77620_FPS_SRC_MASK 0xC0
++#define MAX77620_FPS_SRC_SHIFT 6
++#define MAX77620_FPS_PU_PERIOD_MASK 0x38
++#define MAX77620_FPS_PU_PERIOD_SHIFT 3
++#define MAX77620_FPS_PD_PERIOD_MASK 0x07
++#define MAX77620_FPS_PD_PERIOD_SHIFT 0
++#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
++#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
++#define MAX77620_FPS_EN_SRC_MASK 0x06
++#define MAX77620_FPS_EN_SRC_SHIFT 1
++#define MAX77620_FPS_ENFPS_SW_MASK 0x01
++#define MAX77620_FPS_ENFPS_SW 0x01
++
++/* Minimum and maximum FPS period time (in microseconds) are
++ * different for MAX77620 and Max20024.
++ */
++#define MAX77620_FPS_PERIOD_MIN_US 40
++#define MAX20024_FPS_PERIOD_MIN_US 20
++
++#define MAX77620_FPS_PERIOD_MAX_US 2560
++#define MAX20024_FPS_PERIOD_MAX_US 5120
++
++#define MAX77620_REG_FPS_GPIO1 0x54
++#define MAX77620_REG_FPS_GPIO2 0x55
++#define MAX77620_REG_FPS_GPIO3 0x56
++#define MAX77620_REG_FPS_RSO 0x57
++#define MAX77620_REG_CID0 0x58
++#define MAX77620_REG_CID1 0x59
++#define MAX77620_REG_CID2 0x5A
++#define MAX77620_REG_CID3 0x5B
++#define MAX77620_REG_CID4 0x5C
++#define MAX77620_REG_CID5 0x5D
++
++#define MAX77620_REG_DVSSD4 0x5E
++#define MAX20024_REG_MAX_ADD 0x70
++
++#define MAX77620_CID_DIDM_MASK 0xF0
++#define MAX77620_CID_DIDM_SHIFT 4
++
++/* CNCG2SD */
++#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
++#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
++
++/* Device Identification Metal */
++#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
++/* Device Indentification OTP */
++#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
++
++/* SD CNFG1 */
++#define MAX77620_SD_SR_MASK 0xC0
++#define MAX77620_SD_SR_SHIFT 6
++#define MAX77620_SD_POWER_MODE_MASK 0x30
++#define MAX77620_SD_POWER_MODE_SHIFT 4
++#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
++#define MAX77620_SD_CFG1_ADE_DISABLE 0
++#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
++#define MAX77620_SD_FPWM_MASK 0x04
++#define MAX77620_SD_FPWM_SHIFT 2
++#define MAX77620_SD_FSRADE_MASK 0x01
++#define MAX77620_SD_FSRADE_SHIFT 0
++#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
++#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
++#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
++#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
++#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
++#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
++
++/* LDO_CNFG2 */
++#define MAX77620_LDO_POWER_MODE_MASK 0xC0
++#define MAX77620_LDO_POWER_MODE_SHIFT 6
++#define MAX77620_LDO_CFG2_ADE_MASK BIT(1)
++#define MAX77620_LDO_CFG2_ADE_DISABLE 0
++#define MAX77620_LDO_CFG2_ADE_ENABLE BIT(1)
++#define MAX77620_LDO_CFG2_SS_MASK BIT(0)
++#define MAX77620_LDO_CFG2_SS_FAST BIT(0)
++#define MAX77620_LDO_CFG2_SS_SLOW 0
++
++#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
++#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
++#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
++#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
++#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
++#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
++#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
++
++#define MAX77620_IRQ_LBM_MASK BIT(3)
++#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
++#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
++
++#define MAX77620_PWR_I2C_ADDR 0x3c
++#define MAX77620_RTC_I2C_ADDR 0x68
++
++#define MAX77620_CNFG_GPIO_DRV_MASK BIT(0)
++#define MAX77620_CNFG_GPIO_DRV_PUSHPULL BIT(0)
++#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN 0
++#define MAX77620_CNFG_GPIO_DIR_MASK BIT(1)
++#define MAX77620_CNFG_GPIO_DIR_INPUT BIT(1)
++#define MAX77620_CNFG_GPIO_DIR_OUTPUT 0
++#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK BIT(2)
++#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK BIT(3)
++#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH BIT(3)
++#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW 0
++#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
++#define MAX77620_CNFG_GPIO_INT_FALLING BIT(4)
++#define MAX77620_CNFG_GPIO_INT_RISING BIT(5)
++#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
++#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
++#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
++#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
++#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
++
++#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
++#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
++#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
++#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
++#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
++#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
++#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
++#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
++
++#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
++
++#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
++#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
++#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
++#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
++#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
++#define MAX20024_ONOFFCNFG1_CLRSE 0x18
++
++#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
++#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
++#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
++#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
++#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
++
++#define MAX77620_GLBLM_MASK BIT(0)
++
++#define MAX77620_WDTC_MASK 0x3
++#define MAX77620_WDTOFFC BIT(4)
++#define MAX77620_WDTSLPC BIT(3)
++#define MAX77620_WDTEN BIT(2)
++
++#define MAX77620_TWD_MASK 0x3
++#define MAX77620_TWD_2s 0x0
++#define MAX77620_TWD_16s 0x1
++#define MAX77620_TWD_64s 0x2
++#define MAX77620_TWD_128s 0x3
++
++#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
++#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
++#define MAX77620_CNFGGLBL1_LBHYST (BIT(5) | BIT(4))
++#define MAX77620_CNFGGLBL1_LBDAC 0x0E
++#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
++
++/* CNFG BBC registers */
++#define MAX77620_CNFGBBC_ENABLE BIT(0)
++#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
++#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
++#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
++#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
++#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
++#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
++#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
++
++#define MAX77620_FPS_COUNT 3
++
++/* Interrupts */
++enum {
++ MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
++ MAX77620_IRQ_TOP_SD, /* SD power fail */
++ MAX77620_IRQ_TOP_LDO, /* LDO power fail */
++ MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
++ MAX77620_IRQ_TOP_RTC, /* RTC */
++ MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
++ MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
++ MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
++ MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
++ MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
++};
++
++/* GPIOs */
++enum {
++ MAX77620_GPIO0,
++ MAX77620_GPIO1,
++ MAX77620_GPIO2,
++ MAX77620_GPIO3,
++ MAX77620_GPIO4,
++ MAX77620_GPIO5,
++ MAX77620_GPIO6,
++ MAX77620_GPIO7,
++ MAX77620_GPIO_NR,
++};
++
++/* FPS Source */
++enum max77620_fps_src {
++ MAX77620_FPS_SRC_0,
++ MAX77620_FPS_SRC_1,
++ MAX77620_FPS_SRC_2,
++ MAX77620_FPS_SRC_NONE,
++ MAX77620_FPS_SRC_DEF,
++};
++
++enum max77620_chip_id {
++ MAX77620,
++ MAX20024,
++};
++
++struct max77620_chip {
++ struct device *dev;
++ struct regmap *rmap;
++
++ int chip_irq;
++ int irq_base;
++
++ /* chip id */
++ enum max77620_chip_id chip_id;
++
++ bool sleep_enable;
++ bool enable_global_lpm;
++ int shutdown_fps_period[MAX77620_FPS_COUNT];
++ int suspend_fps_period[MAX77620_FPS_COUNT];
++
++ struct regmap_irq_chip_data *top_irq_data;
++ struct regmap_irq_chip_data *gpio_irq_data;
++};
++
++#endif /* _MFD_MAX77620_H_ */
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0023-mfd-vexpress-Add-ARCH_USES_GETTIMEOFFSET-dependency.patch b/debian/patches/hikey-4.7-rc1/0023-mfd-vexpress-Add-ARCH_USES_GETTIMEOFFSET-dependency.patch
new file mode 100644
index 0000000..83d7630
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0023-mfd-vexpress-Add-ARCH_USES_GETTIMEOFFSET-dependency.patch
@@ -0,0 +1,47 @@
+From fcdad4210fc001b2d46f4bf97a2860792f4265f8 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Wed, 27 Apr 2016 19:49:22 +0200
+Subject: [PATCH 23/24] mfd: vexpress: Add !ARCH_USES_GETTIMEOFFSET dependency
+
+The MFD_VEXPRESS_SYSREG driver selects CLKSRC_MMIO, which in turn
+conflicts with ARCH_USES_GETTIMEOFFSET, causing a harmless Kconfig
+warning when it is set:
+
+warning: (ARCH_MVEBU && ARCH_DIGICOLOR && ARCH_GEMINI && ARCH_KEYSTONE && ARCH_MOXART && ARCH_MXS && PLAT_SPEAR && ARCH_SUNXI && ARCH_TEGRA && ARCH_U300 && PLAT_ORION && ARCH_CLPS711X && ARCH_EP93XX && ARCH_NETX && ARCH_IXP4XX && ARCH_KS8695 && ARCH_W90X900 && ARCH_PXA && ARCH_SA1100 && ARCH_OMAP1 && ARCH_BCM_IPROC && ARCH_INTEGRATOR_AP && ARCH_OMAP2PLUS && MFD_VEXPRESS_SYSREG) selects CLKSRC_MMIO which has unmet direct dependencies (!ARCH_USES_GETTIMEOFFSET)
+
+This was apparently hidden by the fact that no ARM platform that
+still sets ARCH_USES_GETTIMEOFFSET has gpiolib support, and we
+already have a dependency on GPIOLIB that I added a while ago.
+
+However, after 296ad4acb8ef ("gpio: remove deps on
+ARCH_[WANT_OPTIONAL|REQUIRE]_GPIOLIB"), any platform can enable
+CONFIG_GPIOLIB, and that lets us enable MFD_VEXPRESS_SYSREG
+as well.
+
+This adds an explicit dependency on !ARCH_USES_GETTIMEOFFSET
+to guarantee that we can enable the CLKSRC_MMIO driver without
+getting warnings.
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+---
+ drivers/mfd/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index 16d0bef..a49565c 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -1583,7 +1583,7 @@ endmenu
+
+ config MFD_VEXPRESS_SYSREG
+ bool "Versatile Express System Registers"
+- depends on VEXPRESS_CONFIG && GPIOLIB
++ depends on VEXPRESS_CONFIG && GPIOLIB && !ARCH_USES_GETTIMEOFFSET
+ default y
+ select CLKSRC_MMIO
+ select GPIO_GENERIC_PLATFORM
+--
+2.1.4
+
diff --git a/debian/patches/hikey-4.7-rc1/0024-mfd-hi655x-Add-MFD-driver-for-hi655x.patch b/debian/patches/hikey-4.7-rc1/0024-mfd-hi655x-Add-MFD-driver-for-hi655x.patch
new file mode 100644
index 0000000..39bf9df
--- /dev/null
+++ b/debian/patches/hikey-4.7-rc1/0024-mfd-hi655x-Add-MFD-driver-for-hi655x.patch
@@ -0,0 +1,286 @@
+From b52207ef4ea56f8c22288ec3387399aac72c26cf Mon Sep 17 00:00:00 2001
+From: Chen Feng <puck.chen@hisilicon.com>
+Date: Sun, 14 Feb 2016 14:29:21 +0800
+Subject: [PATCH 24/24] mfd: hi655x: Add MFD driver for hi655x
+
+Add PMIC MFD driver to support hisilicon hi665x.
+
+Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
+Signed-off-by: Fei Wang <w.f@huawei.com>
+Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
+Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+---
+ drivers/mfd/Kconfig | 10 +++
+ drivers/mfd/Makefile | 1 +
+ drivers/mfd/hi655x-pmic.c | 162 ++++++++++++++++++++++++++++++++++++++++
+ include/linux/mfd/hi655x-pmic.h | 55 ++++++++++++++
+ 4 files changed, 228 insertions(+)
+ create mode 100644 drivers/mfd/hi655x-pmic.c
+ create mode 100644 include/linux/mfd/hi655x-pmic.h
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index a49565c..1bcf601 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -319,6 +319,16 @@ config MFD_HI6421_PMIC
+ menus in order to enable them.
+ We communicate with the Hi6421 via memory-mapped I/O.
+
++config MFD_HI655X_PMIC
++ tristate "HiSilicon Hi655X series PMU/Codec IC"
++ depends on ARCH_HISI || COMPILE_TEST
++ depends on OF
++ select MFD_CORE
++ select REGMAP_MMIO
++ select REGMAP_IRQ
++ help
++ Select this option to enable Hisilicon hi655x series pmic driver.
++
+ config HTC_EGPIO
+ bool "HTC EGPIO support"
+ depends on GPIOLIB && ARM
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index 921a08d..42a66e1 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -196,6 +196,7 @@ obj-$(CONFIG_MFD_STW481X) += stw481x.o
+ obj-$(CONFIG_MFD_IPAQ_MICRO) += ipaq-micro.o
+ obj-$(CONFIG_MFD_MENF21BMC) += menf21bmc.o
+ obj-$(CONFIG_MFD_HI6421_PMIC) += hi6421-pmic-core.o
++obj-$(CONFIG_MFD_HI655X_PMIC) += hi655x-pmic.o
+ obj-$(CONFIG_MFD_DLN2) += dln2.o
+ obj-$(CONFIG_MFD_RT5033) += rt5033.o
+ obj-$(CONFIG_MFD_SKY81452) += sky81452.o
+diff --git a/drivers/mfd/hi655x-pmic.c b/drivers/mfd/hi655x-pmic.c
+new file mode 100644
+index 0000000..05ddc78
+--- /dev/null
++++ b/drivers/mfd/hi655x-pmic.c
+@@ -0,0 +1,162 @@
++/*
++ * Device driver for MFD hi655x PMIC
++ *
++ * Copyright (c) 2016 Hisilicon.
++ *
++ * Authors:
++ * Chen Feng <puck.chen@hisilicon.com>
++ * Fei Wang <w.f@huawei.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/gpio.h>
++#include <linux/io.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/hi655x-pmic.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++static const struct mfd_cell hi655x_pmic_devs[] = {
++ { .name = "hi655x-regulator", },
++};
++
++static const struct regmap_irq hi655x_irqs[] = {
++ { .reg_offset = 0, .mask = OTMP_D1R_INT },
++ { .reg_offset = 0, .mask = VSYS_2P5_R_INT },
++ { .reg_offset = 0, .mask = VSYS_UV_D3R_INT },
++ { .reg_offset = 0, .mask = VSYS_6P0_D200UR_INT },
++ { .reg_offset = 0, .mask = PWRON_D4SR_INT },
++ { .reg_offset = 0, .mask = PWRON_D20F_INT },
++ { .reg_offset = 0, .mask = PWRON_D20R_INT },
++ { .reg_offset = 0, .mask = RESERVE_INT },
++};
++
++static const struct regmap_irq_chip hi655x_irq_chip = {
++ .name = "hi655x-pmic",
++ .irqs = hi655x_irqs,
++ .num_regs = 1,
++ .num_irqs = ARRAY_SIZE(hi655x_irqs),
++ .status_base = HI655X_IRQ_STAT_BASE,
++ .mask_base = HI655X_IRQ_MASK_BASE,
++};
++
++static struct regmap_config hi655x_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = HI655X_STRIDE,
++ .val_bits = 8,
++ .max_register = HI655X_BUS_ADDR(0xFFF),
++};
++
++static void hi655x_local_irq_clear(struct regmap *map)
++{
++ int i;
++
++ regmap_write(map, HI655X_ANA_IRQM_BASE, HI655X_IRQ_CLR);
++ for (i = 0; i < HI655X_IRQ_ARRAY; i++) {
++ regmap_write(map, HI655X_IRQ_STAT_BASE + i * HI655X_STRIDE,
++ HI655X_IRQ_CLR);
++ }
++}
++
++static int hi655x_pmic_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct hi655x_pmic *pmic;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ void __iomem *base;
++
++ pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
++ if (!pmic)
++ return -ENOMEM;
++ pmic->dev = dev;
++
++ pmic->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!pmic->res)
++ return -ENOENT;
++
++ base = devm_ioremap_resource(dev, pmic->res);
++ if (!base)
++ return -ENOMEM;
++
++ pmic->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
++ &hi655x_regmap_config);
++
++ regmap_read(pmic->regmap, HI655X_BUS_ADDR(HI655X_VER_REG), &pmic->ver);
++ if ((pmic->ver < PMU_VER_START) || (pmic->ver > PMU_VER_END)) {
++ dev_warn(dev, "PMU version %d unsupported\n", pmic->ver);
++ return -EINVAL;
++ }
++
++ hi655x_local_irq_clear(pmic->regmap);
++
++ pmic->gpio = of_get_named_gpio(np, "pmic-gpios", 0);
++ if (!gpio_is_valid(pmic->gpio)) {
++ dev_err(dev, "Failed to get the pmic-gpios\n");
++ return -ENODEV;
++ }
++
++ ret = devm_gpio_request_one(dev, pmic->gpio, GPIOF_IN,
++ "hi655x_pmic_irq");
++ if (ret < 0) {
++ dev_err(dev, "Failed to request gpio %d ret = %d\n",
++ pmic->gpio, ret);
++ return ret;
++ }
++
++ ret = regmap_add_irq_chip(pmic->regmap, gpio_to_irq(pmic->gpio),
++ IRQF_TRIGGER_LOW | IRQF_NO_SUSPEND, 0,
++ &hi655x_irq_chip, &pmic->irq_data);
++ if (ret) {
++ dev_err(dev, "Failed to obtain 'hi655x_pmic_irq' %d\n", ret);
++ return ret;
++ }
++
++ platform_set_drvdata(pdev, pmic);
++
++ ret = mfd_add_devices(dev, PLATFORM_DEVID_AUTO, hi655x_pmic_devs,
++ ARRAY_SIZE(hi655x_pmic_devs), NULL, 0, NULL);
++ if (ret) {
++ dev_err(dev, "Failed to register device %d\n", ret);
++ regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int hi655x_pmic_remove(struct platform_device *pdev)
++{
++ struct hi655x_pmic *pmic = platform_get_drvdata(pdev);
++
++ regmap_del_irq_chip(gpio_to_irq(pmic->gpio), pmic->irq_data);
++ mfd_remove_devices(&pdev->dev);
++ return 0;
++}
++
++static const struct of_device_id hi655x_pmic_match[] = {
++ { .compatible = "hisilicon,hi655x-pmic", },
++ {},
++};
++
++static struct platform_driver hi655x_pmic_driver = {
++ .driver = {
++ .name = "hi655x-pmic",
++ .of_match_table = of_match_ptr(hi655x_pmic_match),
++ },
++ .probe = hi655x_pmic_probe,
++ .remove = hi655x_pmic_remove,
++};
++module_platform_driver(hi655x_pmic_driver);
++
++MODULE_AUTHOR("Chen Feng <puck.chen@hisilicon.com>");
++MODULE_DESCRIPTION("Hisilicon hi655x PMIC driver");
++MODULE_LICENSE("GPL v2");
+diff --git a/include/linux/mfd/hi655x-pmic.h b/include/linux/mfd/hi655x-pmic.h
+new file mode 100644
+index 0000000..dbbe9a6
+--- /dev/null
++++ b/include/linux/mfd/hi655x-pmic.h
+@@ -0,0 +1,55 @@
++/*
++ * Device driver for regulators in hi655x IC
++ *
++ * Copyright (c) 2016 Hisilicon.
++ *
++ * Authors:
++ * Chen Feng <puck.chen@hisilicon.com>
++ * Fei Wang <w.f@huawei.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __HI655X_PMIC_H
++#define __HI655X_PMIC_H
++
++/* Hi655x registers are mapped to memory bus in 4 bytes stride */
++#define HI655X_STRIDE 4
++#define HI655X_BUS_ADDR(x) ((x) << 2)
++
++#define HI655X_BITS 8
++
++#define HI655X_NR_IRQ 32
++
++#define HI655X_IRQ_STAT_BASE (0x003 << 2)
++#define HI655X_IRQ_MASK_BASE (0x007 << 2)
++#define HI655X_ANA_IRQM_BASE (0x1b5 << 2)
++#define HI655X_IRQ_ARRAY 4
++#define HI655X_IRQ_MASK 0xFF
++#define HI655X_IRQ_CLR 0xFF
++#define HI655X_VER_REG 0x00
++
++#define PMU_VER_START 0x10
++#define PMU_VER_END 0x38
++
++#define RESERVE_INT BIT(7)
++#define PWRON_D20R_INT BIT(6)
++#define PWRON_D20F_INT BIT(5)
++#define PWRON_D4SR_INT BIT(4)
++#define VSYS_6P0_D200UR_INT BIT(3)
++#define VSYS_UV_D3R_INT BIT(2)
++#define VSYS_2P5_R_INT BIT(1)
++#define OTMP_D1R_INT BIT(0)
++
++struct hi655x_pmic {
++ struct resource *res;
++ struct device *dev;
++ struct regmap *regmap;
++ int gpio;
++ unsigned int ver;
++ struct regmap_irq_chip_data *irq_data;
++};
++
++#endif
+--
+2.1.4
+
diff --git a/debian/patches/series b/debian/patches/series
index d64c767..ead353d 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -130,3 +130,28 @@ bugfix/all/tools-build-remove-bpf-run-time-check-at-build-time.patch
bugfix/all/power-cpupower-fix-manpages-NAME.patch
bugfix/all/tools-lib-traceevent-fix-use-of-uninitialized-variables.patch
bugfix/all/scripts-fix-x.509-pem-support-in-sign-file.patch
+
+hikey-4.7-rc1/0001-arm64-dts-Reserve-memory-regions-for-hi6220.patch
+hikey-4.7-rc1/0002-arm64-dts-add-sp804-timer-node-for-Hi6220.patch
+hikey-4.7-rc1/0003-arm64-dts-enable-idle-states-for-Hi6220.patch
+hikey-4.7-rc1/0004-arm64-dts-Add-Hi6220-gpio-configuration-nodes.patch
+hikey-4.7-rc1/0005-arm64-dts-add-Hi6220-pinctrl-configuration-nodes.patch
+hikey-4.7-rc1/0006-arm64-dts-add-Hi6220-spi-configuration-nodes.patch
+hikey-4.7-rc1/0007-arm64-dts-add-all-hi6220-i2c-nodes.patch
+hikey-4.7-rc1/0008-arm64-dts-hikey-enable-i2c0-and-i2c1-for-working-wit.patch
+hikey-4.7-rc1/0009-arm64-dts-Add-hi6220-usb-node.patch
+hikey-4.7-rc1/0010-arm64-dts-add-mailbox-node-for-Hi6220.patch
+hikey-4.7-rc1/0011-arm64-dts-add-Hi6220-s-stub-clock-node.patch
+#hikey-4.7-rc1/0012-arm64-dts-hi6220-add-pinctrl-for-uarts-and-enable-th.patch
+hikey-4.7-rc1/0013-arm64-dts-add-LED-nodes-for-hi6220-hikey.patch
+hikey-4.7-rc1/0014-arm64-dts-hikey-Add-hi655x-pmic-dts-node.patch
+hikey-4.7-rc1/0015-arm64-dts-add-dwmmc-nodes-for-hi6220.patch
+hikey-4.7-rc1/0016-arm64-dts-add-wifi-nodes-support-for-hi6220-hikey.patch
+hikey-4.7-rc1/0017-arm64-dts-register-Hi6220-s-thermal-sensor.patch
+hikey-4.7-rc1/0018-arm64-dts-register-Hi6220-s-thermal-zone-for-power-a.patch
+hikey-4.7-rc1/0019-arm64-dts-Add-L2-cache-topology-to-Hi6220.patch
+hikey-4.7-rc1/0020-mfd-max77693-Allow-building-as-a-module.patch
+hikey-4.7-rc1/0021-mfd-cros_ec-Allow-building-for-ARM64.patch
+hikey-4.7-rc1/0022-mfd-max77620-Add-core-driver-for-MAX77620-MAX20024.patch
+hikey-4.7-rc1/0023-mfd-vexpress-Add-ARCH_USES_GETTIMEOFFSET-dependency.patch
+hikey-4.7-rc1/0024-mfd-hi655x-Add-MFD-driver-for-hi655x.patch
Boot log:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.6.0-trunk-arm64 (debian-kernel@lists.debian.org) (gcc version 5.3.1 20160519 (Debian 5.3.1-20) ) #1 SMP Debian 4.6-1~exp2 (2016-05-30)
[ 0.000000] Boot CPU: AArch64 Processor [410fd033]
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] EFI v2.40 by Linaro HiKey EFI Nov 28 2015 10:50:07
[ 0.000000] efi:
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.0 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: Trusted OS migration not required
[ 0.000000] percpu: Embedded 20 pages/cpu @ffffffc07fe8a000 s43928 r8192 d29800 u81920
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: enabling workaround for ARM erratum 845719
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 507406
[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.6.0-trunk-arm64 console=tty0 console=ttyAMA3,115200 root=/dev/mmcblk1p2 rootwait rw efi=noruntime
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[ 0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[ 0.000000] software IO TLB [mem 0x76f2e000-0x7af2e000] (64MB) mapped at [ffffffc076f2e000-ffffffc07af2dfff]
[ 0.000000] Memory: 1913660K/2062392K available (6036K kernel code, 890K rwdata, 2236K rodata, 2856K init, 500K bss, 148732K reserved, 0K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] modules : 0xffffff8000000000 - 0xffffff8008000000 ( 128 MB)
[ 0.000000] vmalloc : 0xffffff8008000000 - 0xffffffbdbfff0000 ( 246 GB)
[ 0.000000] .text : 0xffffff8008080000 - 0xffffff8008664000 ( 6032 KB)
[ 0.000000] .rodata : 0xffffff8008664000 - 0xffffff8008896000 ( 2248 KB)
[ 0.000000] .init : 0xffffff8008896000 - 0xffffff8008b60000 ( 2856 KB)
[ 0.000000] .data : 0xffffff8008b60000 - 0xffffff8008c3ea00 ( 891 KB)
[ 0.000000] vmemmap : 0xffffffbdc0000000 - 0xffffffbfc0000000 ( 8 GB maximum)
[ 0.000000] 0xffffffbdc0000000 - 0xffffffbdc2000000 ( 32 MB actual)
[ 0.000000] fixed : 0xffffffbffe7fd000 - 0xffffffbffec00000 ( 4108 KB)
[ 0.000000] PCI I/O : 0xffffffbffee00000 - 0xffffffbfffe00000 ( 16 MB)
[ 0.000000] memory : 0xffffffc000000000 - 0xffffffc080000000 ( 2048 MB)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 64.
[ 0.000000] RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=8
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] Architected cp15 timer(s) running at 1.20MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x11b661f8e, max_idle_ns: 1763180809113 ns
[ 0.000004] sched_clock: 56 bits at 1200kHz, resolution 833ns, wraps every 4398046510838ns
[ 0.000091] clocksource: arm,sp804: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns
[ 0.000099] sched_clock: 32 bits at 19MHz, resolution 52ns, wraps every 111848106981ns
[ 0.000551] Console: colour dummy device 80x25
[ 0.001075] console [tty0] enabled
[ 0.001102] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.40 BogoMIPS (lpj=4800)
[ 0.001130] pid_max: default: 32768 minimum: 301
[ 0.001294] Security Framework initialized
[ 0.001312] Yama: disabled by default; enable with sysctl kernel.yama.*
[ 0.001345] AppArmor: AppArmor disabled by boot time parameter
[ 0.001406] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.001424] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.002034] Disabling memory control group subsystem
[ 0.002118] ftrace: allocating 22101 entries in 87 pages
[ 0.036208] ASID allocator initialised with 65536 entries
[ 0.038031] EFI runtime services will be disabled.
[ 0.038935] Detected VIPT I-cache on CPU1
[ 0.038985] CPU1: Booted secondary processor [410fd033]
[ 0.039534] Detected VIPT I-cache on CPU2
[ 0.039558] CPU2: Booted secondary processor [410fd033]
[ 0.040120] Detected VIPT I-cache on CPU3
[ 0.040140] CPU3: Booted secondary processor [410fd033]
[ 0.040740] Detected VIPT I-cache on CPU4
[ 0.040781] CPU4: Booted secondary processor [410fd033]
[ 0.041354] Detected VIPT I-cache on CPU5
[ 0.041375] CPU5: Booted secondary processor [410fd033]
[ 0.041927] Detected VIPT I-cache on CPU6
[ 0.041947] CPU6: Booted secondary processor [410fd033]
[ 0.042522] Detected VIPT I-cache on CPU7
[ 0.042543] CPU7: Booted secondary processor [410fd033]
[ 0.042620] Brought up 8 CPUs
[ 0.042783] SMP: Total of 8 processors activated.
[ 0.042801] CPU: All CPU(s) started at EL2
[ 0.042860] alternatives: patching kernel code
[ 0.043645] devtmpfs: initialized
[ 0.048183] DMI not present or invalid.
[ 0.048421] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.048675] pinctrl core: initialized pinctrl subsystem
[ 0.049611] NET: Registered protocol family 16
[ 0.059835] cpuidle: using governor ladder
[ 0.071028] cpuidle: using governor menu
[ 0.071106] vdso: 2 pages (1 code @ ffffff800866a000, 1 data @ ffffff8008b64000)
[ 0.071152] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.071310] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.071455] Serial: AMBA PL011 UART driver
[ 0.072770] f8015000.uart: ttyAMA0 at MMIO 0xf8015000 (irq = 7, base_baud = 0) is a PL011 rev2
[ 0.073145] f7113000.uart: ttyAMA3 at MMIO 0xf7113000 (irq = 8, base_baud = 0) is a PL011 rev2
[ 0.601784] console [ttyAMA3] enabled
[ 0.609439] hi6220-mbox f7510000.mailbox: Mailbox enabled
[ 0.627325] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 0.634728] ACPI: Interpreter disabled.
[ 0.638830] vgaarb: loaded
[ 0.641749] dmi: Firmware registration failed.
[ 0.647182] clocksource: Switched to clocksource arch_sys_counter
[ 0.676442] VFS: Disk quotas dquot_6.6.0
[ 0.680449] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.687605] pnp: PnP ACPI: disabled
[ 0.697255] NET: Registered protocol family 2
[ 0.702193] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.709569] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
[ 0.716446] TCP: Hash tables configured (established 16384 bind 16384)
[ 0.723042] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[ 0.729098] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[ 0.735784] NET: Registered protocol family 1
[ 0.740360] Unpacking initramfs...
[ 2.232649] Freeing initrd memory: 32824K (ffffffc058f24000 - ffffffc05af32000)
[ 2.241530] futex hash table entries: 2048 (order: 6, 262144 bytes)
[ 2.247973] audit: initializing netlink subsys (disabled)
[ 2.253444] audit: type=2000 audit(2.227:1): initialized
[ 2.259354] workingset: timestamp_bits=44 max_order=19 bucket_order=0
[ 2.265903] zbud: loaded
[ 2.270068] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[ 2.277605] io scheduler noop registered
[ 2.281558] io scheduler deadline registered
[ 2.285876] io scheduler cfq registered (default)
[ 2.291643] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.298874] Serial: AMBA driver
[ 2.302126] msm_serial: driver initialized
[ 2.308289] mousedev: PS/2 mouse device common for all mice
[ 2.315231] ledtrig-cpu: registered to indicate activity on CPUs
[ 2.321256] dmi-sysfs: dmi entry is absent.
[ 2.328124] NET: Registered protocol family 10
[ 2.333866] mip6: Mobile IPv6
[ 2.336861] NET: Registered protocol family 17
[ 2.341326] mpls_gso: MPLS GSO support
[ 2.347761] registered taskstats version 1
[ 2.352070] zswap: loaded using pool lzo/zbud
[ 2.358642] hctosys: unable to open rtc device (rtc0)
[ 2.367641] uart-pl011 f7113000.uart: no DMA platform data
[ 2.374246] Freeing unused kernel memory: 2856K (ffffff8008896000 - ffffff8008b60000)
Loading, please wait...
starting version 229
[ 2.423963] random: systemd-udevd urandom read with 7 bits of entropy available
[ 2.488036] Synopsys Designware Multimedia Card Interface Driver
[ 2.490010] i2c_designware f7100000.i2c: could not find pctldev for node /soc/pinmux@f7010000/i2c0_pmx_func, deferring probe
[ 2.490038] i2c_designware f7101000.i2c: could not find pctldev for node /soc/pinmux@f7010000/i2c1_pmx_func, deferring probe
[ 2.517901] dwmmc_k3 f723d000.dwmmc0: could not find pctldev for node /soc/pinmux@f7010000/emmc_pmx_func, deferring probe
[ 2.528958] dwmmc_k3 f723e000.dwmmc1: could not find pctldev for node /soc/pinmux@f7010000/sd_pmx_func, deferring probe
[ 2.539780] dwmmc_k3 f723f000.dwmmc2: could not find pctldev for node /soc/pinmux@f7010000/sdio_pmx_func, deferring probe
Begin: Loading essential drivers ... done.
Begin: Running /scripts/init-premount ... done.
Begin: Mounting root file system ... Begin: Running /scripts/local-top ... done.
Begin: Running /scripts/local-premount ... [ 2.643221] raid6: int64x1 gen() 457 MB/s
[ 2.715208] raid6: int64x1 xor() 466 MB/s
[ 2.787212] raid6: int64x2 gen() 683 MB/s
[ 2.859184] raid6: int64x2 xor() 604 MB/s
[ 2.931238] raid6: int64x4 gen() 1001 MB/s
[ 3.003196] raid6: int64x4 xor() 747 MB/s
[ 3.075190] raid6: int64x8 gen() 1160 MB/s
[ 3.147194] raid6: int64x8 xor() 746 MB/s
[ 3.219217] raid6: neonx1 gen() 743 MB/s
[ 3.291182] raid6: neonx1 xor() 763 MB/s
[ 3.363208] raid6: neonx2 gen() 1153 MB/s
[ 3.435195] raid6: neonx2 xor() 1017 MB/s
[ 3.507177] raid6: neonx4 gen() 1526 MB/s
[ 3.579184] raid6: neonx4 xor() 1180 MB/s
[ 3.651203] raid6: neonx8 gen() 1689 MB/s
[ 3.723182] raid6: neonx8 xor() 1237 MB/s
[ 3.727461] raid6: using algorithm neonx8 gen() 1689 MB/s
[ 3.732869] raid6: .... xor() 1237 MB/s, rmw enabled
[ 3.737842] raid6: using intx1 recovery algorithm
[ 3.743260] xor: measuring software checksum speed
[ 3.787189] 8regs : 2372.000 MB/sec
[ 3.831188] 8regs_prefetch: 2106.000 MB/sec
[ 3.875189] 32regs : 2623.000 MB/sec
[ 3.919189] 32regs_prefetch: 2168.000 MB/sec
[ 3.923816] xor: using function: 32regs (2623.000 MB/sec)
[ 3.999701] Btrfs loaded
Scanning for Btrfs filesystems
done.
Begin: Waiting for root file system ... Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
done.
Gave up waiting for root device. Common problems:
- Boot args (cat /proc/cmdline)
- Check rootdelay= (did the system wait long enough?)
- Check root= (did the system wait for the right device?)
- Missing modules (cat /proc/modules; ls /dev)
ALERT! /dev/mmcblk1p2 does not exist. Dropping to a shell!
BusyBox v1.22.1 (Debian 1:1.22.0-18) built-in shell (ash)
Enter 'help' for a list of built-in commands.
(initramfs) [ 68.039574] random: nonblocking pool is initialized
(initramfs) lsmod
Module Size Used by Not tainted
btrfs 1109763 0
xor 7989 1 btrfs
raid6_pq 91664 1 btrfs
dw_mmc_k3 4854 0
dw_mmc_pltfm 3515 1 dw_mmc_k3
phy_hi6220_usb 3245 0
i2c_designware_platform 6585 0
i2c_designware_core 9686 1 i2c_designware_platform
dw_mmc 34201 2 dw_mmc_k3,dw_mmc_pltfm
i2c_core 56466 2 i2c_designware_platform,i2c_designware_core
leds_gpio 5021 0
(initramfs)
Attachment:
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