On Sun, 2013-11-17 at 14:27 +0000, Ian Campbell wrote: > On Sun, 2013-11-17 at 13:16 +0000, Ben Hutchings wrote: > > On Sun, 2013-11-17 at 10:43 +0000, Ian Campbell wrote: > > > On Sun, 2013-11-17 at 10:12 +0100, Michael Stapelberg wrote: > > > > Hi Lennert, > > > > > > > > Lennert Buytenhek <buytenh@wantstofly.org> writes: > > > > > The problem here was that the Marvell PHY driver at some point supported > > > > > one or two specific Marvell ethernet PHY models, and people then started > > > > > blindly adding new PHY IDs to it without checking whether the already > > > > > supported PHYs and the PHYs for which support was being added had common > > > > > register layouts (and they didn't). > > > > > > > > > > The result is that on some of the very common Marvell PHYs that this > > > > > driver claims to support, the driver does sequences of register writes > > > > > that have entirely different effects than the intended ones, causing > > > > > various unintended side effects, including complete link failure, and > > > > > e.g. on the quad ethernet PHY on some of the mv78xx0 development > > > > > boards, having the Marvell PHY driver enabled causes link to flap on > > > > > the other three ports if you plug/unplug one of the ports because the > > > > > driver thinks it's a good idea to hard reset the whole chip under > > > > > these circumstances... > > > > > > > > > > What needs to be done is that someone with access to the relevant > > > > > Marvell datasheets fix the driver to behave according to which chip > > > > > it's being used on. It's quite a bit of work to sort out this mess, > > > > > easily several tens of hours -- I started looking into it when I was > > > > > still at Marvell, but didn't get it done before leaving. > > > > Thanks for clarifying. This sounds like it would not be a wise choice to > > > > enable this option again :-(. > > > > > > I'm in two minds about this. > > > > > > The issues have been described in general terms but we don't have any > > > specifics for the platforms supported by Debian. Are any of those known > > > specifically to be broken? > > > > Yes, the DB-78xx0-BP development boards. > > > > The number of ports is the last-but-one digit in the PHY model number so > > we could remove everything with a 4 there. > > Which is only > include/linux/marvell_phy.h:#define MARVELL_PHY_ID_88E1116R 0x01410e40 > I think. According to my grep at least... [...] The model number, not the ID. So: MARVELL_PHY_ID_88E1145 MARVELL_PHY_ID_88E1149R MARVELL_PHY_ID_88E1240 (assuming the PHY IDs and masks are correct for those models). Ben. -- Ben Hutchings Beware of bugs in the above code; I have only proved it correct, not tried it. - Donald Knuth
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