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Bug#689268: Intel HD 4000 (Ivy Bridge) graphics freeze



On Sun, 2012-10-07 at 17:06 +0200, Ingo wrote:
> Interesting to see the differences between the 2 kernels. Compared to
> my messages I found following lines in dmesg have disappeared with 3.5:
> 
> mtrr: type mismatch for e0000000,10000000 old: write-back new:
> write-combining
> 
> [drm] MTRR allocation failed.  Graphics performance may suffer.
> [drm:intel_dsm_platform_mux_info] *ERROR* MUX INFO call failed
> 
> i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
> i915 0000:00:02.0: restoring config space at offset 0xf (was 0x100,
> writing 0x10b)
> i915 0000:00:02.0: restoring config space at offset 0x1 (was 0x900007,
> writing 0x900407)
> i915 0000:00:02.0: setting latency timer to 64
> 
> while enabling RC6 states has been added:
> 
> [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
> 
> 
> Probably a hint to the root cause?

Don't think so.

> I also compared the BIOS settings:
> 
> Javier has these options/settings:
> Integrated Graphics Share Memory   [64MB]
> DVMT Memory                       [256MB]
> 
> I only have:
> IGD DVMT Memory			[256MB]
> 
> (which I called previously "agp-aperture" - ancient name when PC's had
> a dedicated AGP-Port). This is the setting which I did change from
> "max" -> "256MB" and got my system stable - which still holds right now.
> 
> However the "mtrr" setups (/proc/mtrr) are still identical with both
> kernels. Seems the "write-combining area" has become obsolete - or
> still not implemented in i915?

The driver calls ioremap_wc() which will enable write-combining through
the PAT in recent processors.  An MTRR is not needed and in 3.5 the
driver doesn't even bother to allocate one:

commit 9e984bc1dffd405138ff22356188b6a1677c64c8
Author: Adam Jackson <ajax@redhat.com>
Date:   Wed Mar 14 11:22:11 2012 -0400

    drm/i915: Don't do MTRR setup if PAT is enabled

Ben.

-- 
Ben Hutchings
You can't have everything.  Where would you put it?

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