Bug#440654: marked as done (linux-image-2.6.18-5-sparc64: fails to boot on SunFire v880: CPU Exception)
Your message dated Sat, 29 Nov 2008 23:18:54 +0100
with message-id <20081129221854.GA3855@galadriel.inutil.org>
and subject line Re: same problem with SMP machines
has caused the Debian Bug report #440654,
regarding linux-image-2.6.18-5-sparc64: fails to boot on SunFire v880: CPU Exception
to be marked as done.
This means that you claim that the problem has been dealt with.
If this is not the case it is now your responsibility to reopen the
Bug report if necessary, and/or fix the problem forthwith.
(NB: If you are a system administrator and have no idea what this
message is talking about, this may indicate a serious mail system
misconfiguration somewhere. Please contact owner@bugs.debian.org
immediately.)
--
440654: http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=440654
Debian Bug Tracking System
Contact owner@bugs.debian.org with problems
--- Begin Message ---
- To: Debian Bug Tracking System <submit@bugs.debian.org>
- Subject: linux-image-2.6.18-5-sparc64: fails to boot on SunFire v880: CPU Exception
- From: Bernd Zeimetz <bernd@bzed.de>
- Date: Mon, 03 Sep 2007 15:30:36 +0200
- Message-id: <20070903133036.27786.45923.reportbug@hal.toad.homelinux.org>
Package: linux-image-2.6.18-5-sparc64
Version: 2.6.18.dfsg.1-13etch2
Severity: important
Booting this kernel on a SunFire v880 results in a CPU exception:
Remapping the kernel... done.
Booting Linux...
ERROR: CPU3 RED State Exception
[..long output: see attached file..]
This makes Etch uninstallable on v880 machines as this kernel is used by
the installer.
I've searched a bit on google, seems stripping the CPUs from the machine
is a workaround, none I'm willing to go though.
I've tried the latestest d-i with linux-image-2.6.21-2-sparc64, it
neither runs into a CPU exception, nor does it boot at all. THe machine
freezes after printing Booting Linux...
Cheers,
Bernd
ERROR: CPU3 RED State Exception
System State (CPU3 reporting)
BBC Devices: 0000.0000.0000.000f 0000.0000.0000.0000
BBC Arb: 0000.0000.0000.000f 0000.0000.0000.000f
BBC Quiesce: 0000.0000.0000.0003 0000.0000.0000.000c
BBC WDogAct: 0000.0000.0000.0001 0000.0000.0000.0001
BBC POR Gen: 0000.0000.0000.0000 0000.0000.0000.0000
BBC XIR Gen: 0000.0000.0000.0000 0000.0000.0000.0000
BBC POR Src: 0000.0000.0000.0000 0000.0000.0000.0000
BBC XIR Src: 0000.0000.0000.0007 0000.0000.0000.000f
BBC EBus TC: 014f.99fd.a7e6.3f29 014f.99fd.a7e6.3f29
CPU0 Config/Control/Status registers:
CPUVersion: 003e.0014.5400.0507
SafConfig: 0caa.01bc.0000.8002 5:1 ID:0 HBM TOL:15
SafBaseAdr: 0000.0400.0000.0000
DispatchCtl: 0000.0000.0000.0009 MS SI
DCacheCtl: 0000.0200.0000.0000 WE
ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
AFAR: 0000.0000.0000.0000
AFSR: 0000.0000.0000.0000 (no errors set)
DMMU SFAR: 0000.0000.fff7.90c8
DMMU SFSR: 0000.0000.0080.8008 TM PR
IMMU SFSR: 0000.0000.0000.0000 (no status set)
CPU0 Trap registers: Trap Level = 1
*TL=1 TT: 0000.0000.0000.0003
TSTATE: 0000.0099.5800.1600 XCC:NC ICC:NC MM=TSO PEF PRIV IE
TPC: 0000.0000.f004.fac0
TnPC: 0000.0000.f004.fac4
TL=2 TT: 0000.0000.0000.0068
TSTATE: 0000.0099.5804.1400 XCC:NC ICC:NC MM=TSO PEF PRIV
TPC: 0000.0000.f004.a304
TnPC: 0000.0000.f004.a308
TL=3 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
TL=4 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
TL=5 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
CPU0 General registers:
%PIL: 15
%PC: 0000.0000.f004.fac0
%nPC: 0000.0000.f004.fac4
%PSTATE: 0000.0000.0000.0035 MM=TSO AG
%CCR: 0000.0000.0000.0099 XCC:NC ICC:NC
%FPRS: 0000.0000.0000.0005 FEF DL
%v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.004a %v2: 0000.0000.0000.0000
%v3: 0000.0000.fff7.8000 %v4: 0000.0000.0000.10f0 %v5: 0caa.01bc.0000.8002
%v6: 0000.0000.0000.007f %v7: 0000.0000.0000.0194
%m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.000d %m2: 8000.00b0.ffbf.80b6
%m3: 0000.0000.fff7.8000 %m4: 0000.0000.fff7.8000 %m5: ffff.fffc.003f.e000
%m6: 8000.00b0.ffbe.a0b6 %m7: 0000.0000.0000.0001
%a0: 0000.0000.0000.0000 %a1: 0000.07ff.f000.0000 %a2: 0000.0200.0000.0000
%a3: ffff.ffff.f018.5fb2 %a4: 0000.0000.0000.0000 %a5: 0000.0000.0000.0000
%a6: 0000.0000.f000.dacc %a7: ffff.ffff.f001.fc4c
%g0: 0000.0000.0000.0000 %g1: 0000.0000.ffff.ffff %g2: 0000.0000.f000.0000
%g3: 0000.0000.fff7.8000 %g4: 0000.0000.0004.ff64 %g5: 0000.0000.f004.fba4
%g6: 0000.0000.fef7.27f8 %g7: 0000.0000.fef7.1800
%o0: 0000.0000.f000.00e0 %o1: 0000.0000.0000.0005 %o2: 0000.0000.0000.0004
%o3: 0000.0000.f000.00e0 %o4: 0000.0000.0000.001f %o5: 0000.0000.0000.0000
%o6: f000.0000.0000.c5f1 %o7: 0000.0000.f000.dacc
%l0: 0000.0000.fef7.0000 %l1: 0000.0000.0000.4020 %l2: 0000.0000.0000.0021
%l3: 0000.0000.0000.0011 %l4: 0000.0000.f004.6e78 %l5: 0000.0000.0000.0000
%l6: 0000.07ff.fff8.0006 %l7: 0000.0000.07ff.fed6
%i0: ffff.ffff.ffff.ffff %i1: 0000.0000.0000.0000 %i2: 0000.0000.0000.0000
%i3: 0000.0000.0000.0000 %i4: 0000.0000.0000.0000 %i5: 0000.0000.0000.0000
%i6: 0000.0000.0000.0000 %i7: 0000.0000.0000.0000
CPU0 Mem Ctrl registers:
Mem Time Ctl1: 106e.9246.18a2.959a
Mem Time Ctl2: 25c9.a82e.4a09.0020
Mem Time Ctl3: 1050.04c9.24a2.82d0
Mem Time Ctl4: 257d.382c.4a69.0020
Mem Addr Dec1: 8000.7e02.8002.0000
Mem Addr Dec2: 8000.7e02.8002.0200
Mem Addr Dec3: 8000.7e02.8002.0400
Mem Addr Dec4: 8000.7e02.8002.0600
Mem Addr Ctl: 4904.1124.4221.1088
CPU1 Config/Control/Status registers:
CPUVersion: 003e.0014.5400.0507
SafConfig: 0caa.01bc.0002.8002 5:1 ID:1 HBM TOL:15
SafBaseAdr: 0000.0400.0080.0000
DispatchCtl: 0000.0000.0000.0009 MS SI
DCacheCtl: 0000.0200.0000.0000 WE
ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
AFAR: 0000.0000.0000.0000
AFSR: 0000.0000.0000.0000 (no errors set)
DMMU SFAR: 0000.0000.fff7.90c8
DMMU SFSR: 0000.0000.0080.8008 TM PR
IMMU SFSR: 0000.0000.0000.0000 (no status set)
CPU1 Trap registers: Trap Level = 1
*TL=1 TT: 0000.0000.0000.0003
TSTATE: 0000.0099.5800.1600 XCC:NC ICC:NC MM=TSO PEF PRIV IE
TPC: 0000.0000.f004.fac0
TnPC: 0000.0000.f004.fac4
TL=2 TT: 0000.0000.0000.0068
TSTATE: 0000.0099.5804.1400 XCC:NC ICC:NC MM=TSO PEF PRIV
TPC: 0000.0000.f004.a304
TnPC: 0000.0000.f004.a308
TL=3 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
TL=4 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
TL=5 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
CPU1 General registers:
%PIL: 15
%PC: 0000.0000.f004.fac0
%nPC: 0000.0000.f004.fac4
%PSTATE: 0000.0000.0000.0035 MM=TSO AG
%CCR: 0000.0000.0000.0099 XCC:NC ICC:NC
%FPRS: 0000.0000.0000.0005 FEF DL
%v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.004a %v2: 0000.0000.0000.0000
%v3: 0000.0000.fff7.8000 %v4: 0000.0000.0000.10f0 %v5: 0caa.01bc.0002.8002
%v6: 0000.0000.0000.007f %v7: 0000.0000.0000.0194
%m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.000d %m2: 8000.00b0.ffbf.80b6
%m3: 0000.0000.fff7.8000 %m4: 0000.0000.fff7.8000 %m5: ffff.fffc.003f.e000
%m6: 8000.00b0.ffbe.a0b6 %m7: 0000.0000.0000.0001
%a0: 0000.0000.0000.0000 %a1: 0000.07ff.f000.0000 %a2: 0000.0200.0000.0000
%a3: 0000.0000.0000.0000 %a4: 0000.0000.0000.0000 %a5: 0000.0000.0000.0000
%a6: 0000.0000.f000.dacc %a7: ffff.ffff.f001.fc4c
%g0: 0000.0000.0000.0000 %g1: ffff.ffff.f017.b400 %g2: 0000.0000.f000.0000
%g3: 0000.0000.fff7.8000 %g4: 0000.0000.0004.ff64 %g5: 0000.0000.f004.fba4
%g6: 0000.0000.fef7.87f8 %g7: 0000.0000.fef7.7800
%o0: 0000.0000.f000.00e0 %o1: 0000.0000.0000.0005 %o2: 0000.0000.0000.0004
%o3: 0000.0000.f000.00e0 %o4: 0000.0000.0000.001f %o5: 0000.0001.0000.0000
%o6: f000.0000.0001.07f1 %o7: 0000.0000.f000.dacc
%l0: 0000.0000.fef7.6000 %l1: 0000.0000.0000.4020 %l2: 0000.0000.0000.0021
%l3: 0000.0000.0000.0011 %l4: 0000.0000.f004.6e78 %l5: 0000.0000.0000.0001
%l6: 0000.07ff.fff8.0006 %l7: 0000.0000.07ff.fed6
%i0: ffff.ffff.ffff.ffff %i1: 0000.0000.0000.0000 %i2: 0000.0000.0000.0000
%i3: 0000.0000.0000.0000 %i4: 0000.0000.0000.0000 %i5: 0000.0000.0000.0000
%i6: 0000.0000.0000.0000 %i7: 0000.0000.0000.0000
CPU1 Mem Ctrl registers:
Mem Time Ctl1: 106e.9246.18a2.959a
Mem Time Ctl2: 25c9.a82e.4a09.0020
Mem Time Ctl3: 1050.04c9.24a2.82d0
Mem Time Ctl4: 257d.382c.4a69.0020
Mem Addr Dec1: 8000.7e02.c002.0000
Mem Addr Dec2: 8000.7e02.c002.0200
Mem Addr Dec3: 8000.7e02.c002.0400
Mem Addr Dec4: 8000.7e02.c002.0600
Mem Addr Ctl: 4904.1124.4221.1088
CPU2 Config/Control/Status registers:
CPUVersion: 003e.0014.5400.0507
SafConfig: 1534.01bc.0004.8002 5:1 ID:2 HBM TOL:15
SafBaseAdr: 0000.0400.0100.0000
DispatchCtl: 0000.0000.0000.0009 MS SI
DCacheCtl: 0000.0200.0000.0000 WE
ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
AFAR: 0000.0000.0000.0000
AFSR: 0000.0000.0000.0000 (no errors set)
DMMU SFAR: 0000.0000.fff7.90c8
DMMU SFSR: 0000.0000.0080.8008 TM PR
IMMU SFSR: 0000.0000.0000.0000 (no status set)
CPU2 Trap registers: Trap Level = 1
*TL=1 TT: 0000.0000.0000.0003
TSTATE: 0000.0099.5800.1600 XCC:NC ICC:NC MM=TSO PEF PRIV IE
TPC: 0000.0000.f004.fac0
TnPC: 0000.0000.f004.fac4
TL=2 TT: 0000.0000.0000.0068
TSTATE: 0000.0099.5804.1400 XCC:NC ICC:NC MM=TSO PEF PRIV
TPC: 0000.0000.f004.a304
TnPC: 0000.0000.f004.a308
TL=3 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
TL=4 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
TL=5 TT: 0000.0000.0000.0000
TSTATE: 0000.0000.0000.0000 XCC:(clear) ICC:(clear) MM=TSO
TPC: 0000.0000.0000.0000
TnPC: 0000.0000.0000.0000
CPU2 General registers:
%PIL: 15
%PC: 0000.0000.f004.fac0
%nPC: 0000.0000.f004.fac4
%PSTATE: 0000.0000.0000.0035 MM=TSO AG
%CCR: 0000.0000.0000.0099 XCC:NC ICC:NC
%FPRS: 0000.0000.0000.0005 FEF DL
%v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.004a %v2: 0000.0000.0000.0000
%v3: 0000.0000.fff7.8000 %v4: 0000.0000.0000.10f0 %v5: 1534.01bc.0004.8002
%v6: 0000.0000.0000.007f %v7: 0000.0000.0000.0194
%m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.000d %m2: 8000.00b0.ffbf.80b6
%m3: 0000.0000.fff7.8000 %m4: 0000.0000.fff7.8000 %m5: ffff.fffc.003f.e000
%m6: 8000.00b0.ffbe.a0b6 %m7: 0000.0000.0000.0001
%a0: 0000.0000.0000.0000 %a1: 0000.07ff.f000.0000 %a2: 0000.0200.0000.0000
%a3: 0000.0000.0000.0000 %a4: 0000.0000.0000.0000 %a5: 0000.0000.0000.0000
%a6: 0000.0000.f000.dacc %a7: ffff.ffff.f001.fc4c
%g0: 0000.0000.0000.0000 %g1: ffff.ffff.f017.b400 %g2: 0000.0000.f000.0000
%g3: 0000.0000.fff7.8000 %g4: 0000.0000.0004.ff64 %g5: 0000.0000.f004.fba4
%g6: 0000.0000.fef7.e7f8 %g7: 0000.0000.fef7.d800
%o0: 0000.0000.f000.00e0 %o1: 0000.0000.0000.0005 %o2: 0000.0000.0000.0004
%o3: 0000.0000.f000.00e0 %o4: 0000.0000.0000.001f %o5: 0000.0002.0000.0000
%o6: f000.0000.0001.49f1 %o7: 0000.0000.f000.dacc
%l0: 0000.0000.fef7.c000 %l1: 0000.0000.0000.4020 %l2: 0000.0000.0000.0021
%l3: 0000.0000.0000.0011 %l4: 0000.0000.f004.6e78 %l5: 0000.0000.0000.0002
%l6: 0000.07ff.fff8.0006 %l7: 0000.0000.07ff.fec3
%i0: ffff.ffff.ffff.ffff %i1: 0000.0000.0000.0000 %i2: 0000.0000.0000.0000
%i3: 0000.0000.0000.0000 %i4: 0000.0000.0000.0000 %i5: 0000.0000.0000.0000
%i6: 0000.0000.0000.0000 %i7: 0000.0000.0000.0000
CPU2 Mem Ctrl registers:
Mem Time Ctl1: 106e.9246.18a2.959a
Mem Time Ctl2: 25c9.a82e.4a09.0020
Mem Time Ctl3: 1050.04c9.24a2.82d0
Mem Time Ctl4: 257d.382c.4a69.0020
Mem Addr Dec1: 8000.7e02.8002.0100
Mem Addr Dec2: 8000.7e02.8002.0300
Mem Addr Dec3: 8000.7e02.8002.0500
Mem Addr Dec4: 8000.7e02.8002.0700
Mem Addr Ctl: 4904.1124.4221.1088
CPU3 Config/Control/Status registers:
CPUVersion: 003e.0014.5400.0507
SafConfig: 1534.01bc.0006.8002 5:1 ID:3 HBM TOL:15
SafBaseAdr: 0000.0400.0180.0000
DispatchCtl: 0000.0000.0000.003b MS IFP SI RPE BPE
DCacheCtl: 0000.0000.0000.0000
ECacheCtl: 0000.0000.0009.4400 3:1 8MB mode=3-3-3 R/W-turn:2 ECC:on
ErrorEnable: 0000.0000.0000.000b CEEN NCEEN UCEEN
AFAR: 0000.07ff.ea00.1800
AFSR: 0000.0000.0000.0000 (no errors set)
DMMU SFAR: 0000.0000.0000.00cc
DMMU SFSR: 0000.0000.0080.8008 TM PR
IMMU SFSR: 0000.0000.0080.8008 TM PR
CPU3 Trap registers: Trap Level = 5
TL=1 TT: 0000.0000.0000.0010
TSTATE: 0000.0000.8000.9606 XCC:(clear) ICC:(clear) PEF PRIV IE
TPC: 0000.0000.0041.ac58
TnPC: 0000.0000.0041.ac5c
TL=2 TT: 0000.0000.0000.0010
TSTATE: 0000.0000.8000.9500 XCC:(clear) ICC:(clear) PEF PRIV AG
TPC: 0000.0000.0041.1198
TnPC: 0000.0000.0041.119c
TL=3 TT: 0000.0000.0000.0010
TSTATE: 0000.0000.8000.9500 XCC:(clear) ICC:(clear) PEF PRIV AG
TPC: 0000.0000.0041.4200
TnPC: 0000.0000.0041.4204
TL=4 TT: 0000.0000.0000.0010
TSTATE: 0000.0000.8000.9500 XCC:(clear) ICC:(clear) PEF PRIV AG
TPC: 0000.0000.0041.4200
TnPC: 0000.0000.0041.4204
*TL=5 TT: 0000.0000.0000.0010
TSTATE: 0000.0000.8000.9500 XCC:(clear) ICC:(clear) PEF PRIV AG
TPC: 0000.0000.0041.4200
TnPC: 0000.0000.0041.4204
CPU3 General registers:
%PIL: 15
%PC: 0000.0000.0041.4200
%nPC: 0000.0000.0041.4204
%PSTATE: 0000.0000.0000.0035 MM=TSO AG
%CCR: 0000.0000.0000.0091 XCC:NC ICC:C
%FPRS: 0000.0000.0000.0000
%v0: 0000.0000.0000.0000 %v1: 0000.0000.0000.0000 %v2: 0000.0000.0000.0000
%v3: 0000.0000.0000.0000 %v4: ffff.ffff.0000.0000 %v5: 0000.0000.0000.0000
%v6: 0000.0000.0000.0000 %v7: 0129.7000.8013.0c25
%m0: 0000.0000.0000.0000 %m1: 0000.0000.0000.0000 %m2: 4040.4040.4040.4040
%m3: 4040.4040.4040.4040 %m4: 0000.0000.0000.0000 %m5: 0000.0000.0000.0494
%m6: 0000.0000.0000.0000 %m7: 0000.0000.0000.03ff
%a0: 0000.0000.0000.0000 %a1: 504f.5354.0000.0000 %a2: 0000.0200.0000.0000
%a3: 0000.0000.0000.0011 %a4: 0000.0000.0000.0002 %a5: 0000.0000.0000.0000
%a6: 0000.0000.0041.0210 %a7: ffff.ffff.f002.018c
%g0: 0000.0000.0000.0000 %g1: 0000.0000.0000.0004 %g2: 0000.0000.0000.0000
%g3: 0000.0000.0051.0b60 %g4: 0000.0000.0068.1a20 %g5: 0000.0000.0000.0000
%g6: 0000.0000.0068.0e40 %g7: 0000.0000.0000.0020
%o0: 0000.0000.0041.19d0 %o1: 0000.0000.0000.0005 %o2: 0000.0000.0063.cf60
%o3: 0000.0000.0045.5848 %o4: 0000.0000.0051.101e %o5: 0000.0000.0063.0e00
%o6: 0000.0000.0041.1111 %o7: 0000.0000.0041.0210
%l0: 0000.0000.0000.9000 %l1: 0000.0000.0073.5548 %l2: 0000.0000.0041.0210
%l3: 0000.0000.0000.0069 %l4: 0000.0000.0000.0002 %l5: 0000.0000.0000.0000
%l6: 0000.0000.0068.0e40 %l7: 0000.0000.8000.9000
%i0: 0000.0000.0041.1b30 %i1: 0000.0000.0000.0005 %i2: 0000.0000.0041.aaa0
%i3: 0000.0000.0045.47c8 %i4: 0000.0000.0000.020f %i5: 0000.0000.0000.0000
%i6: 0000.0000.0041.1271 %i7: 0000.0000.0041.0210
CPU3 Mem Ctrl registers:
Mem Time Ctl1: 106e.9246.18a2.959a
Mem Time Ctl2: 25c9.a82e.4a09.0020
Mem Time Ctl3: 1050.04c9.24a2.82d0
Mem Time Ctl4: 257d.382c.4a69.0020
Mem Addr Dec1: 8000.7e02.c002.0100
Mem Addr Dec2: 8000.7e02.c002.0300
Mem Addr Dec3: 8000.7e02.c002.0500
Mem Addr Dec4: 8000.7e02.c002.0700
Mem Addr Ctl: 4904.1124.4221.1088
IO-Bridge 8 at 0000.0400.0400.0000
Device ID fc00.0000.0011.a954
Ctl/Stat 0255.5554.0080.7e02
Error Ctl fc00.0000.0000.03e0
Int Ctl 8000.0000.0000.0017
Error Log 0000.0000.0000.0000
ECC Ctl e000.0000.0000.0000
EStar Ctl 0000.0000.0000.0001
Queue Ctl 0000.0000.0000.0000
Address Match Address Mask
PCIA Mem 8000.07fd.0000.0000 0000.07ff.0000.0000
PCIA C/IO 8000.07ff.ec00.0000 0000.07ff.fe00.0000
PCIB Mem 8000.07fe.0000.0000 0000.07ff.0000.0000
PCIB C/IO 8000.07ff.ee00.0000 0000.07ff.fe00.0000
AFAR AFSR
UE 0000.0000.0000.0000 0000.0000.0000.0000
CE 0000.0000.0000.0000 0000.0000.0000.0000
PCI A 0000.0000.0000.0000 0000.0000.0000.0000
PCI B 0000.0000.0000.0000 0000.0000.0000.0000
Control/Status Idle Check Diag Diagnostic
PCI A 0000.0002.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
PCI B 0000.0000.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
IO-Bridge 9 at 0000.0400.0480.0000
Device ID fc00.0000.0013.a954
Ctl/Stat 0255.59a8.0090.7e02
Error Ctl fc00.0000.0000.03e0
Int Ctl 8000.0000.0000.0017
Error Log 0000.0000.0000.0000
ECC Ctl e000.0000.0000.0000
EStar Ctl 0000.0000.0000.0001
Queue Ctl 0000.0000.0000.0000
Address Match Address Mask
PCIA Mem 8000.07fb.0000.0000 0000.07ff.0000.0000
PCIA C/IO 8000.07ff.e800.0000 0000.07ff.fe00.0000
PCIB Mem 8000.07fc.0000.0000 0000.07ff.0000.0000
PCIB C/IO 8000.07ff.ea00.0000 0000.07ff.fe00.0000
AFAR AFSR
UE 0000.0000.0000.0000 0000.0000.0000.0000
CE 0000.0000.2000.0000 0000.0000.0000.0000
PCI A 0000.0000.0000.0000 0000.0000.0000.0000
PCI B 0000.0000.0000.0000 0000.0000.0000.0000
Control/Status Idle Check Diag Diagnostic
PCI A 0000.0002.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
PCI B 0000.0000.010e.003f 0000.0000.0000.8000 0000.0000.0000.0000
Resetting...
RSC Alert: Host System has Reset
ERROR: CPU RED-State Exception Reset Recovery
--- End Message ---
--- Begin Message ---
Version: 2.6.23-1
On Sat, Nov 29, 2008 at 06:08:01PM +0100, Bernd Zeimetz wrote:
> Moritz Muehlenhoff wrote:
> > On Thu, Sep 13, 2007 at 03:42:36AM +0200, Bernd Zeimetz wrote:
> >> although no non-SMP kernel boots on this machine as reported in #440720,
> >> even the 2.6.18 SMP kernel from Etch just hangs the machine, just not as
> >> badly as the non-SMP kernel.
> >
> > Does this error still occur with more recent kernel versions?
>
> no, at least since 2.6.23 (if I remember right) the kernels just boot fine.
> #440720 was fixed, too.
Ok, marking both as fixed in that version.
Cheers,
Moritz
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