Flushing the data cache

[Camm Maguire <camm@enhanced.com>]

Greetings!  GCL loads binary modules into its data section, and then
attempts executing the code thus loaded.  On some RISC machines, it
needs to flush the data cache after writing and before executing.
Some samples are included at the end of this post.  

What I'm looking for is the analog on ia64, which does appear to be
necessary after all.  Can anyone help?

Take care,

-- 
Camm Maguire			     			camm@enhanced.com
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"The earth is but one country, and mankind its citizens."  --  Baha'u'llah

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ppc:

#define CLEAR_CACHE_LINE_SIZE 32
#define CLEAR_CACHE do {void *v=memory->cfd.cfd_start,*ve=v+memory->cfd.cfd_size; \
                        v=(void *)((unsigned long)v & ~(CLEAR_CACHE_LINE_SIZE - 1));\
                        for (;v<ve;v+=CLEAR_CACHE_LINE_SIZE) \
                           asm __volatile__ ("dcbst 0,%0\n\tsync\n\ticbi 0,%0\n\tsync\n\tisync": : "r" (v) : "memory");\
                        } while(0)
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m68k:
#define CLEAR_CACHE_LINE_SIZE
#define CLEAR_CACHE do {void *v=memory->cfd.cfd_start,*ve=v+memory->cfd.cfd_size; \
                        v=(void *)((unsigned long)v & ~(CLEAR_CACHE_LINE_SIZE - 1));\
                        cacheflush(v,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,ve-v);\
                    } while(0)
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arm:
#define CLEAR_CACHE do {\
  void *v=memory->cfd.cfd_start,*ve=v+memory->cfd.cfd_size; \
  register unsigned long _beg __asm ("a1") = (unsigned long)(v);	\
  register unsigned long _end __asm ("a2") = (unsigned long)(ve);\
  register unsigned long _flg __asm ("a3") = 0;			\
  __asm __volatile ("swi 0x9f0002		@ sys_cacheflush"	\
		    : "=r" (_beg)				\
		    : "0" (_beg), "r" (_end), "r"(_flg));	\
} while (0)
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