[glibc] 01/01: patches/hurd-i386/tg-tls.diff: update
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sthibault pushed a commit to branch glibc-2.25
in repository glibc.
commit bb02b3323af1b8d1f632e72aa8315c6e21712e93
Author: Samuel Thibault <samuel.thibault@ens-lyon.org>
Date: Wed Aug 2 20:26:19 2017 +0000
patches/hurd-i386/tg-tls.diff: update
---
debian/changelog | 1 +
debian/patches/hurd-i386/tg-tls.diff | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/debian/changelog b/debian/changelog
index e049f65..7e7fc03 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -2,6 +2,7 @@ glibc (2.25-0experimental1) UNRELEASED; urgency=medium
[ Samuel Thibault ]
* patches/hurd-i386/submitted-net.diff: rebased.
+ * patches/hurd-i386/tg-tls.diff: update.
-- Aurelien Jarno <aurel32@debian.org> Wed, 02 Aug 2017 19:03:14 +0200
diff --git a/debian/patches/hurd-i386/tg-tls.diff b/debian/patches/hurd-i386/tg-tls.diff
index aa38740..881668b 100644
--- a/debian/patches/hurd-i386/tg-tls.diff
+++ b/debian/patches/hurd-i386/tg-tls.diff
@@ -257,6 +257,22 @@ glibc-2.8/debian/patches/hurd-i386/local-tls-support.diff 3151
properly before before cthreads initialization, so cthreads can know
--- a/sysdeps/mach/hurd/i386/tls.h
+++ b/sysdeps/mach/hurd/i386/tls.h
+@@ -56,6 +56,15 @@ typedef struct
+ #define TLS_TCB_AT_TP 1
+ #define TLS_DTV_AT_TP 0
+
++/* Alignment requirement for TCB.
++
++ Some processors such as Intel Atom pay a big penalty on every
++ access using a segment override if that segment's base is not
++ aligned to the size of a cache line. (See Intel 64 and IA-32
++ Architectures Optimization Reference Manual, section 13.3.3.3,
++ "Segment Base".) On such machines, a cache line is 64 bytes. */
++#define TCB_ALIGNMENT 64
++
+ #ifndef __ASSEMBLER__
+
+ /* Use i386-specific RPCs to arrange that %gs segment register prefix
@@ -70,7 +70,7 @@ _hurd_tls_init (tcbhead_t *tcb, int seco
/* Get the first available selector. */
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/pkg-glibc/glibc.git
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