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Bug#850182: Please disable TSX in stretch and backport to jessie



On 2017-01-05 09:15, Henrique de Moraes Holschuh wrote:
> On Wed, Jan 4, 2017, at 17:04, Ian Jackson wrote:
> > amd64 with TSX is for the purposes of pthreads like a new
> > architecture: the locking primitives behave differently and expose
> > extra bugs.
> 
> Also valid for S/390x, POWER, and anything else where glibc 2.24
> supports hardware lock elision.

Do you have some pointers about the different behaviour of locking
primitives on S/390 and POWER? They accept to "unlock" already unlocked
mutexes and I haven't seen any bug report about that so far. There have
been a few issues fixed on the glibc and gcc side at the beginning, but
it hasn't been the case for quite some time now.

Also Note that IBM doesn't apply market segmentation the same way than
Intel, so all relatively recent CPUs (less than 5 years for POWER, less
than 3 years for S/390) do support transactional memory. Actually we
even require a POWER7+ CPU for the ppc64el port, so we are sure to have
transactional memory instructions.

Aurelien

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

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