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r6645 - in glibc-package/branches/glibc-2.21/debian: . patches patches/amd64

Author: aurel32
Date: 2015-10-18 19:56:19 +0000 (Sun, 18 Oct 2015)
New Revision: 6645

Added:
   glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-for-Intel-TSX.diff
Removed:
   glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff
Modified:
   glibc-package/branches/glibc-2.21/debian/changelog
   glibc-package/branches/glibc-2.21/debian/patches/series
Log:
Replace patches/amd64/local-blacklist-on-TSX-Haswell.diff by 
local-blacklist-for-Intel-TSX.diff also blacklisting some Broadwell
models.  Closes: #800574.

Modified: glibc-package/branches/glibc-2.21/debian/changelog
===================================================================
--- glibc-package/branches/glibc-2.21/debian/changelog	2015-10-18 17:42:25 UTC (rev 6644)
+++ glibc-package/branches/glibc-2.21/debian/changelog	2015-10-18 19:56:19 UTC (rev 6645)
@@ -79,6 +79,11 @@
     support for futex_atomic_cmpxchg_inatomic to restore the  previous state
     and fix the pulsesink (and others) regression on ARM (closes: #788799)
 
+  [ Henrique de Moraes Holschuh ]
+  * Replace patches/amd64/local-blacklist-on-TSX-Haswell.diff by 
+    local-blacklist-for-Intel-TSX.diff also blacklisting some Broadwell
+    models.  Closes: #800574.
+
  -- Aurelien Jarno <aurel32@debian.org>  Sat, 29 Aug 2015 00:43:44 +0200
 
 glibc (2.21-0experimental1) experimental; urgency=medium

Added: glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-for-Intel-TSX.diff
===================================================================
--- glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-for-Intel-TSX.diff	                        (rev 0)
+++ glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-for-Intel-TSX.diff	2015-10-18 19:56:19 UTC (rev 6645)
@@ -0,0 +1,99 @@
+Intel TSX is broken on Haswell based processors (erratum HSD136/HSW136)
+and a microcode update is available to simply disable the corresponding
+instructions.
+
+A live microcode update will disable the TSX instructions causing
+already started binaries to segfault. This patch simply disable Intel
+TSX (HLE and RTM) on processors which might receive a microcode update,
+so that it doesn't happen.  We might expect newer steppings to fix the
+issue (e.g. as Haswell-EX did).
+
+Intel TSX-NI is also broken on Broadwell systems, and documented as
+being unavailable in their specification updates errata list.  However,
+some end-user systems were shipped with old microcode that left Intel
+TSX-NI still enabled in CPUID on these processors.  We must not allow
+RTM to be used by glibc on these systems, due to runtime system
+misbehavior and live-update of microcode hazards.
+
+Author: Henrique de Moraes Holschuh <hmh@debian.org>
+
+--- a/sysdeps/x86_64/multiarch/init-arch.c
++++ b/sysdeps/x86_64/multiarch/init-arch.c
+@@ -26,7 +26,7 @@
+ 
+ 
+ static void
+-get_common_indeces (unsigned int *family, unsigned int *model)
++get_common_indeces (unsigned int *family, unsigned int *model, unsigned int *stepping)
+ {
+   __cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,
+ 	   __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,
+@@ -36,6 +36,7 @@
+   unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
+   *family = (eax >> 8) & 0x0f;
+   *model = (eax >> 4) & 0x0f;
++  *stepping = eax & 0x0f;
+ }
+ 
+ 
+@@ -47,6 +48,7 @@
+   unsigned int edx;
+   unsigned int family = 0;
+   unsigned int model = 0;
++  unsigned int stepping = 0;
+   enum cpu_features_kind kind;
+ 
+   __cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);
+@@ -56,7 +58,7 @@
+     {
+       kind = arch_kind_intel;
+ 
+-      get_common_indeces (&family, &model);
++      get_common_indeces (&family, &model, &stepping);
+ 
+       unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
+       unsigned int extended_family = (eax >> 20) & 0xff;
+@@ -135,7 +137,7 @@
+     {
+       kind = arch_kind_amd;
+ 
+-      get_common_indeces (&family, &model);
++      get_common_indeces (&family, &model, &stepping);
+ 
+       ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
+ 
+@@ -188,6 +190,24 @@
+ 	}
+     }
+ 
++  /* Disable Intel TSX (HLE and RTM) due to erratum HSD136/HSW136
++     on all Haswell processors, except Haswell-EX/Xeon E7-v3 (306F4),
++     to work around outdated microcode that doesn't disable the
++     broken feature by default.
++
++     Disable TSX on Broadwell, due to errata BDM53/BDW51/BDD51/
++     BDE42.  The errata documentation states that RTM is unusable,
++     and that it should not be advertised by CPUID at all on any
++     such processors.  Unfortunately, it _is_ advertised in some
++     (older) microcode versions.  Exceptions: Broadwell-E (406Fx),
++     likely already fixed at launch */
++  if (kind == arch_kind_intel && family == 6 &&
++      ((model == 63 && stepping <= 2) || (model == 60 && stepping <= 3) ||
++       (model == 69 && stepping <= 1) || (model == 70 && stepping <= 1) ||
++       (model == 61 && stepping <= 4) || (model == 71 && stepping <= 1) ||
++       (model == 86 && stepping <= 2) ))
++    __cpu_features.cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_RTM | bit_HLE);
++
+   __cpu_features.family = family;
+   __cpu_features.model = model;
+   atomic_write_barrier ();
+--- a/sysdeps/x86_64/multiarch/init-arch.h
++++ b/sysdeps/x86_64/multiarch/init-arch.h
+@@ -43,6 +43,7 @@
+ /* COMMON_CPUID_INDEX_7.  */
+ #define bit_RTM		(1 << 11)
+ #define bit_AVX2	(1 << 5)
++#define bit_HLE		(1 << 4)
+ 
+ /* XCR0 Feature flags.  */
+ #define bit_XMM_state  (1 << 1)

Deleted: glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff
===================================================================
--- glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff	2015-10-18 17:42:25 UTC (rev 6644)
+++ glibc-package/branches/glibc-2.21/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff	2015-10-18 19:56:19 UTC (rev 6645)
@@ -1,88 +0,0 @@
-Intel TSX is broken on Haswell based processors (erratum HSD136/HSW136)
-and a microcode update is available to simply disable the corresponding
-instructions.
-
-While the responsability to continue or not using TSX should be left to
-the users, a live microcode update will disable the TSX instructions
-causing already started binaries to segfault. This patch simply disable 
-Intel TSX (HLE and RTM) on processors which might receive a microcode
-update, so that it doesn't happen. We might expect newer steppings to
-fix the issue, and if it is not the case the corresponding processors 
-will be shipped with TSX already disabled.
-
-Author: Henrique de Moraes Holschuh <hmh@debian.org>
-
-diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
-index db74d97..6f61ae6 100644
---- a/sysdeps/x86_64/multiarch/init-arch.c
-+++ b/sysdeps/x86_64/multiarch/init-arch.c
-@@ -26,7 +26,7 @@ struct cpu_features __cpu_features attribute_hidden;
- 
- 
- static void
--get_common_indeces (unsigned int *family, unsigned int *model)
-+get_common_indeces (unsigned int *family, unsigned int *model, unsigned int *stepping)
- {
-   __cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,
- 	   __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,
-@@ -36,6 +36,7 @@ get_common_indeces (unsigned int *family, unsigned int *model)
-   unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
-   *family = (eax >> 8) & 0x0f;
-   *model = (eax >> 4) & 0x0f;
-+  *stepping = eax & 0x0f;
- }
- 
- 
-@@ -47,6 +48,7 @@ __init_cpu_features (void)
-   unsigned int edx;
-   unsigned int family = 0;
-   unsigned int model = 0;
-+  unsigned int stepping = 0;
-   enum cpu_features_kind kind;
- 
-   __cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);
-@@ -56,7 +58,7 @@ __init_cpu_features (void)
-     {
-       kind = arch_kind_intel;
- 
--      get_common_indeces (&family, &model);
-+      get_common_indeces (&family, &model, &stepping);
- 
-       unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
-       unsigned int extended_family = (eax >> 20) & 0xff;
-@@ -131,7 +133,7 @@ __init_cpu_features (void)
-     {
-       kind = arch_kind_amd;
- 
--      get_common_indeces (&family, &model);
-+      get_common_indeces (&family, &model, &stepping);
- 
-       ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
- 
-@@ -176,6 +178,14 @@ __init_cpu_features (void)
- 	}
-     }
- 
-+  /* Disable Intel TSX (HLE and RTM) due to erratum HSD136/HSW136
-+     on Haswell processors, to work around outdated microcode that
-+     doesn't disable the broken feature by default */
-+  if (kind == arch_kind_intel && family == 6 &&
-+      ((model == 63 && stepping <= 2) || (model == 60 && stepping <= 3) ||
-+       (model == 69 && stepping <= 1) || (model == 70 && stepping <= 1)))
-+    __cpu_features.cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_RTM | bit_HLE);
-+
-   __cpu_features.family = family;
-   __cpu_features.model = model;
-   atomic_write_barrier ();
-diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h
-index 793707a..e2745cb 100644
---- a/sysdeps/x86_64/multiarch/init-arch.h
-+++ b/sysdeps/x86_64/multiarch/init-arch.h
-@@ -40,6 +40,7 @@
- 
- /* COMMON_CPUID_INDEX_7.  */
- #define bit_RTM		(1 << 11)
-+#define bit_HLE		(1 << 4)
- #define bit_AVX2	(1 << 5)
- 
- /* XCR0 Feature flags.  */

Modified: glibc-package/branches/glibc-2.21/debian/patches/series
===================================================================
--- glibc-package/branches/glibc-2.21/debian/patches/series	2015-10-18 17:42:25 UTC (rev 6644)
+++ glibc-package/branches/glibc-2.21/debian/patches/series	2015-10-18 19:56:19 UTC (rev 6645)
@@ -43,7 +43,7 @@
 alpha/submitted-rtld-fPIC.diff
 alpha/local-string-functions.diff
 
-amd64/local-blacklist-on-TSX-Haswell.diff
+amd64/local-blacklist-for-Intel-TSX.diff
 
 arm/local-ioperm.diff
 arm/local-sigaction.diff
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