r6301 - in glibc-package/trunk/debian: . patches patches/amd64
Author: aurel32
Date: 2014-10-21 11:07:18 +0000 (Tue, 21 Oct 2014)
New Revision: 6301
Added:
glibc-package/trunk/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff
Modified:
glibc-package/trunk/debian/changelog
glibc-package/trunk/debian/patches/series
Log:
patches/amd64/local-blacklist-on-TSX-Haswell.diff: new patch from
Henrique de Moraes Holschuh to disable TSX on processors which might get
it disable through a microcode update. Closes: #762195.
Modified: glibc-package/trunk/debian/changelog
===================================================================
--- glibc-package/trunk/debian/changelog 2014-10-20 22:43:58 UTC (rev 6300)
+++ glibc-package/trunk/debian/changelog 2014-10-21 11:07:18 UTC (rev 6301)
@@ -21,6 +21,9 @@
#764274.
* Remove libc6-prof package as it's broken for years and there are better
way to profile code nowadays. Closes: #760450.
+ * patches/amd64/local-blacklist-on-TSX-Haswell.diff: new patch from
+ Henrique de Moraes Holschuh to disable TSX on processors which might get
+ it disable through a microcode update. Closes: #762195.
[ Helmut Grohne ]
* debian/patches/any/local-bootstrap-headers.diff: Update to handle
Added: glibc-package/trunk/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff
===================================================================
--- glibc-package/trunk/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff (rev 0)
+++ glibc-package/trunk/debian/patches/amd64/local-blacklist-on-TSX-Haswell.diff 2014-10-21 11:07:18 UTC (rev 6301)
@@ -0,0 +1,88 @@
+Intel TSX is broken on Haswell based processors (erratum HSD136/HSW136)
+and a microcode update is available to simply disable the corresponding
+instructions.
+
+While the responsability to continue or not using TSX should be left to
+the users, a live microcode update will disable the TSX instructions
+causing already started binaries to segfault. This patch simply disable
+Intel TSX (HLE and RTM) on processors which might receive a microcode
+update, so that it doesn't happen. We might expect newer steppings to
+fix the issue, and if it is not the case the corresponding processors
+will be shipped with TSX already disabled.
+
+Author: Henrique de Moraes Holschuh <hmh@debian.org>
+
+diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
+index db74d97..6f61ae6 100644
+--- a/sysdeps/x86_64/multiarch/init-arch.c
++++ b/sysdeps/x86_64/multiarch/init-arch.c
+@@ -26,7 +26,7 @@ struct cpu_features __cpu_features attribute_hidden;
+
+
+ static void
+-get_common_indeces (unsigned int *family, unsigned int *model)
++get_common_indeces (unsigned int *family, unsigned int *model, unsigned int *stepping)
+ {
+ __cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,
+ __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,
+@@ -36,6 +36,7 @@ get_common_indeces (unsigned int *family, unsigned int *model)
+ unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
+ *family = (eax >> 8) & 0x0f;
+ *model = (eax >> 4) & 0x0f;
++ *stepping = eax & 0x0f;
+ }
+
+
+@@ -47,6 +48,7 @@ __init_cpu_features (void)
+ unsigned int edx;
+ unsigned int family = 0;
+ unsigned int model = 0;
++ unsigned int stepping = 0;
+ enum cpu_features_kind kind;
+
+ __cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);
+@@ -56,7 +58,7 @@ __init_cpu_features (void)
+ {
+ kind = arch_kind_intel;
+
+- get_common_indeces (&family, &model);
++ get_common_indeces (&family, &model, &stepping);
+
+ unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
+ unsigned int extended_family = (eax >> 20) & 0xff;
+@@ -131,7 +133,7 @@ __init_cpu_features (void)
+ {
+ kind = arch_kind_amd;
+
+- get_common_indeces (&family, &model);
++ get_common_indeces (&family, &model, &stepping);
+
+ ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
+
+@@ -176,6 +178,14 @@ __init_cpu_features (void)
+ }
+ }
+
++ /* Disable Intel TSX (HLE and RTM) due to erratum HSD136/HSW136
++ on Haswell processors, to work around outdated microcode that
++ doesn't disable the broken feature by default */
++ if (kind == arch_kind_intel && family == 6 &&
++ ((model == 63 && stepping <= 2) || (model == 60 && stepping <= 3) ||
++ (model == 69 && stepping <= 1) || (model == 70 && stepping <= 1)))
++ __cpu_features.cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_RTM | bit_HLE);
++
+ __cpu_features.family = family;
+ __cpu_features.model = model;
+ atomic_write_barrier ();
+diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h
+index 793707a..e2745cb 100644
+--- a/sysdeps/x86_64/multiarch/init-arch.h
++++ b/sysdeps/x86_64/multiarch/init-arch.h
+@@ -40,6 +40,7 @@
+
+ /* COMMON_CPUID_INDEX_7. */
+ #define bit_RTM (1 << 11)
++#define bit_HLE (1 << 4)
+
+ /* XCR0 Feature flags. */
+ #define bit_XMM_state (1 << 1)
Modified: glibc-package/trunk/debian/patches/series
===================================================================
--- glibc-package/trunk/debian/patches/series 2014-10-20 22:43:58 UTC (rev 6300)
+++ glibc-package/trunk/debian/patches/series 2014-10-21 11:07:18 UTC (rev 6301)
@@ -50,6 +50,7 @@
alpha/cvs-unwind-backtrace.diff
amd64/submitted-rwlock-stack-imbalance.diff
+amd64/local-blacklist-on-TSX-Haswell.diff
arm/local-ioperm.diff
arm/local-lowlevellock.diff
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