r4607 - glibc-package/branches/eglibc-2.13/debian/patches/i386
Author: aurel32
Date: 2011-04-17 20:08:56 +0000 (Sun, 17 Apr 2011)
New Revision: 4607
Modified:
glibc-package/branches/eglibc-2.13/debian/patches/i386/cvs-cacheinfo.diff
Log:
Update patches/i386/cvs-cacheinfo.diff from upstream
Modified: glibc-package/branches/eglibc-2.13/debian/patches/i386/cvs-cacheinfo.diff
===================================================================
--- glibc-package/branches/eglibc-2.13/debian/patches/i386/cvs-cacheinfo.diff 2011-04-17 19:57:30 UTC (rev 4606)
+++ glibc-package/branches/eglibc-2.13/debian/patches/i386/cvs-cacheinfo.diff 2011-04-17 20:08:56 UTC (rev 4607)
@@ -1,3 +1,8 @@
+2011-04-03 Ulrich Drepper <drepper@gmail.com>
+
+ * sysdeps/x86_64/cacheinfo.c (intel_02_known): Fix typo in table.
+ * sysdeps/unix/sysv/linux/i386/sysconf.c (intel_02_known): Likewise.
+
2011-03-22 Ulrich Drepper <drepper@gmail.com>
* sysdeps/unix/sysv/linux/i386/sysconf.c (intel_check_word): Increment
@@ -15,6 +20,15 @@
index ff3cf9f..1f5d3b0 100644
--- a/sysdeps/unix/sysv/linux/i386/sysconf.c
+++ b/sysdeps/unix/sysv/linux/i386/sysconf.c
+@@ -135,7 +135,7 @@ static const struct intel_02_cache_info
+ { 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
+ { 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
+ { 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
+- { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
++ { 0xe2, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
+ { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
+ { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
+ { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
@@ -186,6 +186,57 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
/* No need to look further. */
break;
@@ -77,6 +91,15 @@
index 337444d..bd4be3d 100644
--- a/sysdeps/x86_64/cacheinfo.c
+++ b/sysdeps/x86_64/cacheinfo.c
+@@ -130,7 +130,7 @@ static const struct intel_02_cache_info
+ { 0xdc, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
+ { 0xdd, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
+ { 0xde, 12, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
+- { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
++ { 0xe2, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 },
+ { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 },
+ { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 },
+ { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 },
@@ -181,6 +181,57 @@ intel_check_word (int name, unsigned int value, bool *has_level_2,
/* No need to look further. */
break;
Reply to: