[Bug target/34091] [4.2/4.3 Regression] ICE in reload_cse_simplify_operands, at postreload.c:392
------- Comment #14 from danglin at gcc dot gnu dot org 2007-12-05 17:19 -------
The regression was introduced by the following change:
2005-11-21 Jan Hubicka <jh@suse.cz>
PR tree-optimization/24653
* tree-ssa-ccp.c (ccp_fold): Strip down useless conversions.
I have to think the target reload issues that the above exposes were latent.
The ICE has morphed a bit over time. This is the error at revision 107304.
dave@gsyprf11:~/gcc_test$ ../gcc-4.3/objdir/gcc/stage1/xgcc
-B../gcc-4.3/objdir/gcc/stage1/ -S -O2 s_texfilter.c
s_texfilter.c: In function 'sample_lambda_2d':
s_texfilter.c:166: error: unable to find a register to spill in class 'FP_REGS'
s_texfilter.c:166: error: this is the insn:
(insn 235 257 238 20 (set (subreg:SI (reg:HI 235) 0)
(fix:SI (fix:DF (reg:DF 68 %fr22 [234])))) 95 {fix_truncdfsi2}
(insn_list:REG_DEP_TRUE 233 (insn_list:REG_DEP_ANTI 227 (nil)))
(expr_list:REG_DEAD (reg:DF 68 %fr22 [234])
(nil)))
s_texfilter.c:166: internal compiler error: in spill_failure, at reload1.c:1901
There are two target issues involved here.
1) We can't allow mode paradoxical subregs in FP_REGS as this can't be handled
if the pseudo is spilled.
2) pa_secondary_reload() requests a secondary scratch register reload for
essentially everything when CLASS is FP_REGS. However, reload is treating
this reload as optional, resulting in spill failures and out of range REG+D
addresses. We do this because there is an asymmetry between the offsets
allowed for integer loads and stores, and floating point loads and stores.
Integer loads and stores support 14-bit offsets while PA 1.x floating point
loads and stores only support 5-bit offsets. It is a *MAJOR* compromise to
restrict integer loads and stores to 5-bit offsets. So, the target has always
used secondary reloads to rewrite floating-point loads and stores into a
form that provides correct code during register elimination.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34091
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